Agree with Tommy, SWD is ARM proprietary protocol part of ARM CoreSight, Nevertheless, somewhere or sometimes we could have a SoC that integrates together some ARM core with some RISC-V cores. In this hybrid SoC the debug port can either be:
* a JTAG chain with two TAPs (one for ARM and the other for RISC-V (this is supported by current OpenOCD code), or * a single JTAG/SWD TAP based on ARM CoreSight DAP. One of the AP (access ports) could be a JTAG-AP where the debug of the RISC-V core gets accessible. (today OpenOCD does not support JTAG-AP yet) So far I have not seen anything like that. --- ** [tickets:#378] SWD support for RISCV artchitecture** **Status:** new **Milestone:** 0.10.0 **Labels:** openocd **Created:** Wed Dec 28, 2022 07:00 AM UTC by Ashi Gupta **Last Updated:** Thu Dec 29, 2022 01:24 PM UTC **Owner:** nobody Hi, I want to know if SWD debug support has been added for RISCV architecture in openocd ? So far i know that JTAG support is only available. If not any plans in doing so ? --- Sent from sourceforge.net because openocd-devel@lists.sourceforge.net is subscribed to https://sourceforge.net/p/openocd/tickets/ To unsubscribe from further messages, a project admin can change settings at https://sourceforge.net/p/openocd/admin/tickets/options. Or, if this is a mailing list, you can unsubscribe from the mailing list.
