FWIW, Some Microchip FPGAs/SoC FPGAs can support hard and/or soft IP Cortex-M and RISC-V CPUs. But my recollection (from working for Microchip in the past) is that neither supported SWD. Certainly there is no SWD debug access to the RISC-V.
--- ** [tickets:#378] SWD support for RISCV artchitecture** **Status:** new **Milestone:** 0.10.0 **Labels:** openocd **Created:** Wed Dec 28, 2022 07:00 AM UTC by Ashi Gupta **Last Updated:** Thu Dec 29, 2022 05:20 PM UTC **Owner:** nobody Hi, I want to know if SWD debug support has been added for RISCV architecture in openocd ? So far i know that JTAG support is only available. If not any plans in doing so ? --- Sent from sourceforge.net because openocd-devel@lists.sourceforge.net is subscribed to https://sourceforge.net/p/openocd/tickets/ To unsubscribe from further messages, a project admin can change settings at https://sourceforge.net/p/openocd/admin/tickets/options. Or, if this is a mailing list, you can unsubscribe from the mailing list.
