in it often does something very strange and
not what I want. It would be nice IMO to nail down exactly what it
does, to avoid surprises.
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Christopher Head
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“run” pulse SRST and thereby reset
the other target as well? Does it do anything to convince the other
target to run or halt or otherwise when it comes out of reset? Are any
of the answers to these questions unintentional, or are they all
intended behaviour I can rely on?
Thanks,
--
Christopher
ctions into the binary for non-semihosting
purposes, because such halts would not match any FPB resource. I use
that capability regularly as a way to debug halt on certain error
conditions detected by the code, without spending FPB resources to do
so.
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pgp54uVKof0c6.pgp
Descr
hen the option
is there, I prefer to use it.
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that
matter).
Thanks to everyone working on OpenOCD!
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?
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** [tickets:#264] bindto half works when issued after init**
**Status:** new
**Milestone:** 0.9.0
**Created:** Mon Apr 20, 2020 05:56 PM UTC by Christopher Head
**Last Updated:** Mon Apr 20, 2020 05:56 PM UTC
**Owner:** nobody
When the `bindto` command is issued after the `init` command
opular.
Gitlab offers CI minutes as part of their free plan, and their CI
offering runs things inside Docker, but that may not be appropriate for
quite what you need.
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Christopher Head
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solution these days, and runnable under many hosts—so that
the simulator can run in the one environment where it’s known to work
well, and have the OpenOCD instance running under Travis connect to it?
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two processors in a JTAG chain), it
would be extremely confusing to see mdX output showing up in the connection for
the other processor!
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.
Still not sure what the right fix is. I’m not an expert on the guts of JimTCL.
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ide to NULL. Which of course breaks the
event handler’s attempt to operate on the proper target in subsequent
operations.
What is the proper fix for this? Should this be changed in OpenOCD, or should I
write my script a different way?
Thanks!
--
Christopher Head
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supposed to print it, or should the
framework that calls the handler be printing a message if the command handler
returns nonzero?
Thanks!
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It looks like the desync is still happening. It seems that sometimes SF catches
up a bit, but then Zylin gets ahead of it again. They used to always be right
together.
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else that would like to have a more active versioning scheme
> for the project?
Make that three. I think a couple of times a year would be nice, if not
more often.
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O
the case for quite a while now; normally, before,
they always had the same head commit.
Sorry for the noise if this is expected!
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ers (and things that connect to them) expect that the system has been fully
initialized and is ready to talk to.
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e? Sounds like a nice thing to
enhance.
>I'm not sure if threads are part of the core file data. If they're not,
>GDB
>would not be able to interpret them from the core file without help
>from
>OpenOCD.
They are.
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life better.
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Forgot to mention that this is fixed. I don’t seem to have any controls to
close the ticket though.
---
** [tickets:#168] examine-end event handler unable to access memory with two
targets**
**Status:** new
**Milestone:** 0.9.0
**Created:** Fri Nov 17, 2017 07:19 AM UTC by Christopher Head
ly.
Not an issue at all for me, and probably many others, since my code is in Flash.
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e
coherence around debug accesses to
memory? If the policy is that they should be coherent, then I could probably
provide a patch making this happen for Cortex M at some point.
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archives, the discussion kind of
ended without any real resolution, and it seems no workaround has been
implemented. Does anyone know the situation here? Is someone working on a
workaround? Was there a decision to intentionally not implement one?
Thanks!
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e to use a stock OpenOCD.
Does this seem unreasonable?
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engaging tech sites
done by TCL? It would shorten the development cycle of ports to new RTOSs as
well as just new ports.
I don’t suspect that any of this work is so performance-critical that using TCL
would slow it down top much.
--
Christo
vel@lists.sourceforge.net> wrote:
>Did you use 'adapter_khz 8000' for the last test?
>I'm afraid that 8 MHz is too much (WAITs during reset-init).
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was
not enough), I got no more WAITs and 150 kiB/s.
So, what now? Is that setting something that belongs in the F7 target file?
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Check out the vibra
.
Without algorithm: 1 DAP WAIT, 55.177 kiB/s.
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engaging tech sites, Slashdot.org! http
, 4463 makes this change. I get one DAP WAIT, but no more, with my
FTDI at 2M, and programming works fine and verifies properly (at least, it does
once I work around the fact that my nasty multi target hacks have gone from
necessary to counterproductive).
--
Christopher Head
s
e manual
or datasheet. Just curious.
Side note, I saw that the F4 config file sets the upper four bits of
RCC_PLLCFGR to zero, but the reference manual says they should be kept at their
reset value and that the reset value of the register is 0x24003010. Maybe it
doesn’t matter, but what if ST pu
in the last week or two. I can
look up the exact commit ID tomorrow if you want.
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ot;good" programming adapter is used) anyway.
Fair enough. I never wanted to change the default anyway. I just wanted to
provide the user with the ability to change it should they wish. Does this seem
reasonable to you?
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et, which it would not be with ORUNDETECT
cleared, and you have to clear the sticky status bit.
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correct. My sample was about half a meg
of data.
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t ECC errors—we could set chip width to 1 for
F2/F4/F7 and 16 for H7, and the Flash code could recognize that difference and
act accordingly; meanwhile bus width could be 1, 2, 4, or 8 to set the
parallelism.
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Christopher Head
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On Mon, 26 Feb 2018 16:23:08 -0800
Christopher Head <open...@chead.ca> wrote:
> 2. Allow the user to set the parallelism level with a new stm32f2x
> subcommand, since only the board config knows what VDD is being
> supplied.
Having thought it over a little more, perhaps we co
config knows what VDD is being supplied.
3. Move the CR and SR stuff outside the write loop in direct mode, changing the
entire data write operation into a single target_write_memory call directly to
the Flash address.
Thoughts? Objections?
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and perhaps damage the I/O driver, up to at worst set your desk
on fire. I’m not totally convinced that allowing an attacker to do *anything*
with OpenOCD is safe.
--
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Descript
commands when processing untrusted
>input.
That sounds awfully difficult to get right. After all, if I want to steal your
top secret document, all I need available to me is PROGRAM (to put a copy of
said document into the microcontroller) followed by MDW (to read it back).
--
Christophe
k over pipes, but only stdio AFAIK, and there are too many interfaces to
handle them all that way (especially with multiple taps).
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attacks would work if you had to, say, type a password
before OpenOCD would accept your Telnet (or GDB, or TCL, or …) session.
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Check
---
** [tickets:#168] examine-end event handler unable to access memory with two
targets**
**Status:** new
**Milestone:** 0.9.0
**Created:** Fri Nov 17, 2017 07:19 AM UTC by Christopher Head
**Last Updated:** Fri Nov 17, 2017 07:19 AM UTC
**Owner:** nobody
I have a board with an STM32F7
:** new
**Milestone:** 0.9.0
**Created:** Fri Nov 17, 2017 07:19 AM UTC by Christopher Head
**Last Updated:** Fri Nov 17, 2017 07:19 AM UTC
**Owner:** nobody
I have a board with an STM32F7 on it. My target script sources the shipped
stm32f7x.cfg target script. Everything works perfectly. No problems
examine-end handler.
Attached, anonymized, find my config file. I’m using OpenOCD 0.10.0.
Any thoughts?
Thanks!
--
Christopher Head
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of where this happens. Although I
initially wanted this for a custom port, the same sort of complexity
even shows up in one of the official ports.
--
Christopher Head
signature.asc
Descr
o do the whole TCL conversion myself, it might take a
while, so it would be great to know whether such a change would be
accepted before starting work, and also whether there are any other
people interested in doing any of this work.
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