On March 10, 2018 11:25:15 PM PST, Tomas Vanek via OpenOCD-devel <openocd-devel@lists.sourceforge.net> wrote: >I wouldn't call this case as an obscure one. The reason could be >insufficient device clock rate, >not very high adapter_khz. Anyway all these cases could be solved by >configuring >the device properly.
I don’t think this is related to device clock speed. You will get a WAIT if there is a bus stall, and Flash programming is self timed. So I think it depends on the 16 (typical) to 100 (maximum) microsecond word programming time. If you can deliver 35 bits (length of a DRSCAN) plus the TMS transitions within the word programming time, then you will get a WAIT reply. >One more concern: If programming by algo is usable on SWD only, JTAG >users should >set WORKAREASIZE to zero. But algos are used for verify, blank check >and >external memories as well. >This may impose a big penalty... Yes, this is unfortunate. The verify algorithm works fine for me, but of course it is a synchronous, rather than asynchronous, algorithm, so any silicon erratum exposed by bus arbitration or other weirdness would not apply there. In any case, 4463 makes this change. I get one DAP WAIT, but no more, with my FTDI at 2M, and programming works fine and verifies properly (at least, it does once I work around the fact that my nasty multi target hacks have gone from necessary to counterproductive). -- Christopher Head
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