Sent: Friday, March 10, 2023 7:08 AM
To: openocd-devel@lists.sourceforge.net
Subject: [openocd:tickets] #378 SWD support for RISCV artchitecture
One update on the (almost off-topic) discussion started with this ticket
"Allwinner R128 wireless SoC features 64-bit RISC-V core, Arm Cortex-M33
One update on the (almost off-topic) discussion started with this ticket
"Allwinner R128 wireless SoC features 64-bit RISC-V core, Arm Cortex-M33 core,
and HiFi 5 audio DSP"
https://www.cnx-software.com/2023/03/06/allwinner-r128-wireless-soc-features-64-bit-risc-v-core-arm-cortex-m33-core-and-hifi
Cinly,
yes, that's a grey area out of tech domain and more on lawyer sides.
But I see Risc-V cores used as control integrated in HW accelerators, like GPUs
or AI. People that build SoCs could feel comfortable keeping the ARM main
processor while integrating such third-party accelerators.
This kin
Sent: Friday, December 30, 2022 1:20 AM
To: openocd-devel@lists.sourceforge.net
Subject: [openocd:tickets] #378 SWD support for RISCV artchitecture
Agree with Tommy, SWD is ARM proprietary protocol part of ARM CoreSight,
Nevertheless, somewhere or sometimes we could have a SoC that integrates
t
Agree with Tommy, SWD is ARM proprietary protocol part of ARM CoreSight,
Nevertheless, somewhere or sometimes we could have a SoC that integrates
together some ARM core with some RISC-V cores. In this hybrid SoC the debug
port can either be:
* a JTAG chain with two TAPs (one for ARM and the othe
i found this thread for SWD debug support using SPI for esp32 (have not tried
anything though)
https://esp32.com/viewtopic.php?t=3627
---
** [tickets:#378] SWD support for RISCV artchitecture**
**Status:** new
**Milestone:** 0.10.0
**Labels:** openocd
**Created:** Wed Dec 28, 2022 07:00 AM UT
oh ok. Will check on cJTAG support under this link
(https://github.com/riscv/riscv-openocd)
i think ESP32 might have SWD support (not sure though).
---
** [tickets:#378] SWD support for RISCV artchitecture**
**Status:** new
**Milestone:** 0.10.0
**Labels:** openocd
**Created:** Wed Dec 28, 2
You probably want to look at the RISC-V OpenOCD fork for latest RISC-V support.
https://github.com/riscv/riscv-openocd
Changes there periodically get upstreamed to here (the master OpenOCD project).
As far as I know, cJTAG support has been added there.
I don't think that SWD support will ever be
---
** [tickets:#378] SWD support for RISCV artchitecture**
**Status:** new
**Milestone:** 0.10.0
**Labels:** openocd
**Created:** Wed Dec 28, 2022 07:00 AM UTC by Ashi Gupta
**Last Updated:** Wed Dec 28, 2022 07:00 AM UTC
**Owner:** nobody
Hi,
I want to know if SWD debug support has been
