One update on the (almost off-topic) discussion started with this ticket "Allwinner R128 wireless SoC features 64-bit RISC-V core, Arm Cortex-M33 core, and HiFi 5 audio DSP" https://www.cnx-software.com/2023/03/06/allwinner-r128-wireless-soc-features-64-bit-risc-v-core-arm-cortex-m33-core-and-hifi-5-audio-dsp/
While the article reports a SoC with Risc-V + Cortex-M33, I think this should be a dual silicon chips in a single package because I don't believe the same technology can fit for both 800MHz CPU and WiFi/BT radio. For me the Cortex-M33 is in the same chip with the WiFi/BT, while Risc-V and the other digital functions are in another chip. Anyway, some hybrid is popping out. --- ** [tickets:#378] SWD support for RISCV artchitecture** **Status:** new **Milestone:** 0.10.0 **Labels:** openocd **Created:** Wed Dec 28, 2022 07:00 AM UTC by Ashi Gupta **Last Updated:** Sat Jan 07, 2023 11:34 AM UTC **Owner:** nobody Hi, I want to know if SWD debug support has been added for RISCV architecture in openocd ? So far i know that JTAG support is only available. If not any plans in doing so ? --- Sent from sourceforge.net because openocd-devel@lists.sourceforge.net is subscribed to https://sourceforge.net/p/openocd/tickets/ To unsubscribe from further messages, a project admin can change settings at https://sourceforge.net/p/openocd/admin/tickets/options. Or, if this is a mailing list, you can unsubscribe from the mailing list.
