Cinly, yes, that's a grey area out of tech domain and more on lawyer sides. But I see Risc-V cores used as control integrated in HW accelerators, like GPUs or AI. People that build SoCs could feel comfortable keeping the ARM main processor while integrating such third-party accelerators. This kind of hybrid SoC are going to get common, and I agree with recent statement from Risc-V CEO: "Risc-V is inevitable!". And ARM has to face the reality. If they are not flexible enough to allow such hybrid SoC, more people will consider to drop ARM completely. Then, on which config will lawyers agree? A SoC with two independent debug ports? Two independent TAPs on the same JTAG chain? An ARM DAP with a bridge JTAG-AP? I don't know, we will see it. Probably sooner than we expect. Here we are just speculating and bla-bla.
Having the ARM core as intermediate controller for the Risc-V... possible but hard to use during SoC verification. You need one core (ARM one) up and running to test the other cores. Designer will prefer a direct path to each core. --- ** [tickets:#378] SWD support for RISCV artchitecture** **Status:** new **Milestone:** 0.10.0 **Labels:** openocd **Created:** Wed Dec 28, 2022 07:00 AM UTC by Ashi Gupta **Last Updated:** Thu Dec 29, 2022 06:05 PM UTC **Owner:** nobody Hi, I want to know if SWD debug support has been added for RISCV architecture in openocd ? So far i know that JTAG support is only available. If not any plans in doing so ? --- Sent from sourceforge.net because openocd-devel@lists.sourceforge.net is subscribed to https://sourceforge.net/p/openocd/tickets/ To unsubscribe from further messages, a project admin can change settings at https://sourceforge.net/p/openocd/admin/tickets/options. Or, if this is a mailing list, you can unsubscribe from the mailing list.
