Re: [PEDA] file formats for PCB manufacturers

2001-07-20 Thread DUTTON Phil

Jim,

There are more than 1000 Certified Designers worldwide.
Personally, I'm proud to be one of them. As far as I know,it is the only
international qualification, recognising the baseline skills and knowledge
required to be a board designer.

Phil.


Phil Dutton C.I.D.
Senior CAD Technician
IPC Certified Interconnect Designer

Tenix Defence Systems Pty Ltd 
Systems Division - Adelaide
Second Avenue, Technology Park,
Mawson Lakes.  SOUTH AUSTRALIA  5095

-Original Message-
From: Jim McGrath [mailto:[EMAIL PROTECTED]]
Sent: Friday, July 20, 2001 7:20 AM
To: Protel EDA Forum
Subject: Re: [PEDA] file formats for PCB manufacturers


Brad,

If I recall correctly the IPC-D-350 was supposed to be a format that would
allow any CAD package to exchange data (in fact whole designs) with any
other CAD package. Talk about Utopia! It never caught on or hasn't
yet.

The IPC needs more teeth to be truly our guiding force. Most will agree that
their specs are a good place to start but not the end all in information.
Unless

the many component makers adopt their standards they cannot be completely
trusted. I can't tell you how many times A part is call SOIC-16 and actually
is quite differnet in reallity.

Another good example is the design cetification. How many Designers are
certifiied worldwide? 50 maybe?

Don't get me wrong I would LOVE to have a definitive force in our field
but I just don't see it.

I hope I haven't offended anyone but that is the way I feel.

Regards,

Jim McGrath
CAD Connections, Inc.

Brad Velander wrote:

 Jim,
 to a degree you are correct but I don't see where they make any
 serious money from adaptation of their standards. The moneys derived from
 selling the standards to people who might develop output software and then
a
 limited number of designers who have to know what the standard says, at
best
 only covers their expenses. Remember somebody had to write the standard
and
 meet with the other authors, sleep , eat and drink while doing so.

 Brad Velander,
 Lead PCB Designer,
 Norsat International Inc.,
 #300 - 4401 Still Creek Dr.,
 Burnaby, B.C., V5C 6G9.
 Tel. (604) 292-9089 direct
 Fax (604) 292-9010
 website www.norsat.com


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Re: [PEDA] Drawing polygons that contain arcs, is more control po ssible?

2001-07-20 Thread Richard Thompson

Hi Brad

/\say this is the track i just placed (for the outline)
net name = outline
| /   
|/(ooops, forgot the key part)  add a small track named
fill inside the
  area, then drag a polygon completely over it (net name
= fill etc) it will only fill inside the area.( outside is dead copper)
then safely remove the outline tracks.  

this works for me assuming i don't need to repour the polygon. :-)

i would agree though that the arcs are a pain in the a*s*

Rich

   I don't understand your methodology. If you drag the polygon over
 the track outline of the same net and select  remove dead copper. When you
 repour if the polygon touches the track outline then it is not dead copper
 and does not get removed. It can fill inside the track outline and outside
 of it as long as the pour segments can touch that outline somewhere.
 Something is missing here because I just can't follow your lead.
 
 Brad Velander,
 Lead PCB Designer,
 Norsat International Inc.,
 #300 - 4401 Still Creek Dr.,
 Burnaby, B.C., V5C 6G9.
 Tel. (604) 292-9089 direct
 Fax (604) 292-9010
 website www.norsat.com
 
 
  -Original Message-
  From: Richard Thompson [mailto:[EMAIL PROTECTED]]
  Sent: Thursday, July 19, 2001 5:43 AM
  To: Protel EDA Forum
  Subject: Re: [PEDA] Drawing polygons that contain arcs, is 
  more control
  po ssible?
  
  
  hi brad
  
  if i understand corrrectly, (excuse me if i don't) when 
  placing arcs on a
  polygon you cannot press space to change the start/end mode 
  (as you can
  when placing a track) therefore the polygon can be whatever 
  protel feels
  like at the time :-)   
  when i am placing polygon outlines i add a new net called 
  outline and
  fill  i draw around where i want the curved polygon etc with a track
  segment (which is easier as the space bar works) then i drag 
  a polygon fill
  over the top (set its net to be fill) and then select 
  remove dead copper
  etc in the polygon options.  lastly remove the temporary 
  outline voila one
  curved polygon exactly how you need it.
  
  Rich

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Re: [PEDA] more footprints

2001-07-20 Thread HxEngr
 


Re: [PEDA] more footprints

2001-07-20 Thread Greg Olson


- Original Message -
From: Dan G. [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Friday, July 20, 2001 9:23 AM
Subject: [PEDA] more footprints


 Greetings all,

   When editing a library part, the component description only allows 4
 footprints to be associated with that part. This can be seen again when
 placing a part on a schematic, giving only four choices of footprints
 (ie:resistors) plus whatever you can remember.

   My question is: Is there a way of increasing the number of listed
 footprints without having to memorize, write down or search the pcb
 library for the unlisted footprints?

 Regards,
   Dan

Dan:

Instead of having only 1 Resistor schematic part, make several, ie..
1/4WResistor, 1/2WResistor, etc... You should be able to get away with
less than 4 footprints for each of these, even considering through hole and
surface mount.

Greg

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[PEDA] autorouter

2001-07-20 Thread Richard Thompson

Hi guys,

Can anyone explain why the autorouter is giving me this error message
please?

one or more connections cannot be routed due to design rule violations

this happens even if i try to just route a single component or net as well
as the whole board.  i have done a done a complete drc (and online checking
is active) there are no errors/violations reported.  i have tried removing
all of the design rules and it still refuses to play ball.

any ideas?

Rich

Richard Thompson
BLT Industries



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[PEDA] Gerber specification

2001-07-20 Thread Ted Tontis

Yesterday there was a thread on file formats for PCB manufacturers. Here is
where you can find the gerber specification in .pdf format.
http://www.barco.be/ets/data/rs274xc.pdf

Regards,

Ted Tontis C.I.D.
Engage Networks
316 N. Milwaukee Street
Suite 214
Milwaukee WI, 53202
PH 414-273-7600 ext. 7607
FX 414-273-7601

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Re: [PEDA] more footprints

2001-07-20 Thread Madhu Annapragada

Well...I have been tempted to use a single schematic object (say a Schottky)
and associate it with a number of different footprints (DO-41, C-16,
DO-204AR, TO-220AC, D-PAK.. so on). Maybe that is what the original poster
was asking about??
Madhu


-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]
Sent: Friday, July 20, 2001 9:35 AM
To: Protel EDA Forum
Subject: Re: [PEDA] more footprints


In a message dated 7/20/01 9:28:08 AM Eastern Daylight Time, [EMAIL PROTECTED]
writes:


   When editing a library part, the component description only allows 4
 footprints to be associated with that part. This can be seen again when
 placing a part on a schematic, giving only four choices of footprints
 (ie:resistors) plus whatever you can remember.

   My question is: Is there a way of increasing the number of listed
 footprints without having to memorize, write down or search the pcb
 library for the unlisted footprints?



Are you perhaps misunderstanding the use of this field? I don't know of any
component that comes in more than four different footprints, certainly not
four that I would use. I'm sure someone can come up with a counterexample,
or
perhaps you can explain some unusual use for this field.

Steve Hendrix


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Re: [PEDA] Drawing polygons that contain arcs, is more control po ssible?

2001-07-20 Thread Brad Velander

Thanks Richard,
now I got it. I had missed the effect of the two nets. Thanks for
re-explaining it, I must of been having one of those challenged moments.
That is tricky.

Brad Velander,
Lead PCB Designer,
Norsat International Inc.,
#300 - 4401 Still Creek Dr.,
Burnaby, B.C., V5C 6G9.
Tel. (604) 292-9089 direct
Fax (604) 292-9010
website www.norsat.com


 -Original Message-
 From: Richard Thompson [mailto:[EMAIL PROTECTED]]
 Sent: Friday, July 20, 2001 1:07 AM
 To: Protel EDA Forum
 Subject: Re: [PEDA] Drawing polygons that contain arcs, is 
 more control
 po ssible?
 
 
   Hi Brad
 
   /\say this is the track i just placed (for 
 the outline)
 net name = outline
   | /   
   |/(ooops, forgot the key part)  add a small 
 track named
 fill inside the
     area, then drag a polygon completely over 
 it (net name
 = fill etc) it will only fill inside the area.( outside is 
 dead copper)
 then safely remove the outline tracks.  
 
   this works for me assuming i don't need to repour the 
 polygon. :-)
 
   i would agree though that the arcs are a pain in the a*s*
 
   Rich
 

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Re: [PEDA] more footprints

2001-07-20 Thread Brad Velander

Steve,
It would be very easy to get more then 4 footprints if a person was using a
generic transistor symbol. Especially if they are numbering pins using the
EBC/DGS method. Using that method you could then come up with probably no
less then 40 to 50 orientations/footprints. (One reason that I don't use
that method, been there, done that many years ago.)
In answer to the orignal question, I have never heard of any method
to support more footprints within a library symbol, I doubt there is one.

Brad Velander,
Lead PCB Designer,
Norsat International Inc.,
#300 - 4401 Still Creek Dr.,
Burnaby, B.C., V5C 6G9.
Tel. (604) 292-9089 direct
Fax (604) 292-9010
website www.norsat.com


 -Original Message-
 From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]
 Sent: Friday, July 20, 2001 9:35 AM
 To: Protel EDA Forum
 Subject: Re: [PEDA] more footprints
 
 Are you perhaps misunderstanding the use of this field? I 
 don't know of any
 component that comes in more than four different footprints, 
 certainly not
 four that I would use. I'm sure someone can come up with a 
 counterexample,
 or
 perhaps you can explain some unusual use for this field.
 
 Steve Hendrix

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Re: [PEDA] autorouter

2001-07-20 Thread Brooks,Bill

Hi Richard,
I would suggest that you check your setup on Design Rules for the
autorouter. It may be that the spacing you are telling the program to
maintain is so large that there are no paths for the router to take that
would not violate the spacing rule. 
- Bill Brooks

Bill Brooks 
PCB Design Engineer 
DATRON WORLD COMMUNICATIONS INC.
3030 Enterprise Court 
Vista, CA 92083 
Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510 
mailto:[EMAIL PROTECTED] 
IPC Designers Council, San Diego Chapter 
http://www.ipc.org/SanDiego/
http://home.fda.net/bbrooks/pca/pca.htm



-Original Message-
From: Richard Thompson [mailto:[EMAIL PROTECTED]]
Sent: Friday, July 20, 2001 7:08 AM
To: Protel EDA Forum
Subject: [PEDA] autorouter


Hi guys,

Can anyone explain why the autorouter is giving me this error message
please?

one or more connections cannot be routed due to design rule violations

this happens even if i try to just route a single component or net as well
as the whole board.  i have done a done a complete drc (and online checking
is active) there are no errors/violations reported.  i have tried removing
all of the design rules and it still refuses to play ball.

any ideas?

Rich

Richard Thompson
BLT Industries



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Re: [PEDA] Bow Twist

2001-07-20 Thread Brian Guralnick

On normal 2 layer PCBs, I've seen my boards stay flat  fine through the SMT mounting 
process, but after the wave pass, they would have an arch in them.  When I changes the 
design to a 4 layer board, it no longer happened.  I think the material on the 4 layer 
was of better refinement than the 2 layer, even though both boards came from the same 
manufacture.

_
Brian Guralnick



- Original Message - 
From: Dennis Saputelli [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Thursday, July 19, 2001 6:49 PM
Subject: Re: [PEDA] Bow  Twist


| I've occasionally had boards received nice and flat from board fab, and
| then have substantial bow and twist after assembly
| 
| Dennis Saputelli
| 
| Brian Guralnick wrote:
|  
|  Also, bow  twist for a flex PCB is a whole new ball game.
|  
|  _
|  Brian Guralnick
|  
|  - Original Message -
|  From: Harry Selfridge [EMAIL PROTECTED]
|  To: Protel EDA Forum [EMAIL PROTECTED]
|  Sent: Thursday, July 19, 2001 2:33 AM
|  Subject: Re: [PEDA] Bow  Twist
|  
| 
| 
| -- 
| ___
| www.integratedcontrolsinc.comIntegrated Controls, Inc.
|tel: 415-647-04802851 21st Street  
|   fax: 415-647-3003San Francisco, CA 94110
| 
| 

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Re: [PEDA] Bow Twist

2001-07-20 Thread Harry Selfridge

It sounds like your wave soldering process is not set up correctly.  The 
boards should be evenly heated through before wave soldering, then cooled 
uniformly.

What you describe happens when the board is heated mostly on the solder 
wave side, causing softening of the resin and differential expansion top to 
bottom.  As soon as the board leaves the soldering station, it is probably 
cooled rapidly by ambient exposure or forced air cooling.  This is a recipe 
for guaranteed warping.  Your multilayer boards are more tolerant of the 
abuse because they have more thermal mass ( they can't heat or cool as 
rapidly throughout the bulk material ).  The inner layers are essentially 
holding things together for you; however, I'll bet the four layer boards 
are also warping - just not as noticeably.  If you want to see the physics 
in action for yourself, try taking a scrap board and heating just the top 
side with a heat gun - you'll make a 'Frisbee' of it fairly quickly.

Material, layup, copper volume, and differential temperature are the 
ingredients you need to mix carefully to avoid warp, bow, and twist.

Regards - Harry

At 11:52 AM 7/20/01 -0400, you wrote:
On normal 2 layer PCBs, I've seen my boards stay flat  fine through the 
SMT mounting process, but after the wave pass, they would have an arch in 
them.  When I changes the design to a 4 layer board, it no longer 
happened.  I think the material on the 4 layer was of better refinement 
than the 2 layer, even though both boards came from the same manufacture.
_
Brian Guralnick

- Original Message -
From: Dennis Saputelli [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Thursday, July 19, 2001 6:49 PM
Subject: Re: [PEDA] Bow  Twist

| I've occasionally had boards received nice and flat from board fab, and
| then have substantial bow and twist after assembly
snip

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Re: [PEDA] Bow Twist

2001-07-20 Thread Dennis Saputelli

yes I'm sure that was the problem on a few occasions

Dennis Saputelli

Harry Selfridge wrote:
 
 It sounds like your wave soldering process is not set up correctly.  The
 boards should be evenly heated through before wave soldering, then cooled
 uniformly.
 
 What you describe happens when the board is heated mostly on the solder
 wave side, causing softening of the resin and differential expansion top to
 bottom.  As soon as the board leaves the soldering station, it is probably
 cooled rapidly by ambient exposure or forced air cooling.  This is a recipe
 for guaranteed warping.  Your multilayer boards are more tolerant of the
 abuse because they have more thermal mass ( they can't heat or cool as
 rapidly throughout the bulk material ).  The inner layers are essentially
 holding things together for you; however, I'll bet the four layer boards
 are also warping - just not as noticeably.  If you want to see the physics
 in action for yourself, try taking a scrap board and heating just the top
 side with a heat gun - you'll make a 'Frisbee' of it fairly quickly.
 
 Material, layup, copper volume, and differential temperature are the
 ingredients you need to mix carefully to avoid warp, bow, and twist.
 
 Regards - Harry


-- 
___
www.integratedcontrolsinc.comIntegrated Controls, Inc.
   tel: 415-647-04802851 21st Street  
  fax: 415-647-3003San Francisco, CA 94110

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Re: [PEDA] Bow Twist

2001-07-20 Thread Pullen, Bill

Try increasing the pre-heater temp or slow the conveyer speed.  You need the
top side of the board at 200 degrees F before contacting the wave.

Bill Pullen


-Original Message-
From: Harry Selfridge [mailto:[EMAIL PROTECTED]]
Sent: Friday, July 20, 2001 12:54 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Bow  Twist


It sounds like your wave soldering process is not set up correctly.  The 
boards should be evenly heated through before wave soldering, then cooled 
uniformly.

What you describe happens when the board is heated mostly on the solder 
wave side, causing softening of the resin and differential expansion top to 
bottom.  As soon as the board leaves the soldering station, it is probably 
cooled rapidly by ambient exposure or forced air cooling.  This is a recipe 
for guaranteed warping.  Your multilayer boards are more tolerant of the 
abuse because they have more thermal mass ( they can't heat or cool as 
rapidly throughout the bulk material ).  The inner layers are essentially 
holding things together for you; however, I'll bet the four layer boards 
are also warping - just not as noticeably.  If you want to see the physics 
in action for yourself, try taking a scrap board and heating just the top 
side with a heat gun - you'll make a 'Frisbee' of it fairly quickly.

Material, layup, copper volume, and differential temperature are the 
ingredients you need to mix carefully to avoid warp, bow, and twist.

Regards - Harry

At 11:52 AM 7/20/01 -0400, you wrote:
On normal 2 layer PCBs, I've seen my boards stay flat  fine through the 
SMT mounting process, but after the wave pass, they would have an arch in 
them.  When I changes the design to a 4 layer board, it no longer 
happened.  I think the material on the 4 layer was of better refinement 
than the 2 layer, even though both boards came from the same manufacture.
_
Brian Guralnick

- Original Message -
From: Dennis Saputelli [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Thursday, July 19, 2001 6:49 PM
Subject: Re: [PEDA] Bow  Twist

| I've occasionally had boards received nice and flat from board fab, and
| then have substantial bow and twist after assembly
snip

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[PEDA] importing power pcb files

2001-07-20 Thread Ted Tontis

I checked the archive for a thread regarding this but  its not
there. I want to take a power PCB v3.6 file and import it into protel. I was
told at one time this could be done?
How far back does the archive go? is there a more extensive one, or
am I looking at the wrong archive?

Thank you,

Ted Tontis C.I.D.
Engage Networks
316 N. Milwaukee Street
Suite 214
Milwaukee WI, 53202
PH 414-273-7600 ext. 7607
FX 414-273-7601

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