Re: [PEDA] Gerber Import / Viewing in P99SE
Hello, I had a similar problem with the Gerber Files generated from an unknown program on a Apple Computer. In my case, the Aperture Table was in the wrong fomat. I wrote a Perl Script for conversion of these tables, then it worked. Dipl. Ing. J rg Guttmann eMail: [EMAIL PROTECTED] === Visit our Web Site: http://www.imar-navigation.de === iMAR GmbH Gesellschaft f r inertiale Mess-, Automatisierungs- und Regelsysteme Systems for Inertial Measuring, Automation and Control Schlackenbergstrasse 41 D-66386 St. Ingbert / Germany Tel.: +49-(0)6894-9657-34 Fax : +49-(0)6894-9657-22 - Original Message - From: Nick Papas [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Monday, February 10, 2003 4:36 AM Subject: Re: [PEDA] Gerber Import / Viewing in P99SE I would greatly appreciate a copy of your macro. Thanks in advance, Nick Papas -Original Message- From: Ian Capps [mailto:[EMAIL PROTECTED]] Sent: Tuesday, 21 January 2003 16:32 To: Protel EDA Forum Subject: Re: [PEDA] Gerber Import / Viewing in P99SE Terry As Brad as said in his reply the gerbers need to be generated from protel in the first place to be directly importable. For some gerber files you can get away with changing the header and for others it takes a bit more fuddling around. I have a word macro that I have used in the past. It's very clunky but has worked every time if you want it let me know. Ian Capps - Original Message - From: Terry Creer [EMAIL PROTECTED] To: Protel EDA Forum (E-mail) [EMAIL PROTECTED] Sent: Tuesday, January 21, 2003 8:52 AM Subject: [PEDA] Gerber Import / Viewing in P99SE Greetings all, I remember someone mentioning a while ago about importing Gerber files to view in P99SE. I was wondering what perhaps I am doing wrong... First, I create a new PCB. From the file menu, I select Import. I then select .g?? single gerber from the drop down box and then select the gerber file I want to import. I hit open and voila! Nothing. Same happens if I select .g?? batch gerber from the drop down box. Any ideas would be much appreciated, thanks! Terry Creer * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] BOM part fields shown as *
To resonate with what Nick wrote. (1) So I wonder what would happen if I managed to get rid of all the * in the part fields in a schematic. Would there be a problem? I'm thinking of something like the CSV bom output might get borked or something like that. For the reasons that Nick cites, you can't do a global edit on because theres no way to select only a * since its a wildcard. However, getting rid of those * is possible. a. Export all fields to a spreadsheet, delete all *, and then import back to schematic. This can be a very flaky process but can be made to work with enough tries. One of the problems with this is having to suffer through the protel spread sheet editor. b. When placing a sch component, hit the INSERT key before the part is placed. Edit all the part fields to get rid of the * . Now the default fields will be empty instead of having a * . (2) Its too bad that protel only gave us two kinds of fields: Library - read only at sch level. Values are drawn from library. Part - can change at sch level. No values are drawn from library, only the name of the field. I've often wished for a third type in between the two that can be changed at the sch level but has a default value that is drawn from the library. my $0.2 Dave Lewis Nick Papas [EMAIL PROTECTED] on 02/09/2003 07:36:11 PM Please respond to Protel EDA Forum [EMAIL PROTECTED] To:Protel EDA Forum [EMAIL PROTECTED] cc: Subject: Re: [PEDA] BOM part fields shown as * Sounds like you may have your additional component information defined in your Part Field Names. These Part Field Names can be edited in the library editor to give a name to each part field instead of the default Part Field 1 - Part Field 16, but this information does not appear in the BOM list. You should either place your required information in the Library Fields (otherwise known as Read Only Fields) within the library editor, or in the Part Fields within the schematic editor. Then, when generating your BOM, simply activate the appropriate library or part fields to be included in the list, and you should find your additional component information included. By the way, Protel (in their infinite wisdom) have defaulted any blank fields with *, making it extremely difficult to use the * wildcard to search these fields, but just like lots of other issues within Protel, I'm sure you can find a work-around. With Kind Regards Nick Papas -Original Message- From: Mikael Johansson [mailto:[EMAIL PROTECTED]] Sent: Sunday, 9 February 2003 18:07 To: [EMAIL PROTECTED] Subject: [PEDA] BOM part fields shown as * Hello I'm a newbie trying to evaluate Protel 99SE SP6. I've created a component library where the part fields store supplier, order codes etc. When I create a BOM from the schematic the very same part fields only contain an asterisk '*'. If I doubleclick on a component in the schematic I can see my order codes ... as well as a column with the '*'. How do I copy my order codes... to the columns shown in the BOM (for all components in the schematic)? Mikael Johansson _ STOP MORE SPAM with the new MSN 8 and get 2 months FREE* http://join.msn.com/?page=features/junkmail * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Buses
At 10:16 PM 2/6/2003, Peter W. Richards wrote: Can someone explain to me how buses hierarchy work in Protel (99SE sp6?) It can be a tad tricky. The key is in understanding how the netlister recognises what is connected to what. And there is a program shortcoming that requires a workaround. [... original post sequence altered for clarity ...] Having RTFM'ed a little I read something to the effect that drawn bus wires essentially are just eye candy. This seems consistent with the fact that I seem to be able to draw all the bus-wires and labels I want and nothing gets connected right. Who thought this was a good idea??? Yes, bus-wires are *mostly* eye candy, added to make bus usage clearer to the reader. Bus ports, however, are essential in hierarchical design, and net labels and wires are the foundation of all connectivity. I indicated an exception to the bus = eye-candy rule, and it is crucial. To connect a bus to a port or sheet entry, you can place the hot spot for a bus label on the port/sheet entry hot spot, *or* you can draw a bus-wire and place the net label on this bus-wire. See below. The Protel manual is incorrect when it says that bus-wires have no electrical effect. I've got a big design that's begging to be implemented using hierarchical blocks, but as far as I can tell the netlister is dealing with buses in a way that really limits the usefulness of hierarchy. How can I successfully do the following: 1. Create subsheet 'A' with bus output X[7..0] 2. Create subsheet 'B' with bus output Y[7..0] 3. Create subsheet 'C' with bus input Z[15..0] On the subsheets A and B, place an *input* port, in the first case you would name it X[0..7], in the second, Y[0..7]. You can also use descending numbers as you requested, I didn't do that here For every net that you want to connect on the subsheets, you must place an individual net label in a position where it will be electrically active. Every net label has a hot spot (lower left corner with a horizontal label); if this hot spot is on a wire or on the hot spot of a pin, the net connection will be effected to the wire or pin. You must *also* place a net label for the bus itself, in such a way that Protel knows that it is connected to the port. This can be done by placing the net label hot spot on the port hot spot, but it is usually clearer and simpler to draw a bus-wire connecting to the port and place the net label on that bus-wire. Protel will follow the bus-wire back to the port and connect the on-sheet bus to the off-sheet bus. On the subsheet C, place an *output port* named Z[0..15]. Why are input and output reversed? Because the port symbol represents to the eye and to ERC (Schematic Error Check) what is off-sheet. So, for example, an input pin on the sheet must be connected, presumably, to an output pin somewhere else in the hierarchy. On the level above, the inputs on the lower sheet will be seen as the inputs that they actually are If you don't follow this convention, you may have some difficulty getting a clean ERC, and clean ERCs are a mark of good design. 4. Instantiate sheets A, B, and C into toplevel sheet 'D' as follows: A's port X[7..0] connected to C's port Z[15..8] B's port Y[7..0] connected to C's port Z[7..0] On the toplevel sheet, place a sheet symbol for sheets A, B, and C. Use Create Symbol from Sheet on the Design Menu and agree to reverse Input/Output directions. You should now have the appropriate sheet symbols and sheet entries. The following *should* work, but it doesn't seem to, perhaps for a reason I will give below. Draw a bus wire connecting to the C sheet entry and label it A[0..15]. Draw a bus wire connecting to the A sheet entry and label it A[8..15]. Draw a bus wire connecting to the B sheet entry and label it A[0..7]. (It could have been any name, I used A just to emphasize that the name of a net on the top level is not necessarily the same as the name of the net on a lower level. This is *essential* for design re-use.) Apparently, however, Protel connects sheet entry ports to buses only by explicit match of the bus number. If I am correct about this, it is a serious deficiency, I vaguely remember it having been discussed before. Where an eight-member bus connects to another eight-member bus, for example, the connections should be made by sequential match rather than by explicit numerical identity. Has this been fixed in DXP? To make the connectivity work as desired, without monkeying with the subsheets, I do not find simple. I could go on to define a workaround, but first, does anyone else know how to make, say X[0..3] connect to Z[4..7]? With design re-use especially, one does not want to have to modify the subsheets! In the desired case, I'd probably modify the sixteen-bit subsheet to have two explicit 8-bit busses. If Protel supported net renaming, the matter could be accomplished on the top level. Okay, I'll describe the
Re: [PEDA] Buses
[EMAIL PROTECTED] wrote: Apparently, however, Protel connects sheet entry ports to buses only by explicit match of the bus number. If I am correct about this, it is a serious deficiency... To make the connectivity work as desired, without monkeying with the subsheets, I do not find simple. I could go on to define a workaround, but first, does anyone else know how to make, say X[0..3] connect to Z[4..7]? ... Yes, this is EXACTLY the problem I'm having. Protel99's weird ideas about how to connect buses (as I understand them) present a significant barrier to design re-use--if I want my sub-module's X[7..0] output to hook to Y[15..8] in the top-level, I have to go back and change the sub-module to either renumber the bus [15..8], or get rid of the buses entirely and design in terms of single wires (yech...stone age...maybe I'll put the netlist on punch cards while I'm at it) If Protel supported net renaming, the matter could be accomplished on the top level. Okay, I'll describe the workaround because Protel *does* support net renaming, it is merely that it squawks about it. ... I'll try this approach next time...I've already gone back and hacked up the design and converted all 're-named' buses to single wire ports. :( I'm sure glad someone at Protel worked on that whizzy 3D board viewer instead of making buses/hierarchy actually work for nontrivial designs--NOT! On a related Protel-sabotaging-design-reuse note, is there a way to create a sub-module and connect one of its inputs to power or ground, without getting ERC errors that claim I've shorted two nets (for example GND vs. the net name inside the subsheet?) -- Peter W. Richards / [EMAIL PROTECTED] Design Manager, EE ph +1 (408) 737 8100 x113 fx +1 (408) 737 8153 350 Potrero Av Sunnyvale, CA 94085 This email message (and any attached document) contains information from Reflectivity, Inc. which may be considered confidential by Reflectivity, or which may be privileged or otherwise exempt from disclosure under law, and is for the sole use of the individual or entity to whom it is addressed. Any other dissemination, distribution or copying of this message is strictly prohibited. If you receive this message in error, please notify me and destroy the attached message (and all attached documents) immediately. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Netlist translator
Anyone who has an RSI Omninet netlist translator for sale ? Please respond offline to [EMAIL PROTECTED] Peter * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Buses
I guess what I really want is for Protel's bus-naming stuff to work like ViewDraw. I've used it and it worked just fine (in this respect at least) for a much more complicated design. And above all, the way that it works, good or bad, is CLEARLY WRITTEN DOWN IN THE ING MANUAL unlike Protel99... In Viewdraw, the 'bus label' connecting to the submodule's port determines what gets hooked to what. If draw a bus with label FOO[7,5,3,1] connected to a submodule port BAR[0:3] you get exactly what you drew--FOO[7]-BAR[0], FOO[5]-BAR[1], etc. Flexible, and WYSIWYG. This is the only design I've ever seen that makes sense--other CAD vendors [hint hint] should wise up and rip it off!! -Original Message- From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]] Sent: Wednesday, February 12, 2003 2:50 PM To: Peter W. Richards Subject: RE: [PEDA] Buses At 05:24 PM 2/10/2003, you wrote: I'm sure glad someone at Protel worked on that whizzy 3D board viewer instead of making buses/hierarchy actually work for nontrivial designs--NOT! Actually I've seen a number of CAD systems fall down when one looks too closely at how hierarchical designs are handled. OrCAD Capture can be a nightmare, it is too unpleasant to remember, it would ruin my day. with the workaround I gave, Protel actually works as it should, it is just a nuisance that one has to essentially rename the nets, but the renaming can be done at the top level, which is tolerable. In other words, the re-used sheets can be used as-is. On a related Protel-sabotaging-design-reuse note, is there a way to create a sub-module and connect one of its inputs to power or ground, without getting ERC errors that claim I've shorted two nets (for example GND vs. the net name I'd have to think about this, and no time for that at the moment. But my comment is that once one knows the cause of an error or warning, and knows for sure that netlisting will be correct, it is both safe and advisable to place a No-ERC directive on the error or warning where it appears, thus suppressing it. Nets are generally named at the highest level at which they occur, by the way. Basically, once you know how to handle it, Protel works fine with design re-use. But for sure they could make it more transparent. And it would be helpful if buses could be connected sequentially instead of the present explicit requirement; note, however, that explicit at least has the advantage of being utterly explicit. Sometimes one is only picking off part of a bus: which segment would be picked off if sequence is used instead of explicit identity? There is a way to deal with this, I am sure, but my point is that it is not quite as trivial a problem as it might seem. The present structure does allow what needs to be done -- through net renaming -- forcing one to be explicit. In the instant case as I recall it, we wanted to connect, say, Y0-Y7 on a subsheet to Z8-Z15 out of a bus Z0-Z15 on the top level. If we simply connect the bus Z0-Z15 to the sheet entry Y0-Y7, how is Protel to know that we want anything other than Z0 to Y0, Z1 to Y1, etc.? An answer would be if Protel treated a local bus net label as controlling assignment by sequence. If one has a bus A0-A15 and then places, on the bus wire immediately next to the sheet entry, a net label A[8..A15], Protel should know that we want to assign 8 to 0, 9 to 1, etc. It appears that if a bus A[0..15] exists on a sheet, instances of subsets of that on the sheet are treated as equivalent. That is the problem, and this is why the fix is to use a completely different bus name and rename to make the equivalents explicit. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
