Re: [PEDA] An example why IPC footprints are often sub-optimal

2004-03-16 Thread gacrowell
; To: [EMAIL PROTECTED] > Subject: [PEDA] An example why IPC footprints are often sub-optimal > > > One to stir up the hornets nest a little...and a little off > topic maybe > > http://www.considered.com.au/ProtelFiles/images/Phycomp_vs_IPC.gif > > shows the Phycomp

Re: [PEDA] An example why IPC footprints are often sub-optimal

2004-03-16 Thread Robert M. Wolfe
Saputelli" <[EMAIL PROTECTED]> To: "Protel EDA Forum" <[EMAIL PROTECTED]> Sent: Monday, March 15, 2004 11:49 PM Subject: Re: [PEDA] An example why IPC footprints are often sub-optimal > this is a great picture Ian! > i totally agree with your statements here > >

Re: [PEDA] An example why IPC footprints are often sub-optimal

2004-03-16 Thread John A. Ross [Design]
> -Original Message- > From: Ian Wilson [mailto:[EMAIL PROTECTED] > Sent: Tuesday, March 16, 2004 4:26 AM > To: [EMAIL PROTECTED] > Subject: [PEDA] An example why IPC footprints are often sub-optimal > > One to stir up the hornets nest a little...and a little off &

Re: [PEDA] An example why IPC footprints are often sub-optimal

2004-03-15 Thread Kathy Quinlan
> -Original Message- > From: Ian Wilson [mailto:[EMAIL PROTECTED] > Sent: Tuesday, 16 March 2004 12:26 PM > To: [EMAIL PROTECTED] > Subject: [PEDA] An example why IPC footprints are often sub-optimal > > > One to stir up the hornets nest a little...and a l

Re: [PEDA] An example why IPC footprints are often sub-optimal

2004-03-15 Thread Ian Wilson
On 03:53 PM 16/03/2004, Brian Guralnick said: Thank god, that, since my first PCB with protel's PCB & Schematic back in 96/97, I never since used a single Protel footprint. Ever. To be fair this isn't really a Protel issue. This is more an IPC issue. The Protel libraries are based on the only t

Re: [PEDA] An example why IPC footprints are often sub-optimal

2004-03-15 Thread Ian Wilson
On 03:49 PM 16/03/2004, Dennis Saputelli said: <..snip..> as to maximum packing density: isn't this a function of the placement jaws? and isn't that a moving target? I guess newer machines are more accurate than older ones - you do have to work with what your assembler can cope with though (or mov

Re: [PEDA] An example why IPC footprints are often sub-optimal

2004-03-15 Thread Dennis Saputelli
this is a great picture Ian! i totally agree with your statements here we have found the smaller footprints to be both more reliable and easier to assemble a large pad deposits more paste than a smaller pad (-duh!) this, in excess, is one of the main causes of tombstoning and the huge silkscreen

[PEDA] An example why IPC footprints are often sub-optimal

2004-03-15 Thread Ian Wilson
One to stir up the hornets nest a little...and a little off topic maybe http://www.considered.com.au/ProtelFiles/images/Phycomp_vs_IPC.gif shows the Phycomp (the old Philips, now part of Yageo) reflow 0402 footprint versus the 0402 footprint from the Altium P2004 Chip Resistor library (in the .