[PEDA] DRC issue
Protel EDA forum members, In a P99SE design currently being wrapped up, we have a DRC error that is something we want to do that generates an error we would like to not get flagged. It would be good to set a very specific design rule to remove this DRC error, but I want to keep from having this new rule disquise any other real errors we need to correct. Our biggest concern in overlooking this desired error if it is flagged is we may also miss real DRC errors buried somewhere in the list. Here's the scenario: In BGAs we have in this design, several pads are not used and therefore don't have any assigned netnames. We want access to them due to this being an initial prototype design and so we have vias associated with the pads to provide access to them even though they are currently unused. In the debug stage, we may need to make use of them and this provides that access if necessary. Of course, everything associated with the unused pads is flagged as a DRC error. My desire would be to set a design rule where anything associated with these unused pads is not flagged, but everything else is to prevent missing any real DRC errors in this design. I tend to think that with Protel's selection capabilities, there is some way to set this up. Being there are more experienced minds out here than mine with Protel software, I wanted to pose this question and see if someone has a way figured to do this selection and rule setup. I look forward to any and all suggestions. Thanks in advance for your inputs and comments. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] DRC issue
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Re: [PEDA] DRC issue
I would add those pins to the netlist. IOW, add some wires to those pins on the schematic and bring them out to either some man made test points (i.e. a part with one pad); or a header somewhere. Name 'em spare1, spare2, spare3, etc. Problem solved. Jeff Stout - Original Message - From: Ken Pelic [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Cc: KerryArtesyn [EMAIL PROTECTED] Sent: Wednesday, August 22, 2001 12:20 PM Subject: [PEDA] DRC issue Protel EDA forum members, In a P99SE design currently being wrapped up, we have a DRC error that is something we want to do that generates an error we would like to not get flagged. It would be good to set a very specific design rule to remove this DRC error, but I want to keep from having this new rule disquise any other real errors we need to correct. Our biggest concern in overlooking this desired error if it is flagged is we may also miss real DRC errors buried somewhere in the list. Here's the scenario: In BGAs we have in this design, several pads are not used and therefore don't have any assigned netnames. We want access to them due to this being an initial prototype design and so we have vias associated with the pads to provide access to them even though they are currently unused. In the debug stage, we may need to make use of them and this provides that access if necessary. Of course, everything associated with the unused pads is flagged as a DRC error. My desire would be to set a design rule where anything associated with these unused pads is not flagged, but everything else is to prevent missing any real DRC errors in this design. I tend to think that with Protel's selection capabilities, there is some way to set this up. Being there are more experienced minds out here than mine with Protel software, I wanted to pose this question and see if someone has a way figured to do this selection and rule setup. I look forward to any and all suggestions. Thanks in advance for your inputs and comments. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] DRC issue
everything associated with the unused pads is flagged as a DRC error. My desire would be to set a design rule where anything associated with these unused pads is not flagged, but everything else is to prevent missing any real DRC errors in this design. Ken Under tools,design rule checks, only check off Clearance and unrouted for online and reports. Do not check shorted- circuit constraint.Your BGAs and design will pass 100 % DRCs if the design is routed correctly. No-Net pads and fan outs will not be flagged. The Clearance and short-circuit check overlap a design rule check so your board will pass with clearance and unrouted checked only. I design allot of boards and have no problems with this method. In all the designs I have ever completed with Protel, I have only had three errors that escaped the DRC. Two involved planes and one involved the use of a conflicting design rule for overlapping holes enabled at the same time as my clearance rule. It works Mike Reagan EDSI Frederick Md * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] DRC issue
Try putting a no-erc directive marker on each unconnected pin. The no-erc marker looks like a red X. Best regards, Ivan Baggett Bagotronix Inc. website: www.bagotronix.com - Original Message - From: Ken Pelic [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Cc: KerryArtesyn [EMAIL PROTECTED] Sent: Wednesday, August 22, 2001 1:20 PM Subject: [PEDA] DRC issue Protel EDA forum members, In a P99SE design currently being wrapped up, we have a DRC error that is something we want to do that generates an error we would like to not get flagged. It would be good to set a very specific design rule to remove this DRC error, but I want to keep from having this new rule disquise any other real errors we need to correct. Our biggest concern in overlooking this desired error if it is flagged is we may also miss real DRC errors buried somewhere in the list. Here's the scenario: In BGAs we have in this design, several pads are not used and therefore don't have any assigned netnames. We want access to them due to this being an initial prototype design and so we have vias associated with the pads to provide access to them even though they are currently unused. In the debug stage, we may need to make use of them and this provides that access if necessary. Of course, everything associated with the unused pads is flagged as a DRC error. My desire would be to set a design rule where anything associated with these unused pads is not flagged, but everything else is to prevent missing any real DRC errors in this design. I tend to think that with Protel's selection capabilities, there is some way to set this up. Being there are more experienced minds out here than mine with Protel software, I wanted to pose this question and see if someone has a way figured to do this selection and rule setup. I look forward to any and all suggestions. Thanks in advance for your inputs and comments. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] DRC issue
Ken Pelic wrote: Here's the scenario: In BGAs we have in this design, several pads are not used and therefore don't have any assigned netnames. We want access to them due to this being an initial prototype design and so we have vias associated with the pads to provide access to them even though they are currently unused. In the debug stage, we may need to make use of them and this provides that access if necessary. Of course, everything associated with the unused pads is flagged as a DRC error. My desire would be to set a design rule where anything associated with these unused pads is not flagged, but everything else is to prevent missing any real DRC errors in this design. What I would do is put into the schematic net names such as spare01, spare02 etc, and treat these as if they were any other signal. The via could be replaced with a single pad component of equivalent pad and hole size, or call it a test point. That will get rid of the error message, and the schematic will show the pad and BGA pin assignment clearly, too. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] DRC issue
This is yet another case where the availability of No-Net in the design rule net drop lists would help. At the moment it is not possible to set a design rule saying that it is OK for a no-net primitive to connect to another no-net primitive. Hopefully this will be fixed soon as it does affect things like connecting mounting holes to fills etc. I find it when connecting surface mount connectors with strain relief tabs and the like - you want to connect to a significant bit of copper to ensure reasonable pull strength. Ken, in your case I think I would go with others advice about adding the spare nets to the Sch. You could even terminate these spare tracks in a probe-point component (on the Sch and PCB) which can easily be a single thru-hole pad. Then you get it all nicely documented on the Sch and PCB overlay as well and you don't have to remember anything about telling Protel to deal correctly with single pin nets. Ian Wilson On 12:20 PM 22/08/2001 -0500, Ken Pelic said: Protel EDA forum members, In a P99SE design currently being wrapped up, we have a DRC error that is something we want to do that generates an error we would like to not get flagged. It would be good to set a very specific design rule to remove this DRC error, but I want to keep from having this new rule disquise any other real errors we need to correct. Our biggest concern in overlooking this desired error if it is flagged is we may also miss real DRC errors buried somewhere in the list. Here's the scenario: In BGAs we have in this design, several pads are not used and therefore don't have any assigned netnames. We want access to them due to this being an initial prototype design and so we have vias associated with the pads to provide access to them even though they are currently unused. In the debug stage, we may need to make use of them and this provides that access if necessary. Of course, everything associated with the unused pads is flagged as a DRC error. My desire would be to set a design rule where anything associated with these unused pads is not flagged, but everything else is to prevent missing any real DRC errors in this design. I tend to think that with Protel's selection capabilities, there is some way to set this up. Being there are more experienced minds out here than mine with Protel software, I wanted to pose this question and see if someone has a way figured to do this selection and rule setup. I look forward to any and all suggestions. Thanks in advance for your inputs and comments. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
