Re: [PEDA] Making of 956 pin SCH component (boring)

2002-09-20 Thread vincent mail




Re: [PEDA] Making of 956 pin SCH component (boring)

2002-09-20 Thread Steve Wiseman

20/09/2002 06:45:18, "Rick Wilson (Protta)" <[EMAIL PROTECTED]> wrote:

>Not sure what good it will do now, since the Protel 99SE or DXP programs
>do not have a Library ASCII in?

99SE certainly has an ASCII library - I used to have a vhdl2lib converter for 
FPGAs, which generated text files. 

Steve


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Re: [PEDA] Making of 956 pin SCH component (boring)

2002-09-19 Thread Tony Karavidas

IF there is a way to create footprints as an ASCII pcb file, the current
tool can probably read that, and THEN 'create library from PCB'



> -Original Message-
> From: Rick Wilson (Protta) [mailto:[EMAIL PROTECTED]] 
> Sent: Thursday, September 19, 2002 10:45 PM
> To: 'Protel EDA Forum'
> Subject: Re: [PEDA] Making of 956 pin SCH component (boring)
> 
> 
> Version 2.2 Schematic, the product that was sold with 2.8 PCB 
> was able to ASCII in/out the libraries.
> 
> Not sure what good it will do now, since the Protel 99SE or 
> DXP programs do not have a Library ASCII in?
> 
> Rick Wilson
> 
> 
> 
> -Original Message-
> From: Scott Ellis [mailto:[EMAIL PROTECTED]] 
> Sent: Thursday, September 19, 2002 7:00 PM
> To: Protel EDA Forum
> Subject: Re: [PEDA] Making of 956 pin SCH component (boring)
> 
> 
> I think that the original format for protel sch parts back in 
> version 3 had a text format. I am not sure if an older 
> version of protel could do the conversion of a text to ver3 
> binary library and then just convert the library format to 
> the current version. It would not take too long to check if 
> it could be done.
> 
> (I think this all derived from the fact that the Orcad 
> libraries were originally a text format and protel followed suit. )
> 
> (Of course I could be wrong, it is a while since I have 
> looked at any of the version 3 and earlier file formats.)
> 
> Scott Ellis
> Manager
> Novatex Research - Excellence in Electronic Research & 
> Development [EMAIL PROTECTED] 41 Yule Road, 
> Merewether, Newcastle, NSW 2291, Australia
> Ph 0412 988408   Fax 02 49636058
> - Original Message -----
> From: "John Haddy" <[EMAIL PROTECTED]>
> To: "Protel EDA Forum" <[EMAIL PROTECTED]>
> Sent: Friday, September 20, 2002 10:36 AM
> Subject: Re: [PEDA] Making of 956 pin SCH component (boring)
> 
> 
> > What a great idea, Vincent! Now why doesn't ALTIUM provide 
> a text file
> input
> > format for generating library components!?
> >
> > It would make my life ever so much easier if I could simply
> > auto-create all the pins (with their correct parameters) of a 
> > schematic symbol - the subsequent shuffling to suit my preferred 
> > positioning is a walk in the park if you don't have to do all that 
> > typing first!
> >
> > Being an IC design group, we have a single pad definition 
> master file
> > that is used for verilog generation, xml documentation, 
> etc. The only 
> > missing part is a tool for import into Protel schematic library. So 
> > the biggest risk area in the process is that the PCB won't 
> match the 
> > IC, if a pin swap/change is missed due to the manual nature of 
> > schematic
> component
> > generation.
> >
> > Any import format would do - I can easily write a parser to extract
> > the relevant fields from our master pad definition.
> >
> > I'm unfamiliar with what it takes to write a generator such 
> as Vincent
> 
> > describes, but if anybody would care to write a generic one using a
> > defined text file syntax as input, I'd be mighty grateful!
> >
> > John Haddy
> >
> > > -Original Message-
> > > From: vincent mail [mailto:[EMAIL PROTECTED]]
> > > Sent: Thursday, 19 September 2002 11:24 PM
> > > To: Protel EDA Forum
> > > Subject: Re: [PEDA] Making of 956 pin SCH component (boring)
> > >
> > >
> > > send me one of those altera txt files . i'll write you a a
> > > generator.
> > >
> > >
> > > Juha Pajunen wrote:
> > >
> > > >Hi,
> > > >
> > > >I am making Altera 956 pin FPGA SCH component, assign
> > > >that many pin is annoying... why not there is component 
> wizard like
> 
> > > >PCB library editor has, at least I do not know it...?
> > > >It would be nice to have a program that could read
> > > >pin-out information file
> > > >(Altera offers pin-out file, that is in TEXT format)
> > > >and "make" pins to SCH component!
> > > >
> > > >How do you do your huge pin SCH components?
> > > >
> > > >Sincerely,
> > > >Juha Pajunen, Hw Engineer
> > > >Bitboys Oy
> > > >E-mail: [EMAIL PROTECTED]
> > > >
> > > >NOTE:  This message, and any att

Re: [PEDA] Making of 956 pin SCH component (boring)

2002-09-19 Thread Rick Wilson (Protta)

Version 2.2 Schematic, the product that was sold with 2.8 PCB was able
to ASCII in/out the libraries.

Not sure what good it will do now, since the Protel 99SE or DXP programs
do not have a Library ASCII in?

Rick Wilson



-Original Message-
From: Scott Ellis [mailto:[EMAIL PROTECTED]] 
Sent: Thursday, September 19, 2002 7:00 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Making of 956 pin SCH component (boring)


I think that the original format for protel sch parts back in version 3
had a text format. I am not sure if an older version of protel could do
the conversion of a text to ver3 binary library and then just convert
the library format to the current version. It would not take too long to
check if it could be done.

(I think this all derived from the fact that the Orcad libraries were
originally a text format and protel followed suit. )

(Of course I could be wrong, it is a while since I have looked at any of
the version 3 and earlier file formats.)

Scott Ellis
Manager
Novatex Research - Excellence in Electronic Research & Development
[EMAIL PROTECTED] 41 Yule Road, Merewether, Newcastle, NSW
2291, Australia
Ph 0412 988408   Fax 02 49636058
- Original Message -
From: "John Haddy" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Friday, September 20, 2002 10:36 AM
Subject: Re: [PEDA] Making of 956 pin SCH component (boring)


> What a great idea, Vincent! Now why doesn't ALTIUM provide a text file
input
> format for generating library components!?
>
> It would make my life ever so much easier if I could simply 
> auto-create all the pins (with their correct parameters) of a 
> schematic symbol - the subsequent shuffling to suit my preferred 
> positioning is a walk in the park if you don't have to do all that 
> typing first!
>
> Being an IC design group, we have a single pad definition master file 
> that is used for verilog generation, xml documentation, etc. The only 
> missing part is a tool for import into Protel schematic library. So 
> the biggest risk area in the process is that the PCB won't match the 
> IC, if a pin swap/change is missed due to the manual nature of 
> schematic
component
> generation.
>
> Any import format would do - I can easily write a parser to extract 
> the relevant fields from our master pad definition.
>
> I'm unfamiliar with what it takes to write a generator such as Vincent

> describes, but if anybody would care to write a generic one using a 
> defined text file syntax as input, I'd be mighty grateful!
>
> John Haddy
>
> > -Original Message-
> > From: vincent mail [mailto:[EMAIL PROTECTED]]
> > Sent: Thursday, 19 September 2002 11:24 PM
> > To: Protel EDA Forum
> > Subject: Re: [PEDA] Making of 956 pin SCH component (boring)
> >
> >
> > send me one of those altera txt files . i'll write you a a 
> > generator.
> >
> >
> > Juha Pajunen wrote:
> >
> > >Hi,
> > >
> > >I am making Altera 956 pin FPGA SCH component, assign
> > >that many pin is annoying... why not there is component wizard like

> > >PCB library editor has, at least I do not know it...?
> > >It would be nice to have a program that could read
> > >pin-out information file
> > >(Altera offers pin-out file, that is in TEXT format)
> > >and "make" pins to SCH component!
> > >
> > >How do you do your huge pin SCH components?
> > >
> > >Sincerely,
> > >Juha Pajunen, Hw Engineer
> > >Bitboys Oy
> > >E-mail: [EMAIL PROTECTED]
> > >
> > >NOTE:  This message, and any attached files, may contain privileged

> > >or confidential information. It is intended for use only by the 
> > >designated recipients. Any disclosure, copying or distribution of, 
> > >or reliance
upon,
> > >this message by anyone else is strictly prohibited.
> > >
> >
> > --
> > -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
> >  _
> > //  Vincent Himpe
> >// _  ___/   Lab Manager
> >   / \ \   / /  /ST Microelectronics
> >  /___\ \ / /  / 5510 Six Forks Road . Suite 200
> > /__//_/__/  Raleigh NC 27612
> >
> > Tel : (919) 850 6070
> > Fax : (919) 850 6689
> > e-mail : [EMAIL PROTECTED]
> >
> > -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
> >
> >
> >
> >
> >
> >
>


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Re: [PEDA] Making of 956 pin SCH component (boring)

2002-09-19 Thread Scott Ellis

I think that the original format for protel sch parts back in version 3 had
a text format. I am not sure if an older version of protel could do the
conversion of a text to ver3 binary library and then just convert the
library format to the current version.
It would not take too long to check if it could be done.

(I think this all derived from the fact that the Orcad libraries were
originally a text format and protel followed suit. )

(Of course I could be wrong, it is a while since I have looked at any of the
version 3 and earlier file formats.)

Scott Ellis
Manager
Novatex Research - Excellence in Electronic Research & Development
[EMAIL PROTECTED]
41 Yule Road, Merewether, Newcastle, NSW 2291, Australia
Ph 0412 988408   Fax 02 49636058
- Original Message -
From: "John Haddy" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Friday, September 20, 2002 10:36 AM
Subject: Re: [PEDA] Making of 956 pin SCH component (boring)


> What a great idea, Vincent! Now why doesn't ALTIUM provide a text file
input
> format for generating library components!?
>
> It would make my life ever so much easier if I could simply auto-create
> all the pins (with their correct parameters) of a schematic symbol - the
> subsequent shuffling to suit my preferred positioning is a walk in the
> park if you don't have to do all that typing first!
>
> Being an IC design group, we have a single pad definition master file
> that is used for verilog generation, xml documentation, etc. The only
> missing part is a tool for import into Protel schematic library. So the
> biggest risk area in the process is that the PCB won't match the IC, if
> a pin swap/change is missed due to the manual nature of schematic
component
> generation.
>
> Any import format would do - I can easily write a parser to extract the
> relevant fields from our master pad definition.
>
> I'm unfamiliar with what it takes to write a generator such as Vincent
> describes, but if anybody would care to write a generic one using a
> defined text file syntax as input, I'd be mighty grateful!
>
> John Haddy
>
> > -Original Message-
> > From: vincent mail [mailto:[EMAIL PROTECTED]]
> > Sent: Thursday, 19 September 2002 11:24 PM
> > To: Protel EDA Forum
> > Subject: Re: [PEDA] Making of 956 pin SCH component (boring)
> >
> >
> > send me one of those altera txt files . i'll write you a a generator.
> >
> >
> > Juha Pajunen wrote:
> >
> > >Hi,
> > >
> > >I am making Altera 956 pin FPGA SCH component, assign
> > >that many pin is annoying... why not there is component
> > >wizard like PCB library editor has, at least I do not
> > >know it...?
> > >It would be nice to have a program that could read
> > >pin-out information file
> > >(Altera offers pin-out file, that is in TEXT format)
> > >and "make" pins to SCH component!
> > >
> > >How do you do your huge pin SCH components?
> > >
> > >Sincerely,
> > >Juha Pajunen, Hw Engineer
> > >Bitboys Oy
> > >E-mail: [EMAIL PROTECTED]
> > >
> > >NOTE:  This message, and any attached files, may contain privileged or
> > >confidential information. It is intended for use only by the designated
> > >recipients. Any disclosure, copying or distribution of, or reliance
upon,
> > >this message by anyone else is strictly prohibited.
> > >
> >
> > --
> > -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
> >  _
> > //  Vincent Himpe
> >// _  ___/   Lab Manager
> >   / \ \   / /  /ST Microelectronics
> >  /___\ \ / /  / 5510 Six Forks Road . Suite 200
> > /__//_/__/  Raleigh NC 27612
> >
> > Tel : (919) 850 6070
> > Fax : (919) 850 6689
> > e-mail : [EMAIL PROTECTED]
> >
> > -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
> >
> >
> >
> >
> >
> >
>


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Re: [PEDA] Making of 956 pin SCH component (boring)

2002-09-19 Thread John Haddy

What a great idea, Vincent! Now why doesn't ALTIUM provide a text file input
format for generating library components!?

It would make my life ever so much easier if I could simply auto-create
all the pins (with their correct parameters) of a schematic symbol - the
subsequent shuffling to suit my preferred positioning is a walk in the
park if you don't have to do all that typing first!

Being an IC design group, we have a single pad definition master file
that is used for verilog generation, xml documentation, etc. The only
missing part is a tool for import into Protel schematic library. So the
biggest risk area in the process is that the PCB won't match the IC, if
a pin swap/change is missed due to the manual nature of schematic component
generation.

Any import format would do - I can easily write a parser to extract the
relevant fields from our master pad definition.

I'm unfamiliar with what it takes to write a generator such as Vincent
describes, but if anybody would care to write a generic one using a
defined text file syntax as input, I'd be mighty grateful!

John Haddy

> -Original Message-
> From: vincent mail [mailto:[EMAIL PROTECTED]]
> Sent: Thursday, 19 September 2002 11:24 PM
> To: Protel EDA Forum
> Subject: Re: [PEDA] Making of 956 pin SCH component (boring)
>
>
> send me one of those altera txt files . i'll write you a a generator.
>
>
> Juha Pajunen wrote:
>
> >Hi,
> >
> >I am making Altera 956 pin FPGA SCH component, assign
> >that many pin is annoying... why not there is component
> >wizard like PCB library editor has, at least I do not
> >know it...?
> >It would be nice to have a program that could read
> >pin-out information file
> >(Altera offers pin-out file, that is in TEXT format)
> >and "make" pins to SCH component!
> >
> >How do you do your huge pin SCH components?
> >
> >Sincerely,
> >Juha Pajunen, Hw Engineer
> >Bitboys Oy
> >E-mail: [EMAIL PROTECTED]
> >
> >NOTE:  This message, and any attached files, may contain privileged or
> >confidential information. It is intended for use only by the designated
> >recipients. Any disclosure, copying or distribution of, or reliance upon,
> >this message by anyone else is strictly prohibited.
> >
>
> --
> -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
>  _
> //  Vincent Himpe
>// _  ___/   Lab Manager
>   / \ \   / /  /ST Microelectronics
>  /___\ \ / /  / 5510 Six Forks Road . Suite 200
> /__//_/__/  Raleigh NC 27612
>
> Tel : (919) 850 6070
> Fax : (919) 850 6689
> e-mail : [EMAIL PROTECTED]
>
> -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
>
>
>
>
>
>

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Re: [PEDA] Making of 956 pin SCH component (boring)

2002-09-19 Thread JaMi Smith

Excellent! Excellent!

- Original Message - 
From: "vincent mail" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Thursday, September 19, 2002 6:24 AM
Subject: Re: [PEDA] Making of 956 pin SCH component (boring)


> send me one of those altera txt files . i'll write you a a generator.
> 
> 
> Juha Pajunen wrote:
> 

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Re: [PEDA] Making of 956 pin SCH component (boring)

2002-09-19 Thread JaMi Smith

Excellent idea!

You got my vote . . .

- Original Message - 
From: "Juha Pajunen" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Wednesday, September 18, 2002 10:21 PM
Subject: [PEDA] Making of 956 pin SCH component (boring)


> Hi,
> 
> I am making Altera 956 pin FPGA SCH component, assign
> that many pin is annoying... why not there is component
> wizard like PCB library editor has, at least I do not
> know it...?
> It would be nice to have a program that could read
> pin-out information file
> (Altera offers pin-out file, that is in TEXT format)
> and "make" pins to SCH component!
> 
> How do you do your huge pin SCH components?
> 
> Sincerely,
> Juha Pajunen, Hw Engineer
> Bitboys Oy
> E-mail: [EMAIL PROTECTED]
> 
> NOTE:  This message, and any attached files, may contain privileged or
> confidential information. It is intended for use only by the designated
> recipients. Any disclosure, copying or distribution of, or reliance upon,
> this message by anyone else is strictly prohibited.

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Re: [PEDA] Making of 956 pin SCH component (boring)

2002-09-19 Thread vincent mail

send me one of those altera txt files . i'll write you a a generator.


Juha Pajunen wrote:

>Hi,
>
>I am making Altera 956 pin FPGA SCH component, assign
>that many pin is annoying... why not there is component
>wizard like PCB library editor has, at least I do not
>know it...?
>It would be nice to have a program that could read
>pin-out information file
>(Altera offers pin-out file, that is in TEXT format)
>and "make" pins to SCH component!
>
>How do you do your huge pin SCH components?
>
>Sincerely,
>Juha Pajunen, Hw Engineer
>Bitboys Oy
>E-mail: [EMAIL PROTECTED]
>
>NOTE:  This message, and any attached files, may contain privileged or
>confidential information. It is intended for use only by the designated
>recipients. Any disclosure, copying or distribution of, or reliance upon,
>this message by anyone else is strictly prohibited.
>

-- 
-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
 _
//  Vincent Himpe
   // _  ___/   Lab Manager
  / \ \   / /  /ST Microelectronics
 /___\ \ / /  / 5510 Six Forks Road . Suite 200
/__//_/__/  Raleigh NC 27612

Tel : (919) 850 6070
Fax : (919) 850 6689
e-mail : [EMAIL PROTECTED]

-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-






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Re: [PEDA] Making of 956 pin SCH component (boring)

2002-09-19 Thread Rene Tschaggelar

The biggest FPGA I'done is a 144 pin. Yes, it takes some work.
It was a TQFP and I wanted the schematic to look like the 
footprint. I placed each pin by hand and named it according to
the ALTERA naming: (TDI, TMS, GNDIO, VCCINT, GCLK1 .. ) but only 
after having them placed with increasing numbers as names. I 
have the numbers visible and only the changed names, not the 
number names.

The motivation to have the schematic equal to the footprint :
When placing tracks to and from the FPGA I want a minimal amount 
of vias and crossings, so the process of assigning a wire on 
the schematic and assigning a pin in MaxPlus2 or Quartus is 
iterative. And having the footprint equal to the footprint
supports that.

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net


Juha Pajunen wrote:
> 
> Hi,
> 
> I am making Altera 956 pin FPGA SCH component, assign
> that many pin is annoying... why not there is component
> wizard like PCB library editor has, at least I do not
> know it...?
> It would be nice to have a program that could read
> pin-out information file
> (Altera offers pin-out file, that is in TEXT format)
> and "make" pins to SCH component!
> 
> How do you do your huge pin SCH components?

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[PEDA] Making of 956 pin SCH component (boring)

2002-09-19 Thread Juha Pajunen

Hi,

I am making Altera 956 pin FPGA SCH component, assign
that many pin is annoying... why not there is component
wizard like PCB library editor has, at least I do not
know it...?
It would be nice to have a program that could read
pin-out information file
(Altera offers pin-out file, that is in TEXT format)
and "make" pins to SCH component!

How do you do your huge pin SCH components?

Sincerely,
Juha Pajunen, Hw Engineer
Bitboys Oy
E-mail: [EMAIL PROTECTED]

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