Re: [PEDA] Creating custom design rules?
On 05:06 PM 10/04/2001 -0600, Gladieux, Jed said: Does anyone know how to create new design rules. For example, I would like to flag instances where component outlines on the silkscreen layers overlap. I got bit by this on a very busy board and wound up with 2 components physically interfering with each other although pads/tracks were all OK. I'm currently using Protel98 but am planning to migrate to 99SE as soon as I get a chance. Wasn't able to find anything in P98 Help. Maybe I'll try Protel's Knowledge Base, but in the meantime, it anyone knows how to do this I would appreciate any advice. TIA, Jed Gladieux Jed - in my other reply I forgot to mention that you can't create a design rule that is not there - if P98 doesn't support the rule you need there is no way of creating one. That said, the design rules that are in P99SE are quite extensive, less so in P98. Ian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Creating custom design rules?
There is a design rule called component clearance constraint under the Placement tab. It will generate an error if the top/bottom overlay primitives of a component come within a specified distance. This should do the trick. -Original Message- From: Gladieux, Jed [mailto:[EMAIL PROTECTED]] Sent: Wednesday, 11 April 2001 9:07 AM To: '[EMAIL PROTECTED]' Subject: [PEDA] Creating custom design rules? Does anyone know how to create new design rules. For example, I would like to flag instances where component outlines on the silkscreen layers overlap. I got bit by this on a very busy board and wound up with 2 components physically interfering with each other although pads/tracks were all OK. I'm currently using Protel98 but am planning to migrate to 99SE as soon as I get a chance. Wasn't able to find anything in P98 Help. Maybe I'll try Protel's Knowledge Base, but in the meantime, it anyone knows how to do this I would appreciate any advice. TIA, Jed Gladieux Ball Aerospace 1600 Commerce St., CO-5 Boulder, CO 80301 Phone: 303-939-5819 Fax: 303-939-5550 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Creating custom design rules?
However, the coponent clearance rule is next to useless once you start working with tightly packed boards. If you want to place componnets so that their silkscreen borders overlap (e.g. 0402s places side by side), you need to turn off the component clearance rule - so you end up with the very dangerous situation of requiring manual checking of each and every component placement. I've said this before (but I'll repeat it in the hope that someone at Protel listens :-): What is really needed is an extra layer defined as a physical component outline layer. A clearance rule based on this layer would ensure that components did not try to physically occupy the same space. This rule would need to be combined with clearance rules that would ensure minimum gap between a primitive entity (e.g. pad, or a soldermask opening) and entities on the silkscreen layer (so that one component's legend doesn't end up over a pad). It is getting very rare, with the boards that I work on, that the silkscreen overlay bears any resemblance to the actual component outline - so using this as the rule to prevent component interference is not useful. Just my $0.02c Cheers, John Haddy -Original Message- From: Ian Wilson [mailto:[EMAIL PROTECTED]] Sent: Wednesday, 11 April 2001 10:00 AM To: Protel EDA Forum Subject: Re: [PEDA] Creating custom design rules? On 05:06 PM 10/04/2001 -0600, Gladieux, Jed said: Does anyone know how to create new design rules. For example, I would like to flag instances where component outlines on the silkscreen layers overlap. I got bit by this on a very busy board and wound up with 2 components physically interfering with each other although pads/tracks were all OK. I'm currently using Protel98 but am planning to migrate to 99SE as soon as I get a chance. Wasn't able to find anything in P98 Help. Maybe I'll try Protel's Knowledge Base, but in the meantime, it anyone knows how to do this I would appreciate any advice. TIA, Jed Gladieux In P99SE you can set a rule for component clearance. If you set the Check Mode to Full and the clearance of 0mil/mm you will get an accurate check of interference even for convoluted component outlines - assuming your overlay details are correct. P98, from memory, does not have the full check mode and it doesn't have the same method of setting component clearance. Anyway P99SE should go someway to trapping your problem. Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Creating custom design rules?
On 05:22 PM 10/04/2001 -0700, Abd ul-Rahman Lomax said: At 05:06 PM 4/10/01 -0600, Gladieux, Jed wrote: Does anyone know how to create new design rules. For example, I would like to flag instances where component outlines on the silkscreen layers overlap. [using Protel 98] Component interference rules did not exist in Protel 98. They've been added to Protel 99SE, though they could still use improvement. They assume a bounding rectangle being the extent of the primitives on all layers (don't ask me what happens if the component is rotated -- I haven't checked). If you have component outlines at MMC, you will get over-conservative spacing. Simple bounding rectangle is not used with Check Mode = Full. You set this mode in the component clearance rule. This has been discussed before. The default check mode is not Full (can't recall what is though). It is worth experimenting with. No need for the polygon outline etc - just use the component overlay. I haven't checked how it behaves with a multi-sided component - one with different outline on the top and bottom layers. This could be an exercise for someone else to undertake and report on. In my experience Full Check Mode correctly treats arcs diagonals as well as orthos and ignores comments and designators. I think we would prefer a polygon outline on a defined layer, and the polygon outline track would have zero dimension; one we? - I think I would prefer you said 'I in your comments. This is your opinion, it is an assumption that others agree. (This is an example of the high-and-mighty talk from us regular respondents that I feel guilty of and have mentioned before.) In cases where the overlay does not represent the outline of the component, such as where you have a polarity mark outside a device region, a device extents layer override would be helpful, otherwise it is not necessary. I would not like to see old projects broken so it would presumably need to be a component option (Use choose_layer as Component Boundary check box where choose_layer is a drop list of layers present in that component. Should be globally settable of course. Ultimately, we will want height information in there. I agree - I would like to be able to define rooms within a component and associate a height with each room. To allow simple more complex models than simple blocks. I guess instead of heights we will really need a reference to an 3D model. A simple height would not solve your issue of tucking a res under the curve of an axial cap as the 3D check/viewer cap would, presumably, assume it is a block rather than a cylinder. Hence the requirement for a reference to a 3D model. Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Creating custom design rules?
On 10:41 AM 11/04/2001 +1000, John Haddy said: However, the coponent clearance rule is next to useless once you start working with tightly packed boards. If you want to place componnets so that their silkscreen borders overlap (e.g. 0402s places side by side), you need to turn off the component clearance rule - so you end up with the very dangerous situation of requiring manual checking of each and every component placement. What about allowing support for negative component clearances? So you can define an allowed overlap between, for example, 0402 components. I agree that in cases where a defined overlap is permissible that the extra layer would be very helpful but I suspect will not happen in the next SP. I am thinking about what could be implemented in SP7 easily here. Allowing negative clearances should not be hard. I've said this before (but I'll repeat it in the hope that someone at Protel listens :-): What is really needed is an extra layer defined as a physical component outline layer. A clearance rule based on this layer would ensure that components did not try to physically occupy the same space. This rule would need to be combined with clearance rules that would ensure minimum gap between a primitive entity (e.g. pad, or a soldermask opening) and entities on the silkscreen layer (so that one component's legend doesn't end up over a pad). Yep - there is a lot to think about in implementing this suggestion, new rules that I can think of: 1) Minimum solder mask width (a bit like checking for internal plane connectivity) 2) Overlay near pads (as you mentioned) 3) others bye for now, Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Creating custom design rules?
I have adjusted my silkscreen on these parts to accommodate the closer grouping. This allows me to place them closer but it violates the IPC spacing rules. Only a few houses have commented on this practice. - Original Message - From: John Haddy [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Tuesday, 10 April, 2001 7:41 PM Subject: Re: [PEDA] Creating custom design rules? However, the coponent clearance rule is next to useless once you start working with tightly packed boards. If you want to place componnets so that their silkscreen borders overlap (e.g. 0402s places side by side), you need to turn off the component clearance rule - so you end up with the very dangerous situation of requiring manual checking of each and every component placement. I've said this before (but I'll repeat it in the hope that someone at Protel listens :-): What is really needed is an extra layer defined as a physical component outline layer. A clearance rule based on this layer would ensure that components did not try to physically occupy the same space. This rule would need to be combined with clearance rules that would ensure minimum gap between a primitive entity (e.g. pad, or a soldermask opening) and entities on the silkscreen layer (so that one component's legend doesn't end up over a pad). It is getting very rare, with the boards that I work on, that the silkscreen overlay bears any resemblance to the actual component outline - so using this as the rule to prevent component interference is not useful. Just my $0.02c Cheers, John Haddy -Original Message- From: Ian Wilson [mailto:[EMAIL PROTECTED]] Sent: Wednesday, 11 April 2001 10:00 AM To: Protel EDA Forum Subject: Re: [PEDA] Creating custom design rules? On 05:06 PM 10/04/2001 -0600, Gladieux, Jed said: Does anyone know how to create new design rules. For example, I would like to flag instances where component outlines on the silkscreen layers overlap. I got bit by this on a very busy board and wound up with 2 components physically interfering with each other although pads/tracks were all OK. I'm currently using Protel98 but am planning to migrate to 99SE as soon as I get a chance. Wasn't able to find anything in P98 Help. Maybe I'll try Protel's Knowledge Base, but in the meantime, it anyone knows how to do this I would appreciate any advice. TIA, Jed Gladieux In P99SE you can set a rule for component clearance. If you set the Check Mode to Full and the clearance of 0mil/mm you will get an accurate check of interference even for convoluted component outlines - assuming your overlay details are correct. P98, from memory, does not have the full check mode and it doesn't have the same method of setting component clearance. Anyway P99SE should go someway to trapping your problem. Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Creating custom design rules?
At 05:06 PM 4/10/01 -0600, Gladieux, Jed wrote: Does anyone know how to create new design rules. For example, I would like to flag instances where component outlines on the silkscreen layers overlap. [using Protel 98] Component interference rules did not exist in Protel 98. They've been added to Protel 99SE, though they could still use improvement. They assume a bounding rectangle being the extent of the primitives on all layers (don't ask me what happens if the component is rotated -- I haven't checked). If you have component outlines at MMC, you will get over-conservative spacing. I think we would prefer a polygon outline on a defined layer, and the polygon outline track would have zero dimension; one should be able to butt them up against each other without creating an error, if clearance is set to zero. Any crossing of polygon outlines would create an error. There's a fairly simple algorithm for detecting these crossings I suppose it doesn't have to be a polygon, it could be discrete tracks. Ultimately, we will want height information in there. For example, one might tuck a resistor underneath the curve of a large axial electrolytic capacitor without creating any assembly problem, since the axial cap will be inserted last anyway. When the 3-D analyzer is ready for prime time, with accessible models, I'd think full component clearance checking will become possible. But just having polygon outlines would be a great start. [EMAIL PROTECTED] Abdulrahman Lomax P.O. Box 690 El Verano, CA 95433 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Creating custom design rules?
Hi, PowerSmart wrote: I have adjusted my silkscreen on these parts to accommodate the closer grouping. This allows me to place them closer but it violates the IPC spacing rules. Only a few houses have commented on this practice. The IPC is STRICKLY a start point by no means up to current standards, practices or capablities. Jim McGrath CAD Connections, Inc. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Creating custom design rules?
-Original Message- From: PowerSmart [mailto:[EMAIL PROTECTED]] Sent: Wednesday, 11 April 2001 11:56 AM To: Protel EDA Forum Subject: Re: [PEDA] Creating custom design rules? I have adjusted my silkscreen on these parts to accommodate the closer grouping. This allows me to place them closer but it violates the IPC spacing rules. Only a few houses have commented on this practice. With small components, I need the silkscreen as close as possible to the pad (dictated by the fabricator's manufacturing tolerance on silkscreen positioning), PLUS I want to overlap adjacent component overlay traces. I regularly need 0402s placed on a 1mm pitch, for example. If I could guarantee that every board would be fully machine assembled, I could get away with removing the silkscreen entirely. Unfortunately, I need hand placement for prototypes and a sea of pads without bounding boxes to guide a human is just asking for trouble. So, if I must have overlay present, I don't want it interfering with my placement any more than absolutely necessary. John Haddy Cisco Systems WNBU Level 2, 3 Innovation Rd; North Ryde NSW 2113; Australia PO Box 617; North Ryde NSW 1670; Australia Phone: +61 2 8874 5406; Fax: +61 2 8874 5401 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Creating custom design rules?
Thomas wrote: Sorry Jed, didn't see you were running Protel98. As others have stated there is no rule for this in 98, only 99se supports component clearance rules. I guess you could construct components with the overlay repeated on an unused mid layer and set rules for that, seems a bit kludgey though. Are you sure there wasn't a component clearance check in P98? I'm sure, way back with 2.8 or earlier, I made the resistor outlines .090 wide specifically to prevent component clearance DRC errors. -- Peter Bennett TRIUMF 4004 Wesbrook Mall, Vancouver, BC, Canada GPS and NMEA info and programs: http://vancouver-webpages.com/peter/index.html * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Creating custom design rules?
On 05:06 PM 10/04/2001 -0600, Gladieux, Jed said: Does anyone know how to create new design rules. For example, I would like to flag instances where component outlines on the silkscreen layers overlap. I got bit by this on a very busy board and wound up with 2 components physically interfering with each other although pads/tracks were all OK. I'm currently using Protel98 but am planning to migrate to 99SE as soon as I get a chance. Wasn't able to find anything in P98 Help. Maybe I'll try Protel's Knowledge Base, but in the meantime, it anyone knows how to do this I would appreciate any advice. TIA, Jed Gladieux In P99SE you can set a rule for component clearance. If you set the Check Mode to Full and the clearance of 0mil/mm you will get an accurate check of interference even for convoluted component outlines - assuming your overlay details are correct. P98, from memory, does not have the full check mode and it doesn't have the same method of setting component clearance. Anyway P99SE should go someway to trapping your problem. Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Creating custom design rules?
On Tue, 24 Apr 2001, Dennis Saputelli wrote: what is the distance from the silkscreen line to the pad? silkscreen tolerance is not real tight By the time it's 0402, it's dots rather than lines, and they're outside, rather than between, the pads. That's more an 0603 version I've drawn there. I generally give the silk screen about 10-12 thou of clearance, depending on who's etching the boards. The nice thing about drawing only between the pads, not round the edge, is that there's far less tolerance needed. Your mileage may vary, of course - but since starting to do this, boards are a lot easier to cope with, both at design and first protoype build. Steve * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Creating custom design rules?
what is the distance from the silkscreen line to the pad?
silkscreen tolerance is not real tight
Dennis Saputelli
Steve Wiseman wrote:
On Wed, 11 Apr 2001, John Haddy wrote:
I need hand placement for prototypes and a sea of pads without bounding
boxes to guide a human is just asking for trouble. So, if I must have
overlay present, I don't want it interfering with my placement any more
than absolutely necessary.
After years of making bounding boxes thinner and closer, I've now given
up, and run with 2 lines closing the box described by the pads at the end
of 0402 0603 components. It conveys the same amount of information in
far less space, and seems to be operator friendly (so far...)
Bad ASCII art follows - fixed-pitch font will be needed to make any sense
of it...
-- pad
| | - outline
| |
Steve.
--
___
www.integratedcontrolsinc.comIntegrated Controls, Inc.
tel: 415-647-04802851 21st Street
fax: 415-647-3003San Francisco, CA 94110
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Re: [PEDA] Creating custom design rules?
On Wed, 11 Apr 2001, John Haddy wrote:
I need hand placement for prototypes and a sea of pads without bounding
boxes to guide a human is just asking for trouble. So, if I must have
overlay present, I don't want it interfering with my placement any more
than absolutely necessary.
After years of making bounding boxes thinner and closer, I've now given
up, and run with 2 lines closing the box described by the pads at the end
of 0402 0603 components. It conveys the same amount of information in
far less space, and seems to be operator friendly (so far...)
Bad ASCII art follows - fixed-pitch font will be needed to make any sense
of it...
-- pad
| | - outline
| |
Steve.
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