Hello All,
1) Place filtering on all inputs and outputs (series R and a cap to GND)
2) Avoid traces running over GND and power plane breaks. You can play with
layer stackup to do this.
3) Place series R's and potentially capacitors (to gnd) on all clock
signals.
Paul
-Original Message
]
www: www.norsat.com
> -Original Message-
> From: Paul C. Brown [mailto:[EMAIL PROTECTED]]
> Sent: Monday, April 09, 2001 3:03 PM
> To: Protel EDA Forum
> Subject: Re: [PEDA] FCC and design for Manufacturability advice
>
>
> Hello All,
>
> 1) Place filtering
hen determine a course
of action from their initial report.
Tony
> -Original Message-
> From: Paul C. Brown [mailto:[EMAIL PROTECTED]]
> Sent: Monday, April 09, 2001 3:03 PM
> To: Protel EDA Forum
> Subject: Re: [PEDA] FCC and design for Manufacturability advice
>
&
