Re: [PEDA] Setting component clearance rules
Ian, I'm not sure if your suggestion of vertical clearance is endorsed or just some of that famous UK wit. Your example is one of the few times this would be helpful. Through hole on top of SMT. Other combinations would drive the test and inspection guys nuts (bonkers?). I too have the clearance blues (greens) but more often when adding dual footprint patterns to cover parts availablility issues. Similar to placing a dip for prototype and an overlayed SOIC footprint for production. I recently placed two 0805 footprints so they formed a common pad high or gnd selector for a zero ohm placement. I tried every combination of positive or negative clearance rules to get rid of the clearance violation only to give up and contruct a special three pad footprint with a three pin resistor symbol. A poor way to do it because the new symbol shows up as a single ref designator and single value. I had to make a separate symbol for pull up and one for pull down placement. -Original Message- From: Ian Wilson [mailto:[EMAIL PROTECTED]] Sent: Wednesday, February 06, 2002 2:44 PM To: Protel EDA Forum Subject: Re: [PEDA] Setting component clearance rules On 01:52 PM 6/02/2002 -0500, Abd ul-Rahman Lomax said: At 02:00 PM 2/6/2002 +1100, Ian Wilson wrote: Negative clearances on components do not work - would be nice if they did. Alternatively a rule that allowed component clearance violations to be ignored for specific components or regions would be helpful. Here is what we should have. There should be two placement outline layers. Track on these layers would represent the limits of reserved board space; a closed outline figure would be required. Crossing of this track (not mere contact) would generate a placement violation, as would enclosure of one component's space by that of another except if the following feature is added: A further refinement would be that additional closed figures would be allowed *within* the outline, representing free space under the part. (crossing of such tracks would be an error.) The placement outline layer would be an associated layer, i.e., it flips with the part. The placement outline would also be used by any autoplacement routines. The design rules should also allow exceptions, as Mr. Wilson suggested. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA But then why stop there - the design rules should allow us to check that the component fitting under the one with some off-pcb space is not too high. I may be able to fit an 0805 under a ROM socket possibly even an S0 in some parts but not a fat tant. Or what about fitting small components under the curve of a large axial cap? The height available varies with distance from the centre line of the component. I seem to remember that one of the PCB packages has a design rule system that can deal with addition and subtraction etc. Using this (and with some extra design rule functions like DistanceToComponentBorder, and/or Overlap etc that give us measures off the component(s) being DRC'ed) we could get more elaborate. Cost would be a significant slow down in DRC and great scope for complex design rules not doing what we actually wanted. Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Setting component clearance rules
At 02:00 PM 2/6/2002 +1100, Ian Wilson wrote: Negative clearances on components do not work - would be nice if they did. Alternatively a rule that allowed component clearance violations to be ignored for specific components or regions would be helpful. Here is what we should have. There should be two placement outline layers. Track on these layers would represent the limits of reserved board space; a closed outline figure would be required. Crossing of this track (not mere contact) would generate a placement violation, as would enclosure of one component's space by that of another except if the following feature is added: A further refinement would be that additional closed figures would be allowed *within* the outline, representing free space under the part. (crossing of such tracks would be an error.) The placement outline layer would be an associated layer, i.e., it flips with the part. The placement outline would also be used by any autoplacement routines. The design rules should also allow exceptions, as Mr. Wilson suggested. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Setting component clearance rules
On 01:52 PM 6/02/2002 -0500, Abd ul-Rahman Lomax said: At 02:00 PM 2/6/2002 +1100, Ian Wilson wrote: Negative clearances on components do not work - would be nice if they did. Alternatively a rule that allowed component clearance violations to be ignored for specific components or regions would be helpful. Here is what we should have. There should be two placement outline layers. Track on these layers would represent the limits of reserved board space; a closed outline figure would be required. Crossing of this track (not mere contact) would generate a placement violation, as would enclosure of one component's space by that of another except if the following feature is added: A further refinement would be that additional closed figures would be allowed *within* the outline, representing free space under the part. (crossing of such tracks would be an error.) The placement outline layer would be an associated layer, i.e., it flips with the part. The placement outline would also be used by any autoplacement routines. The design rules should also allow exceptions, as Mr. Wilson suggested. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA But then why stop there - the design rules should allow us to check that the component fitting under the one with some off-pcb space is not too high. I may be able to fit an 0805 under a ROM socket possibly even an S0 in some parts but not a fat tant. Or what about fitting small components under the curve of a large axial cap? The height available varies with distance from the centre line of the component. I seem to remember that one of the PCB packages has a design rule system that can deal with addition and subtraction etc. Using this (and with some extra design rule functions like DistanceToComponentBorder, and/or Overlap etc that give us measures off the component(s) being DRC'ed) we could get more elaborate. Cost would be a significant slow down in DRC and great scope for complex design rules not doing what we actually wanted. Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Setting component clearance rules
At 06:43 AM 2/7/2002 +1100, Ian Wilson wrote: But then why stop there - the design rules should allow us to check that the component fitting under the one with some off-pcb space is not too high. I may be able to fit an 0805 under a ROM socket possibly even an S0 in some parts but not a fat tant. Or what about fitting small components under the curve of a large axial cap? The height available varies with distance from the centre line of the component. Yes. I made no suggestion that Protel should stop at any particular place I do think that my suggestion about allowing internal pockets may be overkill for a first implementation. That, being relatively rare, should be covered by design rule exceptions. I seem to remember that one of the PCB packages has a design rule system that can deal with addition and subtraction etc. Using this (and with some extra design rule functions like DistanceToComponentBorder, and/or Overlap etc that give us measures off the component(s) being DRC'ed) we could get more elaborate. Cost would be a significant slow down in DRC and great scope for complex design rules not doing what we actually wanted. Collision detection should be pretty fast, and then, once there are no collisions, checking for enclosure should also be pretty fast. I don't think that the slowdown would be significant, there are plenty of other things much more complex which are DRC'd. Remember, most components would have a rectangular outline, so not too many primitives would be in the outline. Outline at MMC (maximum material condition, the largest that the part could be, or, in this case, additional allowance might be made for manufacturing requirements) is a very simple concept, I'm surprised that it was not implemented long ago. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Setting component clearance rules
the solution i have found to work best is to not use component clearance rules Dennis Saputelli Pat Lyons wrote: I am trying to set component clearance rules to allow small components to overlap the bounding box of larger components or oddly shaped components. As an example allowing surface mount filter caps to sit tightly against the pins of a TO-220. Setting negative clearance between the 2 classes of components does not seem to accomplish this. Jayhawk Design -- Pat Lyons, [EMAIL PROTECTED] on 02/05/2002 -- ___ www.integratedcontrolsinc.comIntegrated Controls, Inc. tel: 415-647-04802851 21st Street fax: 415-647-3003San Francisco, CA 94110 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Setting component clearance rules
At 07:53 PM 5/02/02 -0600, you wrote: I am trying to set component clearance rules to allow small components to overlap the bounding box of larger components or oddly shaped components. As an example allowing surface mount filter caps to sit tightly against the pins of a TO-220. Setting negative clearance between the 2 classes of components does not seem to accomplish this. Jayhawk Design -- Pat Lyons, [EMAIL PROTECTED] on 02/05/2002 No Can Do. Negative clearances on components do not work - would be nice if they did. Alternatively a rule that allowed component clearance violations to be ignored for specific components or regions would be helpful. Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
