The QTests perform five tests on the Xilinx ZynqMP CAN controller:
Tests the CAN controller in loopback, sleep and snoop mode.
Tests filtering of incoming CAN messages.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Francisco Iglesias
Signed-off-by: Vikram Garhwal
---
Changelog:
v10 -> v11:
Resending the series with correct cc.
Replace DB_PRINTS with trace-events.
Removed unnecessary local variables.
Added const with tx/rx buffers in qtest.
Added reviewed-by tags for qtest.
v9 -> v10:
Rebase the series with the new meson build system.
Connect CAN0 and CAN1 on the ZynqMP.
Reviewed-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Vikram Garhwal
---
include/hw/arm/xlnx-zynqmp.h | 8
hw/arm/xlnx-zcu102.c | 20
hw/arm/xlnx-zynqmp.c | 34
The Xilinx ZynqMP CAN controller is developed based on SocketCAN, QEMU CAN bus
implementation. Bus connection and socketCAN connection for each CAN module
can be set through command lines.
Example for using single CAN:
-object can-bus,id=canbus0 \
-machine xlnx-zcu102.canbus0=canbus0 \
Reviewed-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Vikram Garhwal
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 47dd38a..a8c672c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1559,6 +1559,14 @@ F:
Reviewed-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Vikram Garhwal
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 47dd38a..a8c672c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1559,6 +1559,14 @@ F:
Connect CAN0 and CAN1 on the ZynqMP.
Reviewed-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Vikram Garhwal
---
include/hw/arm/xlnx-zynqmp.h | 8
hw/arm/xlnx-zcu102.c | 20
hw/arm/xlnx-zynqmp.c | 34
The QTests perform five tests on the Xilinx ZynqMP CAN controller:
Tests the CAN controller in loopback, sleep and snoop mode.
Tests filtering of incoming CAN messages.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Francisco Iglesias
Signed-off-by: Vikram Garhwal
---
Changelog:
v10 -> v11:
Resending the series with correct cc.
Replace DB_PRINTS with trace-events.
Removed unnecessary local variables.
Added const with tx/rx buffers in qtest.
Added reviewed-by tags for qtest.
v9 -> v10:
Rebase the series with the new meson build system.
Connect CAN0 and CAN1 on the ZynqMP.
Reviewed-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Vikram Garhwal
---
include/hw/arm/xlnx-zynqmp.h | 8
hw/arm/xlnx-zcu102.c | 20
hw/arm/xlnx-zynqmp.c | 34
On 13.10.2020 22:21, Claudio Fontana wrote:
this fixes non-TCG builds broken recently by replay reverse debugging.
stub the needed functions in stub/, including errors for hmp and qmp.
This includes duplicating some code in replay/, and puts the logic
for non-replay related events in the
On Mon, Sep 28, 2020 at 6:12 PM Green Wan wrote:
>
> Add '-drive' support to OTP device. Allow users to assign a raw file
> as OTP image.
>
> test commands for 16k otp.img filled with zero:
>
> dd if=/dev/zero of=./otp.img bs=1k count=16
nits: please prefix the command with a leading "$ ", like
Hi Green,
On Mon, Sep 28, 2020 at 6:12 PM Green Wan wrote:
>
> - Add write operation to update fuse data bit when PWE bit is on.
> - Add array, fuse_wo, to store the 'written' status for all bits
>of OTP to block the write operation.
>
> Signed-off-by: Green Wan
> Reviewed-by: Alistair
TL;DR: this should allow the QEMU maintainer to push to the staging
branch, and have custom jobs running on the project's aarch64 and
s390x machines. Simple usage looks like:
git push remote staging
./scripts/ci/gitlab-pipeline-status --verbose --wait
Long version:
The idea about a
To have the jobs dispatched to custom runners, gitlab-runner must
be installed, active as a service and properly configured. The
variables file and playbook introduced here should help with those
steps.
The playbook introduced here covers a number of different Linux
distributions and FreeBSD,
To run basic jobs on custom runners, the environment needs to be
properly set up. The most common requirement is having the right
packages installed.
The playbook introduced here covers a number of different Linux
distributions and FreeBSD, and are intended to provide a reproducible
environment.
As described in the included documentation, the "custom runner" jobs
extend the GitLab CI jobs already in place.
Those jobs are intended to run on hardware and/or Operating Systems
not provided by GitLab's shared runners.
Signed-off-by: Cleber Rosa
---
.gitlab-ci.d/custom-runners.yml | 14
The QEMU project has two machines (aarch64 and s390) that can be used
for jobs that do build and run tests. This introduces those jobs,
which are a mapping of custom scripts used for the same purpose.
Signed-off-by: Cleber Rosa
---
.gitlab-ci.d/custom-runners.yml | 192
Public bug reported:
Hello together,
i build qemu-5.1.0 from source on centos 8 withe the following command:
../configure --prefix=/usr --target-list=x86_64-softmmu,x86_64-linux-
user
make -j4
make install
The build and the installation finished successfully. But when i try the
command
man
Hi Richard,
Please forgive my cumbersome mailing agent at work.
Please look inline for 'victor>'
From: Richard Henderson
Sent: Tuesday, October 13, 2020 7:22 PM
To: Philippe Mathieu-Daudé; qemu-devel@nongnu.org; Victor Kamensky (kamensky)
Cc: Aleksandar
On 10/13/20 4:11 PM, Richard Henderson wrote:
> On 10/13/20 6:25 AM, Philippe Mathieu-Daudé wrote:
>> Yocto developers have expressed interest in running MIPS32
>> CPU with custom number of TLB:
>> https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg03428.html
>>
>> Help them by making the
Hi Philippe,
Thank you very much for looking at this. I gave a spin to
your 3 patch series in original setup, and as expected with
'-cpu 34Kf,tlb-entries=64' option it works great.
If nobody objects, and your patches could be merged, we
would greatly appreciate it.
Thanks,
Victor
OK, I will modify it later.
On 2020/10/14 9:29, Zheng Chuan wrote:
> Also DEBUG_CACHE in migration/page_cache.c is need to rebase on trace_calls.
>
> On 2020/10/13 21:20, Bihong Yu wrote:
>> Thank you for your review. OK, I will try to rewrite the DPRINTF to use
>> trace_ instead.
>>
>> On
Also DEBUG_CACHE in migration/page_cache.c is need to rebase on trace_calls.
On 2020/10/13 21:20, Bihong Yu wrote:
> Thank you for your review. OK, I will try to rewrite the DPRINTF to use
> trace_ instead.
>
> On 2020/10/13 17:39, Dr. David Alan Gilbert wrote:
>> * Bihong Yu
Hi, Philippe,
On Tue, Oct 13, 2020 at 9:45 PM Philippe Mathieu-Daudé wrote:
>
> On 10/13/20 1:12 PM, Huacai Chen wrote:
> > Hi, Philippe,
> >
> > On Mon, Oct 12, 2020 at 4:12 PM Philippe Mathieu-Daudé
> > wrote:
> >>
> >> On 10/11/20 4:53 AM, Huacai Chen wrote:
> >>> Hi, Philippe,
> >>>
> >>>
On Mon, Oct 12, 2020 at 7:12 AM chenjiajun wrote:
>
>
>
> On 2020/10/2 10:05, Raphael Norwitz wrote:
> > On Mon, Sep 28, 2020 at 9:17 AM Jiajun Chen wrote:
> >>
> >> Used_memslots is equal to dev->mem->nregions now, it is true for
> >> vhost kernel, but not for vhost user, which uses the memory
> -Original Message-
> From: Max Reitz [mailto:mre...@redhat.com]
> Sent: Tuesday, October 13, 2020 10:47 PM
> To: Chenqun (kuhn) ; qemu-devel@nongnu.org;
> qemu-triv...@nongnu.org
> Cc: vsement...@virtuozzo.com; stefa...@redhat.com; f...@euphon.net;
> ebl...@redhat.com;
Hi all -
I've been playing around with qemu-system-arm on a MacOS 10.15 box. I'm trying
to bridge the guest but I haven't had any luck. It looks like the proper way
to do this is with a TAP device. AFAIK, this was done in the past by
installing a TUN/TAP kernel extension (kext), which Apple
On Tue, Oct 6, 2020 at 5:48 AM Igor Mammedov wrote:
>
> On Mon, 28 Sep 2020 21:17:31 +0800
> Jiajun Chen wrote:
>
> > Used_memslots is equal to dev->mem->nregions now, it is true for
> > vhost kernel, but not for vhost user, which uses the memory regions
> > that have file descriptor. In fact,
On Wed, Oct 14, 2020 at 06:42:02AM +0900, Dmitry Fomichev wrote:
> +{
> +NvmeEffectsLog log = {};
> +uint32_t *dst_acs = log.acs, *dst_iocs = log.iocs;
> +uint32_t trans_len;
> +int i;
> +
> +trace_pci_nvme_cmd_supp_and_effects_log_read();
> +
> +if (off >= sizeof(log)) {
>
On Tue, Oct 13, 2020 at 5:29 PM Alistair Francis wrote:
>
> On Mon, Oct 12, 2020 at 8:45 AM Peter Maydell
> wrote:
> >
> > The netduino2 and netduinoplus2 boards forgot to set the system_clock_scale
> > global, which meant that if guest code used the systick timer in "use
> > the processor
On Mon, Oct 12, 2020 at 8:45 AM Peter Maydell wrote:
>
> The netduino2 and netduinoplus2 boards forgot to set the system_clock_scale
> global, which meant that if guest code used the systick timer in "use
> the processor clock" mode it would hang because time never advances.
>
> Set the global to
Signed-off-by: Alistair Francis
---
include/hw/riscv/boot.h | 2 ++
hw/riscv/boot.c | 9 +
2 files changed, 11 insertions(+)
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index 0acbd8aa6e..2975ed1a31 100644
--- a/include/hw/riscv/boot.h
+++
Instead of loading the kernel at a hardcoded start address, let's load
the kernel at the next alligned address after the end of the firmware.
This should have no impact for current users of OpenSBI, but will
allow loading a noMMU kernel at the start of memory.
Signed-off-by: Alistair Francis
This series allows loading a noMMU kernel using the -kernel option.
Currently if using -kernel QEMU assumes you also have firmware and loads
the kernel at a hardcoded offset. This series changes that so we only
load the kernel at an offset if a firmware (-bios) was loaded.
This series also adds a
Allow the user to specify the main application CPU for the sifive_u
machine.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
---
include/hw/riscv/sifive_u.h | 1 +
hw/riscv/sifive_u.c | 18 +-
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git
Instead of returning the unused entry address from riscv_load_firmware()
instead return the end address. Also return the end address from
riscv_find_and_load_firmware().
This tells the caller if a firmware was loaded and how big it is. This
can be used to determine the load address of the next
On 10/3/20 10:49 AM, Philippe Mathieu-Daudé wrote:
> Fix an unlikely memory leak in load_elf_image().
>
> Fixes: bf858897b7 ("linux-user: Re-use load_elf_image for the main binary.")
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> linux-user/elfload.c | 8
> 1 file changed, 4
On Tue, Oct 13, 2020 at 01:19:30PM +0800, Yang Weijiang wrote:
> With more components in XSS being developed on Intel platform,
> it's necessary to clean up existing XSAVE related feature words to
> make the name clearer. It's to prepare for adding CET related support
> in following patches.
>
>
On 10/12/20 9:05 AM, Philippe Mathieu-Daudé wrote:
> Philippe Mathieu-Daudé (2):
> hw/mips/malta: Move gt64120 related code together
> hw/mips/malta: Use clearer qdev style
Reviewed-by: Richard Henderson
r~
On 10/12/20 6:20 AM, Philippe Mathieu-Daudé wrote:
> Philippe Mathieu-Daudé (5):
> hw: Replace magic value by PCI_NUM_PINS definition
> hw/pci-host/pam: Use ARRAY_SIZE() instead of magic value
> hw/pci-host/versatile: Add the MEMORY_WINDOW_COUNT definition
> hw/pci-host/versatile: Add the
On 10/13/20 5:26 AM, Peter Maydell wrote:
> When using -icount, it's useful for the CPU_LOG_EXEC logging
> to include information about when cpu_io_recompile() was
> called, because it alerts the reader of the log that the
> tracing of a previous TB execution may not actually
> correspond to an
On 10/13/20 6:25 AM, Philippe Mathieu-Daudé wrote:
> Yocto developers have expressed interest in running MIPS32
> CPU with custom number of TLB:
> https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg03428.html
>
> Help them by making the number of TLB entries a CPU property,
> keeping our
Currently, the functions that resolve CPU model versions
(x86_cpu_model_resolve_version(), x86_cpu_model_resolve_alias())
need a machine to be initialized first. Get rid of this
requirement by making those functions get an explicit
default_version argument.
No behavior changes are introduced by
The new parameter can be used by management software to query for
CPU model alias information for multiple machines without
restarting QEMU.
Signed-off-by: Eduardo Habkost
---
Changes v1 -> v2:
* Rewrite documentation, with suggestions from Markus
---
qapi/machine-target.json
New function is very similar to the old function, but it just
takes a X86CPUModel as argument, and its name makes its purpose
clearer.
Signed-off-by: Eduardo Habkost
---
target/i386/cpu.c | 33 +
1 file changed, 17 insertions(+), 16 deletions(-)
diff --git
We will change query-cpu-definitions to have a new `machine`
parameter. Move the code that reads default_cpu_version to
qmp_query_cpu_definitions() to make that easier to implement.
This patch shouldn't introduce any behavior change. Results of
query-cpu-definition will be exactly the same.
Changes v1 -> v2:
* Rewrite documentation, with suggestions from Markus
* Try to reduce churn and keep the existing default_cpu_version
static variable
* Replace x86_cpu_class_get_alias_of() with x86_cpu_model_resolve_alias()
Link to v1:
Instead of calling x86_cpu_class_get_alias_of(), just save the
actual CPU model name in X86CPUModel and use it in `-cpu help`.
Signed-off-by: Eduardo Habkost
---
target/i386/cpu.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/target/i386/cpu.c
The QMP code was never called by *-user, and we will add
machine-type-specific code there, so add #ifdefs to make it safe.
Signed-off-by: Eduardo Habkost
---
target/i386/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index
Move find_machine() from vl.c to core/machine.c and rename it to
machine_find_class(), so it can be reused by other code.
The function won't reuse the results of the previous
object_class_get_list() call like it did in vl.c, but this
shouldn't be a problem because the function is expected to be
Hi Sean,
Thanks much for your detailed replies. It's clear to me why GPAs are
different from HVAs in QEM/KVM. Thanks! I appreciate it if you could
help with the following two more questions.
On Tue, Oct 13, 2020 at 3:03 AM Sean Christopherson
wrote:
>
> This is where memslots come in. Think of
On 10/12/20 8:37 AM, Peter Maydell wrote:
> +nextlabel = gen_new_label();
> +tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[a->rn], 0, nextlabel);
> +gen_jmp(s, read_pc(s) + a->imm);
> +
> +gen_set_label(nextlabel);
> +tmp = load_reg(s, a->rn);
> +store_reg(s, 14, tmp);
> +
On Wed, 14 Oct 2020, BALATON Zoltan via wrote:
On Tue, 13 Oct 2020, Philippe Mathieu-Daudé wrote:
On 6/29/20 8:55 PM, BALATON Zoltan wrote:
This patch is more complex as it should be which I intend to fix once
agreement can be made on how to get back the necessary functionality
removed by
We can easily propagate temp values through the entire extended
basic block (in this case, the set of blocks connected by fallthru),
simply by not discarding the register state at the branch.
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 35 ++-
1 file
In several cases, it's easy to optimize across a non-taken branch
simply by *not* flushing the relevant tables. This is true both
for value propagation and register allocation.
This comes up in quite a number of cases with arm, most simply in
how conditional execution is implemented. But it
We can easily register allocate the entire extended basic block
(in this case, the set of blocks connected by fallthru), simply
by not discarding the register state at the branch.
This does not help blocks starting with a label, as they are
reached via a taken branch, and that would require
On Tue, 13 Oct 2020, Philippe Mathieu-Daudé wrote:
On 6/29/20 8:55 PM, BALATON Zoltan wrote:
OpenBIOS gets RAM size via fw_cfg but rhe original board firmware
Typo "the".
detects RAM using SPD data so generate and add SDP eeproms to cover as
EEPROMs?
much RAM as possible to describe
On 2020-10-12 12:49, Daniel P. Berrangé wrote:
On Mon, Oct 12, 2020 at 05:21:15PM +0100, Dr. David Alan Gilbert wrote:
* Tobin Feldman-Fitzthum (to...@linux.vnet.ibm.com) wrote:
> AMD SEV allows a guest owner to inject a secret blob
> into the memory of a virtual machine. The secret is
>
The emulation code has been changed to advertise NVM Command Set when
"zoned" device property is not set (default) and Zoned Namespace
Command Set otherwise.
Define values and structures that are needed to support Zoned
Namespace Command Set (NVMe TP 4053) in PCI NVMe controller emulator.
Define
nvme_write() now handles WRITE, WRITE ZEROES and ZONE_APPEND.
Signed-off-by: Dmitry Fomichev
---
hw/block/nvme.c | 95 +--
hw/block/trace-events | 1 -
2 files changed, 28 insertions(+), 68 deletions(-)
diff --git a/hw/block/nvme.c
From: Niklas Cassel
Many CNS commands have "allocated" command variants. These include
a namespace as long as it is allocated, that is a namespace is
included regardless if it is active (attached) or not.
While these commands are optional (they are mandatory for controllers
supporting the
ZNS specification defines two zone conditions for the zones that no
longer can function properly, possibly because of flash wear or other
internal fault. It is useful to be able to "inject" a small number of
such zones for testing purposes.
This commit defines two optional device properties,
Zone Descriptor Extension is a label that can be assigned to a zone.
It can be set to an Empty zone and it stays assigned until the zone
is reset.
This commit adds a new optional module property, "zone_descr_ext_size".
Its value must be a multiple of 64 bytes. If this value is non-zero,
it
In NVMe 1.4, a namespace must report an ID descriptor of UUID type
if it doesn't support EUI64 or NGUID. Add a new namespace property,
"uuid", that provides the user the option to either specify the UUID
explicitly or have a UUID generated automatically every time a
namespace is initialized.
With ZNS support in place, the majority of code in nvme_rw() has
become read- or write-specific. Move these parts to two separate
handlers, nvme_read() and nvme_write() to make the code more
readable and to remove multiple is_write checks that so far existed
in the i/o path.
This is a refactoring
Add two module properties, "max_active" and "max_open" to control
the maximum number of zones that can be active or open. Once these
variables are set to non-default values, these limits are checked
during I/O and Too Many Active or Too Many Open command status is
returned if they are exceeded.
Added brief descriptions of the new device properties that are
now available to users to configure features of Zoned Namespace
Command Set in the emulator.
This patch is for documentation only, no functionality change.
Signed-off-by: Dmitry Fomichev
---
hw/block/nvme.c | 41
This log page becomes necessary to implement to allow checking for
Zone Append command support in Zoned Namespace Command Set.
This commit adds the code to report this log page for NVM Command
Set only. The parts that are specific to zoned operation will be
added later in the series.
All
v5 -> v6
- Remove zoned state persistence code. Replace position-independent
zone lists with QTAILQs.
- Close all open zones upon clearing of the controller. This is
a similar procedure to the one previously performed upon powering
up with zone persistence.
- Squash NS Types and
From: Niklas Cassel
Define the structures and constants required to implement
Namespace Types support.
Namespace Types introduce a new command set, "I/O Command Sets",
that allows the host to retrieve the command sets associated with
a namespace. Introduce support for the command set and enable
Hi Marc-André,
On 10/13/20 10:25 PM, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
Add new commands to add and remove SSH public keys from
~/.ssh/authorized_keys.
I took a different approach for testing, including the unit tests right
with the code. I wanted to overwrite the
On Tue, Oct 13, 2020 at 09:08:46PM +0200, Klaus Jensen wrote:
> From: Klaus Jensen
>
> This adds support for reporting the Deallocated or Unwritten Logical
> Block error (DULBE). This requires tracking the allocated/deallocated
> status of all logical blocks.
>
> Introduce a bitmap that does
On 10/13/20 1:38 PM, Peter Maydell wrote:
> * has short-vector support (eg Cortex-A9)
> * v8A, can implement FPSCR.{Stride,Len} as RAZ/WI
> * no short-vector support, Stride/Len can be written
>but the only effect is that some insns must UNDEF
>(eg Cortex-A7)
Yep.
The other thing I
On Tue, 13 Oct 2020 at 21:37, Mihai Carabas wrote:
> Does anyone know if there is any progress with pvpanic patches that
> brings in mmio support [1]?
I don't think so. If I recall correctly there was quite a lot
of discussion on at least one version of that patchset, and it
was never clear to
Signed-off-by: Philippe Mathieu-Daudé
---
hw/misc/mac_via.c | 18 +-
1 file changed, 1 insertion(+), 17 deletions(-)
diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c
index 9e64c2521fc..54088b6625a 100644
--- a/hw/misc/mac_via.c
+++ b/hw/misc/mac_via.c
@@ -362,22 +362,6 @@
Rewrite via1_irq_request() as generic via_irq_request().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/misc/mac_via.c | 31 +++
1 file changed, 15 insertions(+), 16 deletions(-)
diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c
index 6db62dab7db..9e64c2521fc 100644
The same logic is used in 4 different places:
- via1_irq_request()
- via2_irq_request()
- via1_VBL()
- via1_one_second()
Extract the common function and reuse it.
Philippe Mathieu-Daudé (3):
hw/misc/mac_via: Make generic via_irq_request() from
via1_irq_request()
hw/misc/mac_via: Replace
via1_VBL() and via1_one_second() just call the generic
via_irq_request() handler raising a specific IRQ.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/misc/mac_via.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c
index
On Tue, 13 Oct 2020 at 21:06, Richard Henderson
wrote:
> I think these two sets of masking are confusing.
> Perhaps usefully rearranged as
>
> if (!fp16) {
> val &= ~fz16;
> }
> vfp_set_fpscr_to_host(env, val);
>
> if (!m-profile) {
> vec_len = extract32(val, 16,
Hi Paolo and Sean,
Thanks much for your prompt replies and clear explanations.
On Tue, Oct 13, 2020 at 2:43 AM Paolo Bonzini wrote:
>
> No, the logic to find the HPA with a given HVA is the same as the
> hardware logic to translate HVA -> HPA. That is it uses the host
> "regular" page tables,
Hey John,
Sorry for the late reply! I was in the midst of a job change and couldn't
get time to get to this.
The work sounds interesting! I have a couple of questions regarding this:
1. How do I actually build this part? I am familiar with building and
using QEMU. Does the qapi parser
Hello,
Does anyone know if there is any progress with pvpanic patches that
brings in mmio support [1]? I see no activity since late 2018, but I do
see support added to the kernel (also asking myself how this was tested):
46f934c misc/pvpanic: add support to get pvpanic device info FDT
Patchew URL:
https://patchew.org/QEMU/20201013202502.335336-1-marcandre.lur...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20201013202502.335336-1-marcandre.lur...@redhat.com
Subject: [PATCH 0/2]
From: Marc-André Lureau
Add new commands to add and remove SSH public keys from
~/.ssh/authorized_keys.
I took a different approach for testing, including the unit tests right
with the code. I wanted to overwrite the function to get the user
details, I couldn't easily do that over QMP.
From: Marc-André Lureau
The glib function was introduced in 2.64. It's a safer version of
getpwnam, and also simpler to use than getpwnam_r.
Currently, it's only use by the next patch in qemu-ga, which doesn't
(well well...) need the thread safety guarantees. Since the fallback
version is still
From: Marc-André Lureau
Hi,
Add two new commands to help modify ~/.ssh/authorized_keys.
Although it's possible already to modify the authorized_keys files via
file-{read,write} or exec, the commands are often denied by default, and the
logic is left to the client. Let's add specific commands
On Tue, 13 Oct 2020 at 18:30, Richard Henderson
wrote:
> Well, the only further comment is that, in the followup, only WLS gains the IT
> block check. While I understand that's required to avoid an abort in QEMU for
> this case, all three of the insns have that case as CONSTRAINED UNPREDICTABLE.
On 10/13/20 3:35 AM, Peter Maydell wrote:
> For AArch32, unlike the VCVT of integer to float, which honours the
> rounding mode specified by the FPSCR, VCVT of fixed-point to float is
> always round-to-nearest. (AArch64 fixed-point-to-float conversions
> always honour the FPCR rounding mode.)
>
>
On 10/12/20 8:37 AM, Peter Maydell wrote:
> @@ -198,8 +200,14 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t
> val)
> /*
> * M profile FPSCR is RES0 for the QC, STRIDE, FZ16, LEN bits
> * and also for the trapped-exception-handling bits IxE.
> + *
On 6/29/20 8:55 PM, BALATON Zoltan wrote:
OpenBIOS gets RAM size via fw_cfg but rhe original board firmware
Typo "the".
detects RAM using SPD data so generate and add SDP eeproms to cover as
EEPROMs?
much RAM as possible to describe with SPD (this may be less than the
actual ram_size due
On 6/29/20 8:55 PM, BALATON Zoltan wrote:
Values not used frequently enough may not worth putting in a local
variable, especially with names almost as long as the original value
because that does not improve readability, to the contrary it makes it
harder to see what value is used. Drop a few
On 6/29/20 8:55 PM, BALATON Zoltan wrote:
Fall back to load binary ROM image if loading ELF fails. This also
moves PROM_BASE and PROM_SIZE defines to board as these are matching
the ROM size and address on this board and removes the now unused
PROM_ADDR and BIOS_SIZE defines from common mac.h.
On 6/29/20 8:55 PM, BALATON Zoltan wrote:
Half of the occurances already use get_system_memory() directly
instead of sysmem variable, convert the two other uses to
get_system_memory() too which seems to be more common and drop the
variable.
Signed-off-by: BALATON Zoltan
Reviewed-by: Mark
On 10/13/20 7:22 PM, Georg Kotheimer wrote:
The HLVX.WU instruction is supposed to read a machine word,
but prior to this change it read a byte instead.
Fixes: 8c5362acb57 ("target/riscv: Allow generating hlv/hlvx/hsv
instructions")
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by:
this fixes non-TCG builds broken recently by replay reverse debugging.
stub the needed functions in stub/, including errors for hmp and qmp.
This includes duplicating some code in replay/, and puts the logic
for non-replay related events in the replay/ module (+ the stubs),
so this should be
From: Paolo Bonzini
remove dependency of check-block from non-native archs
Signed-off-by: Claudio Fontana
---
tests/Makefile.include | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/Makefile.include b/tests/Makefile.include
index 5aca98e60c..4037490b69 100644
---
the tests assume TCG is available, thus breaking
for TCG-only tests, where only the TCG accelerator option
is passed to the QEMU binary.
Suggested-by: Paolo Bonzini
Acked-by: Paolo Bonzini
Signed-off-by: Claudio Fontana
---
tests/qtest/bios-tables-test.c | 10 ++
1 file changed, 10
This series now unbreaks current non-tcg builds
(!CONFIG_TCG).
tests Makefiles need to avoid relying on all non-native
archs binaries to be present,
bios-tables-test needs to skip tests that are tcg-only,
and notably the replay framework needs to consider that
it might not be functional (or its
From: Klaus Jensen
This adds support for reporting the Deallocated or Unwritten Logical
Block error (DULBE). This requires tracking the allocated/deallocated
status of all logical blocks.
Introduce a bitmap that does this. The bitmap is always intialized to
all ones (aka, all blocks are
1 - 100 of 374 matches
Mail list logo
