[PATCH v2 32/40] target/hexagon: Add locks, id, next_PC to state

From: Brian Cain Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 34 +- target/hexagon/cpu.c | 4 target/hexagon/machine.c | 4 3 files changed, 41 insertions(+), 1 deletion(-) diff --git a/target/hexagon

Re: [PATCH 23/38] target/hexagon: Add implicit attributes to sysemu macros

On 3/11/2025 5:30 PM, ltaylorsimp...@gmail.com wrote: -Original Message- From: Brian Cain Sent: Friday, February 28, 2025 11:26 PM To: qemu-devel@nongnu.org Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a

[PATCH v2 34/40] target/hexagon: Add {TLB, k0}lock, cause code, wait_next_pc

From: Brian Cain {TLB,k0}lock counts are used to represent the TLB, k0 locks among hardware threads. wait_next_pc represents the program counter to set when resuming from a wait-for-interrupts state. cause_code contains the precise exception cause.This will be used by subsequent commits

[PATCH v2 39/39] target/hexagon: Add pcycle setting functionality

Signed-off-by: Brian Cain Signed-off-by: Matheus Tavares Bernardino --- target/hexagon/cpu_helper.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c index 5d0ba23d02..447421cdd0 100644 --- a/target/hexagon

Re: [PATCH 8/8] tests/functional: Add a hexagon minivm test

On 3/4/2025 9:46 AM, Philippe Mathieu-Daudé wrote: Hi Brian, On 1/3/25 18:20, Brian Cain wrote: From: Brian Cain A bit opaque... Signed-off-by: Brian Cain ---   MAINTAINERS |  1 +   tests/functional/meson.build    |  8 +   tests/functional

[PATCH v2 00/40] hexagon system emulation v2, part 1/3

"Add gdb support for sys regs" - checks / mutability of regs via gdbstub TBD * "Add initial MMU model" - hex_dump_mmu_entry, cpu_index Brian Cain (40): docs: Add hexagon sysemu docs docs/system: Add hexagon CPU emulation target/hexagon: Fix badva reference, delete C

[PATCH v2 31/39] target/hexagon: Add implicit sysreg writes

From: Brian Cain Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/translate.c | 16 1 file changed, 16 insertions(+) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 70e0a1ff33..743c96e6e1 100644 --- a/target/hexagon

[PATCH v2 15/40] target/hexagon: Add guest/sys reg writes to DisasContext

From: Brian Cain Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/translate.h | 36 1 file changed, 36 insertions(+) diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 4c1868369a..c3806fe068 100644 --- a

[PATCH v2 29/40] target/hexagon: Add TCG overrides for thread ctl

From: Brian Cain Define TCG overrides for start, stop, wait, resume instructions. Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/gen_tcg_sys.h | 18 ++ target/hexagon/helper.h | 4 target/hexagon/op_helper.c | 20 3

[PATCH v2 28/39] target/hexagon: Implement modify_ssr, resched, pending_interrupt

From: Brian Cain Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/helper.h| 5 + target/hexagon/op_helper.c | 20 2 files changed, 25 insertions(+) diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h index 730eaf8b9a

[PATCH v2 09/39] target/hexagon: Implement arch_get_system_reg()

From: Brian Cain Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/cpu_helper.c | 33 - 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c index 1a1520214e..4732a698b4

Re: [PATCH 09/38] target/hexagon: Add guest, system reg number state

On 3/12/2025 2:15 PM, Philippe Mathieu-Daudé wrote: Hi Brian, On 1/3/25 06:25, Brian Cain wrote: From: Brian Cain Signed-off-by: Brian Cain ---   target/hexagon/cpu.h |  8   target/hexagon/cpu.c | 17 +   2 files changed, 25 insertions(+) diff --git a/target

[PATCH v2 03/11] hw/hexagon: Add machine configs for sysemu

From: Brian Cain Some header includes are modified here: these are uniquely required for basic system emulation functionality and had not been required for linux-user. Acked-by: Markus Armbruster Co-authored-by: Mike Lambert Co-authored-by: Sid Manning Signed-off-by: Brian Cain

[PATCH v2 04/11] hw/hexagon: Add v68, sa8775-cdsp0 defs

From: Brian Cain Acked-by: Taylor Simpson Signed-off-by: Brian Cain --- hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc | 63 ++ hw/hexagon/machine_cfg_v68n_1024.h.inc| 64 +++ 2 files changed, 127 insertions(+) create mode 100644 hw/hexagon

[PATCH v2 03/39] target/hexagon: Implement iassign{r,w} helpers

From: Brian Cain iassign{r,w} are the "Interrupt to thread assignment {read,write}" instructions. Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/op_helper.c | 48 -- 1 file changed, 46 insertions(+), 2 deletions(-) di

[PATCH v2 08/39] target/hexagon: Implement get_exe_mode()

From: Brian Cain Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/reg_fields_def.h.inc | 11 +++ target/hexagon/cpu_helper.c | 23 +++ 2 files changed, 34 insertions(+) diff --git a/target/hexagon/reg_fields_def.h.inc b/target

Re: [PATCH 38/38] target/hexagon: Add hex_interrupts support

On 3/12/2025 12:32 PM, ltaylorsimp...@gmail.com wrote: -Original Message- From: Brian Cain Sent: Friday, February 28, 2025 11:26 PM To: qemu-devel@nongnu.org Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a

[PATCH v2 22/39] target/hexagon: Implement setprio, resched

From: Brian Cain The hardware-assisted scheduler helps manage tasks on the run queue and interrupt steering. This instruction is defined in the Qualcomm Hexagon V71 Programmer's Reference Manual - https://docs.qualcomm.com/bundle/publicresource/80-

[PATCH v2 10/39] target/hexagon: Implement arch_{s, g}et_{thread, system}_reg()

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu_helper.h | 15 --- target/hexagon/cpu_helper.c | 16 2 files changed, 24 insertions(+), 7 deletions(-) diff --git a/target/hexagon/cpu_helper.h b/target/hexagon/cpu_helper.h index e8d89d8526

[PATCH v2 30/40] target/hexagon: Add TCG overrides for rte, nmi

From: Brian Cain Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/gen_tcg_sys.h | 19 +++ target/hexagon/helper.h | 1 + target/hexagon/op_helper.c | 4 3 files changed, 24 insertions(+) diff --git a/target/hexagon/gen_tcg_sys.h b/target

Re: [PATCH 05/39] target/hexagon: Implement modify SSR

On 3/19/2025 11:58 AM, Richard Henderson wrote: On 3/19/25 09:39, ltaylorsimp...@gmail.com wrote: I caution against putting a level of indirection into CPUHexagonState for the HVX registers.  The HVX TCG implementation relies on an offset from the start of CPUHexagonState to identify the oper

Re: [PATCH 1/8] hw/intc: Add l2vic interrupt controller

On 3/24/2025 2:40 PM, ltaylorsimp...@gmail.com wrote: -Original Message- From: Brian Cain Sent: Saturday, March 1, 2025 11:21 AM To: qemu-devel@nongnu.org Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a

Re: [PATCH 01/39] target/hexagon: Implement ciad helper

On 3/17/2025 11:08 AM, ltaylorsimp...@gmail.com wrote: -Original Message- From: Brian Cain Sent: Friday, February 28, 2025 11:28 PM To: qemu-devel@nongnu.org Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a

Re: [PATCH 12/38] target/hexagon: Add imported macro, attr defs for sysemu

On 3/7/2025 1:01 PM, ltaylorsimp...@gmail.com wrote: -Original Message- From: Brian Cain Sent: Friday, February 28, 2025 11:26 PM To: qemu-devel@nongnu.org Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a

[PATCH v2 18/39] target/hexagon: add simple cpu_exec_reset and pointer_wrap

From: Matheus Tavares Bernardino Signed-off-by: Matheus Tavares Bernardino --- target/hexagon/cpu.c | 8 1 file changed, 8 insertions(+) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 85ccf9893a..0445146f2b 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @

[PATCH v2 38/39] target/hexagon: Add guest reg reading functionality

From: Matheus Tavares Bernardino Signed-off-by: Matheus Tavares Bernardino --- target/hexagon/cpu.c | 19 ++- target/hexagon/op_helper.c | 19 +-- 2 files changed, 35 insertions(+), 3 deletions(-) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c in

[PATCH v2 29/39] target/hexagon: Add pkt_ends_tb to translation

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/translate.h | 1 + target/hexagon/translate.c | 102 - 2 files changed, 101 insertions(+), 2 deletions(-) diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 0bdf526a9e

[PATCH v2 20/39] target/hexagon: Implement siad inst

From: Brian Cain siad is the 'Set interrupt auto disable' instruction. Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/op_helper.c | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/target/hexagon/op_helper.c b/target/hexagon/o

Re: [PATCH 04/39] target/hexagon: Implement start/stop helpers

On 3/17/2025 11:35 AM, ltaylorsimp...@gmail.com wrote: -Original Message- From: Brian Cain Sent: Friday, February 28, 2025 11:28 PM To: qemu-devel@nongnu.org Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a

Re: [PATCH 21/38] target/hexagon: Add system reg insns

On 3/7/2025 7:32 PM, ltaylorsimp...@gmail.com wrote: -Original Message- From: Brian Cain Sent: Friday, February 28, 2025 11:26 PM To: qemu-devel@nongnu.org Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a

[PATCH v2 21/39] target/hexagon: Implement hexagon_resume_threads()

From: Brian Cain Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/cpu.h| 1 + target/hexagon/cpu_helper.h | 1 + target/hexagon/cpu_helper.c | 76 + target/hexagon/op_helper.c | 3 +- 4 files changed, 80 insertions(+), 1

[PATCH v2 25/40] target/hexagon: Add system reg insns

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/hex_common.py | 15 +- target/hexagon/imported/encode_pp.def | 213 +++-- target/hexagon/imported/system.idef | 262 +++--- 3 files changed, 408 insertions(+), 82 deletions(-) diff

Re: [PATCH 38/39] target/hexagon: Add guest reg reading functionality

On 3/19/2025 1:36 PM, ltaylorsimp...@gmail.com wrote: -Original Message- From: Brian Cain Sent: Friday, February 28, 2025 11:29 PM To: qemu-devel@nongnu.org Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a

[PATCH v2 30/39] target/hexagon: Add next_PC, {s,g}reg writes

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/translate.h | 2 + target/hexagon/genptr.c| 7 +- target/hexagon/translate.c | 134 - 3 files changed, 123 insertions(+), 20 deletions(-) diff --git a/target/hexagon/translate.h b/target

[PATCH v2 27/40] target/hexagon: Add implicit attributes to sysemu macros

From: Brian Cain Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/hex_common.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index 009b71f8e6..39451e6d88 100755 --- a/target/hexagon/hex_common.py

[PATCH v2 05/39] target/hexagon: Implement modify SSR

From: Brian Cain The per-vCPU System Status Register controls many modal behaviors of the system architecture. When the SSR is updated, we trigger the necessary effects for interrupts, privilege/MMU, and HVX context mapping. Signed-off-by: Brian Cain --- target/hexagon/cpu_helper.c | 33

[PATCH v2 08/11] hw/hexagon: Define hexagon "virt" machine

From: Brian Cain Signed-off-by: Brian Cain --- configs/devices/hexagon-softmmu/default.mak | 1 + configs/targets/hexagon-softmmu.mak | 1 + include/hw/hexagon/virt.h | 43 ++ hw/hexagon/virt.c | 435 hw/hexagon

[PATCH v2 37/40] target/hexagon: Add initial MMU model

From: Brian Cain Co-authored-by: Taylor Simpson Co-authored-by: Michael Lambert Co-authored-by: Sid Manning Co-authored-by: Matheus Tavares Bernardino Signed-off-by: Brian Cain --- target/hexagon/cpu-param.h | 4 + target/hexagon/cpu.h | 8 + target/hexagon/hex_mmu.h | 30

[PATCH v2 33/39] target/hexagon: initialize sys/guest reg TCGvs

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/translate.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 743c96e6e1..01a236d108 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon

Re: [PATCH 34/38] target/hexagon: Add initial MMU model

On 3/12/2025 12:04 PM, ltaylorsimp...@gmail.com wrote: -Original Message- From: Brian Cain Sent: Friday, February 28, 2025 11:26 PM To: qemu-devel@nongnu.org Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a

[PATCH v2 05/11] hw/hexagon: Add support for cfgbase

From: Sid Manning Reviewed-by: Taylor Simpson Signed-off-by: Sid Manning --- hw/hexagon/hexagon_dsp.c | 10 ++ target/hexagon/cpu.c | 2 ++ 2 files changed, 12 insertions(+) diff --git a/hw/hexagon/hexagon_dsp.c b/hw/hexagon/hexagon_dsp.c index d491a21a76..486dc41f5d 100644 --- a

Re: [PATCH 30/39] target/hexagon: Add next_PC, {s,g}reg writes

On 3/18/2025 1:50 PM, ltaylorsimp...@gmail.com wrote: -Original Message- From: Brian Cain Sent: Friday, February 28, 2025 11:29 PM To: qemu-devel@nongnu.org Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a

[PATCH v2 32/39] target/hexagon: Define system, guest reg names

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/internal.h | 2 ++ target/hexagon/cpu.c | 29 + 2 files changed, 31 insertions(+) diff --git a/target/hexagon/internal.h b/target/hexagon/internal.h index 94e5e502a9..a9eb5645f1 100644 --- a/target

[PATCH v2 12/40] target/hexagon: Add guest, system reg number defs

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 5 ++ target/hexagon/hex_regs.h | 115 ++ 2 files changed, 120 insertions(+) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index df1f2b569c..46e0dc9d0b 100644 --- a

[PATCH v2 15/39] target/hexagon: Implement hex_tlb_lookup_by_asid()

From: Brian Cain Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/hex_mmu.c | 30 -- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/target/hexagon/hex_mmu.c b/target/hexagon/hex_mmu.c index 8f9f16158f..476796265b 100644 --- a

[PATCH v2 12/39] target/hexagon: Add implementation of cycle counters

From: Brian Cain The PCYCLE register is available in system mode, but only increments when the SYSCFG.PCYCLEEN field is set. The UPCYCLE register is available in user mode and we model it unconditionally in linux-user emulation, as if the system had enabled PCYCCLEEN. For now, the model is

[PATCH v2 09/11] tests/qtest: Add hexagon boot-serial-test

Add boot-serial-test support for Hexagon architecture using the virt machine. Signed-off-by: Brian Cain --- tests/qtest/boot-serial-test.c | 8 tests/qtest/meson.build| 2 ++ 2 files changed, 10 insertions(+) diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot

[PATCH v2 06/40] target/hexagon: Make gen_exception_end_tb non-static

From: Brian Cain Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/translate.h | 2 ++ target/hexagon/translate.c | 9 - 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index d251e2233f

[PATCH v2 01/39] target/hexagon: Implement ciad helper

From: Brian Cain ciad is the clear interrupt auto disable instruction. Signed-off-by: Brian Cain --- target/hexagon/op_helper.c | 45 +- 1 file changed, 39 insertions(+), 6 deletions(-) diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c

[PATCH v2 31/40] target/hexagon: Add sreg_{read,write} helpers

From: Brian Cain Co-authored-by: Sid Manning Signed-off-by: Brian Cain --- target/hexagon/cpu_helper.h | 8 ++ target/hexagon/cpu.c| 1 - target/hexagon/cpu_helper.c | 37 + target/hexagon/op_helper.c | 152 +++- 4 files changed, 193

Re: [PATCH 33/38] target/hexagon: Add gdb support for sys regs

On 2/28/2025 11:26 PM, Brian Cain wrote: From: Brian Cain Co-authored-by: Matheus Tavares Bernardino Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 6 ++ target/hexagon/internal.h | 4 ++ target/hexagon/cpu.c | 17 ++ target/hexagon/gdbstub.c | 45

Re: [PATCH 39/39] target/hexagon: Add pcycle setting functionality

On 3/19/2025 1:49 PM, ltaylorsimp...@gmail.com wrote: -Original Message- From: Brian Cain Sent: Friday, February 28, 2025 11:29 PM To: qemu-devel@nongnu.org Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a

Re: [PATCH 12/39] target/hexagon: Add implementation of cycle counters

On 4/1/2025 9:42 PM, Brian Cain wrote: On 3/19/2025 2:50 PM, ltaylorsimp...@gmail.com wrote: -Original Message- From: Brian Cain Sent: Friday, February 28, 2025 11:28 PM To:qemu-devel@nongnu.org Cc:brian.c...@oss.qualcomm.com;richard.hender...@linaro.org; phi...@linaro.org

[PATCH v2 39/40] target/hexagon: Define f{S,G}ET_FIELD macros

From: Brian Cain Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/macros.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index 4823c97fde..5c3a4a533c 100644 --- a/target/hexagon/macros.h +++ b/target

Re: [PATCH 17/39] target/hexagon: Implement software interrupt

On 3/19/2025 4:28 PM, ltaylorsimp...@gmail.com wrote: -Original Message- From: Brian Cain Sent: Friday, February 28, 2025 11:28 PM To: qemu-devel@nongnu.org Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a

Re: [PATCH 24/39] target/hexagon: Add exec-start-addr prop

On 3/17/2025 3:03 PM, ltaylorsimp...@gmail.com wrote: -Original Message- From: Brian Cain Sent: Friday, February 28, 2025 11:29 PM To: qemu-devel@nongnu.org Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a

Re: [PATCH 22/39] target/hexagon: Implement setprio, resched

On 3/20/2025 5:28 PM, ltaylorsimp...@gmail.com wrote: -Original Message- From: Sid Manning Sent: Thursday, March 20, 2025 3:26 PM To: ltaylorsimp...@gmail.com; 'Brian Cain' ; qemu-devel@nongnu.org Cc: richard.hender...@linaro.org; phi...@linaro.org; Matheus Bernardino

Re: [PATCH 13/39] target/hexagon: Implement modify_syscfg()

On 3/19/2025 4:12 PM, ltaylorsimp...@gmail.com wrote: -Original Message- From: Brian Cain Sent: Friday, February 28, 2025 11:28 PM To: qemu-devel@nongnu.org Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a

Re: [PATCH 11/39] target/hexagon: Add representation to count cycles

On 3/17/2025 2:33 PM, ltaylorsimp...@gmail.com wrote: -Original Message- From: Brian Cain Sent: Friday, February 28, 2025 11:28 PM To: qemu-devel@nongnu.org Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a

Re: [PATCH 07/39] target/hexagon: Implement wait helper

On 3/17/2025 1:37 PM, ltaylorsimp...@gmail.com wrote: -Original Message- From: Brian Cain Sent: Friday, February 28, 2025 11:28 PM To: qemu-devel@nongnu.org Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a

Re: [PATCH 10/39] target/hexagon: Implement arch_{s,g}et_{thread,system}_reg()

On 3/17/2025 2:24 PM, ltaylorsimp...@gmail.com wrote: -Original Message- From: Brian Cain Sent: Friday, February 28, 2025 11:28 PM To: qemu-devel@nongnu.org Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a

Re: [PATCH 06/39] target/hexagon: Implement {g,s}etimask helpers

On 3/21/2025 4:48 PM, Sid Manning wrote: -Original Message- From: ltaylorsimp...@gmail.com Sent: Monday, March 17, 2025 12:44 PM To: 'Brian Cain' ; qemu-devel@nongnu.org Cc: richard.hender...@linaro.org; phi...@linaro.org; Matheus Bernardino (QUIC) ; a...@rev.ng; a...@rev

[PATCH v2 33/40] target/hexagon: Add a TLB count property

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 2 ++ target/hexagon/cpu.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index fc6552e64c..8b1ff23c01 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h

Re: [PATCH 22/38] target/hexagon: Add sysemu TCG overrides

On 3/7/2025 7:43 PM, ltaylorsimp...@gmail.com wrote: -Original Message- From: Brian Cain Sent: Friday, February 28, 2025 11:26 PM To: qemu-devel@nongnu.org Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a

Re: [PATCH 03/38] target/hexagon: Add System/Guest register definitions

On 4/16/2025 5:02 PM, ltaylorsimp...@gmail.com wrote: -Original Message- From: Brian Cain Sent: Wednesday, April 16, 2025 1:43 PM To: ltaylorsimp...@gmail.com; qemu-devel@nongnu.org Cc: richard.hender...@linaro.org; phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a

[PATCH v2 06/39] target/hexagon: Implement {g,s}etimask helpers

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/op_helper.c | 33 +++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 4b1fc23a15..03e69421c7 100644 --- a/target/hexagon

[PATCH v2 24/39] target/hexagon: Add exec-start-addr prop

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 1 + target/hexagon/cpu.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 92b32f434b..39d6983263 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -196,6

[PATCH v2 04/39] target/hexagon: Implement start/stop helpers, soft reset

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu.h| 1 + target/hexagon/cpu_helper.h | 3 ++ target/hexagon/cpu.c| 18 ++- target/hexagon/cpu_helper.c | 94 + target/hexagon/op_helper.c | 4 +- 5 files changed, 117

[PATCH v2 20/40] target/hexagon: Add placeholder greg/sreg r/w helpers

From: Brian Cain Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/helper.h| 9 + target/hexagon/op_helper.c | 34 ++ 2 files changed, 43 insertions(+) diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h index

[PATCH v2 02/39] target/hexagon: Implement {c,}swi helpers

From: Brian Cain {c,}swi are the "software interrupt"/"Cancel pending interrupts" instructions. Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/op_helper.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/target/hexagon/

[PATCH v2 00/11] hexagon system emulation v2, part 3/3

h this and/or QTimer out of this series to simplify things a bit. Brian Cain (8): hw/hexagon: Add globalreg model hw/hexagon: Add global register tracing hw/hexagon: Add machine configs for sysemu hw/hexagon: Add v68, sa8775-cdsp0 defs hw/hexagon: Modify "Standalone" symb

[PATCH v2 11/39] target/hexagon: Add representation to count cycles

From: Brian Cain The PCYCLE register can be enabled to indicate accumulated clock cycles. Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 2 +- target/hexagon/machine.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h

[PATCH v2 40/40] target/hexagon: Add hex_interrupts support

From: Brian Cain Co-authored-by: Taylor Simpson Co-authored-by: Sid Manning Co-authored-by: Michael Lambert Signed-off-by: Brian Cain --- target/hexagon/cpu.h| 1 + target/hexagon/hex_interrupts.h | 15 ++ target/hexagon/cpu.c| 2 + target/hexagon

[PATCH v2 37/39] target/hexagon: Add support for loadw_phys

From: Brian Cain Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/hex_common.py | 3 +++ target/hexagon/imported/encode_pp.def | 1 + target/hexagon/imported/ldst.idef | 3 +++ 3 files changed, 7 insertions(+) diff --git a/target/hexagon/hex_common.py b

[PATCH v2 34/39] target/hexagon: Add TLB, k0 {un,}lock

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/sys_macros.h | 8 +-- target/hexagon/op_helper.c | 104 2 files changed, 108 insertions(+), 4 deletions(-) diff --git a/target/hexagon/sys_macros.h b/target/hexagon/sys_macros.h index

[PATCH v2 13/40] target/hexagon: Add guest, system reg number state

From: Brian Cain Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 7 +++ target/hexagon/cpu.c | 4 2 files changed, 11 insertions(+) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 46e0dc9d0b..42b877a04c 100644 --- a/target/hexagon

[PATCH v2 11/11] hw/intc: Add l2vic interrupt controller

From: Sid Manning Co-authored-by: Matheus Tavares Bernardino Co-authored-by: Damien Hedde Signed-off-by: Brian Cain --- MAINTAINERS| 2 + docs/devel/hexagon-l2vic.rst | 59 + docs/devel/index-internals.rst | 1 + include/hw/intc/l2vic.h| 38 +++ hw

[PATCH v2 23/39] target/hexagon: Add sysemu_ops, cpu_get_phys_page_debug()

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu.c | 31 +++ 1 file changed, 31 insertions(+) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 2ae6874841..2af0b4089e 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c

[PATCH v2 01/11] hw/hexagon: Add globalreg model

Some of the system registers are shared among all threads in the core. This object contains the representation and interface to the system registers. Signed-off-by: Brian Cain --- include/hw/hexagon/hexagon_globalreg.h | 60 ++ target/hexagon/cpu.h | 1 + hw/hexagon

[PATCH v2 05/40] target/hexagon: Handle system/guest registers in gen_analyze_funcs.py and hex_common.py

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/gen_analyze_funcs.py | 21 +++- target/hexagon/hex_common.py| 161 2 files changed, 179 insertions(+), 3 deletions(-) diff --git a/target/hexagon/gen_analyze_funcs.py b/target/hexagon

[PATCH v2 10/11] hw/timer: Add QTimer device

From: Sid Manning Note: QTimer was implemented before ARM SSE Timer was upstreamed, there may be opportunity to use that device instead. Co-authored-by: Damien Hedde Co-authored-by: Tobias Röhmel Signed-off-by: Brian Cain --- MAINTAINERS| 2 + include/hw/timer/qct

[PATCH v2 19/39] target/hexagon: Implement hexagon_tlb_fill()

From: Brian Cain Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/cpu.c | 134 ++- 1 file changed, 133 insertions(+), 1 deletion(-) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 0445146f2b..2ae6874841 100644

[PATCH v2 22/40] target/hexagon: Make A_PRIV, "J2_trap*" insts need_env()

From: Brian Cain Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/hex_common.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index fa122b6d76..fe5263e13f 100755 --- a/target/hexagon

[PATCH v2 01/40] docs: Add hexagon sysemu docs

From: Brian Cain Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- MAINTAINERS| 3 + docs/devel/hexagon-sys.rst | 112 + docs/devel/index-internals.rst | 1 + docs/system/hexagon/cdsp.rst | 12 docs/system/target

[PATCH v2 36/40] target/hexagon: Add gdb support for sys regs

From: Brian Cain Co-authored-by: Matheus Tavares Bernardino Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 6 ++ target/hexagon/internal.h | 4 ++ target/hexagon/cpu.c | 17 ++ target/hexagon/gdbstub.c | 45 ++ target/hexagon/op_helper.c | 22

[PATCH v2 07/11] target/hexagon: add build config for softmmu

Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- MAINTAINERS | 1 + configs/devices/hexagon-softmmu/default.mak | 7 +++ configs/targets/hexagon-softmmu.mak | 6 ++ target/hexagon/cpu.h| 4 target/Kconfig

[PATCH v2 07/39] target/hexagon: Implement wait helper

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu_helper.h | 1 + target/hexagon/op_helper.c | 6 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/target/hexagon/cpu_helper.h b/target/hexagon/cpu_helper.h index 95a0cc0788..e8d89d8526 100644 --- a/target

Re: [PATCH 20/38] target/hexagon: Implement do_raise_exception()

On 3/7/2025 3:28 PM, ltaylorsimp...@gmail.com wrote: -Original Message- From: Brian Cain Sent: Friday, February 28, 2025 11:26 PM To: qemu-devel@nongnu.org Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a

[PATCH v2 21/40] target/hexagon: Add vmstate representation

From: Brian Cain Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/internal.h | 4 target/hexagon/cpu.c | 3 +++ target/hexagon/machine.c | 25 + 3 files changed, 32 insertions(+) create mode 100644 target/hexagon/machine.c diff

[PATCH v2 14/40] target/hexagon: Add TCG values for sreg, greg

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/translate.h | 5 + target/hexagon/translate.c | 2 ++ 2 files changed, 7 insertions(+) diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 2bd125297a..4c1868369a 100644 --- a/target/hexagon/translate.h

Re: [PATCH 14/38] target/hexagon: Add new macro definitions for sysemu

On 3/7/2025 1:35 PM, ltaylorsimp...@gmail.com wrote: -Original Message- From: Brian Cain Sent: Friday, February 28, 2025 11:26 PM To: qemu-devel@nongnu.org Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a

[PATCH v2 25/39] target/hexagon: extend hexagon_cpu_mmu_index() for sysemu

From: Brian Cain Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/cpu_helper.h | 1 + target/hexagon/cpu.c| 26 ++- target/hexagon/cpu_helper.c | 41 + 3 files changed, 63 insertions(+), 5 deletions

[PATCH v2 00/39] hexagon system emulation v2, part 2/3

- don't use ULL for UINT32 * "Define system, guest reg names" - fix last five reg names * "Add TLB, k0 {un,}lock" - revisit design with suggestion from Richard * "Define gen_precise_exception" - reword commit subject Brian Cain (37): target/hexagon: Implemen

[PATCH v2 09/40] target/hexagon: Add privilege check, use tag_ignore()

From: Brian Cain Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/cpu.h| 1 + linux-user/hexagon/cpu_loop.c | 16 target/hexagon/cpu.c| 1 + target/hexagon/translate.c | 8 target/hexagon/gen_tcg_funcs.py | 32

[PATCH v2 04/40] target/hexagon: Add missing A_CALL attr, hintjumpr to multi_cof

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/hex_common.py | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index 758e5fd12d..e60e8efabc 100755 --- a/target/hexagon/hex_common.py +++ b/target

Re: [PATCH 28/38] target/hexagon: Initialize htid, modectl regs

On 3/20/2025 12:38 PM, Sid Manning wrote: -Original Message- From: Richard Henderson Sent: Thursday, March 20, 2025 10:34 AM To: Sid Manning ; ltaylorsimp...@gmail.com; 'Philippe Mathieu-Daudé' ; 'Brian Cain' ; qemu-devel@nongnu.org Cc: Matheus Bernardino (QU

Re: [PATCH 10/38] target/hexagon: Add TCG values for sreg, greg

On 3/6/2025 3:38 PM, ltaylorsimp...@gmail.com wrote: -Original Message- From: Brian Cain Sent: Friday, February 28, 2025 11:26 PM To: qemu-devel@nongnu.org Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a

[PATCH v2 10/40] target/hexagon: Add memory order definition

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu-param.h | 5 + 1 file changed, 5 insertions(+) diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h index 635d509e74..22bffa7881 100644 --- a/target/hexagon/cpu-param.h +++ b/target/hexagon/cpu-param.h

[PATCH v2 36/39] target/hexagon: Add TCG overrides for transfer insts

From: Brian Cain Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/gen_tcg_sys.h | 25 + 1 file changed, 25 insertions(+) diff --git a/target/hexagon/gen_tcg_sys.h b/target/hexagon/gen_tcg_sys.h index 6d73a18db4..e56553462f 100644 --- a/target

Re: [PATCH 15/38] target/hexagon: Add handlers for guest/sysreg r/w

On 3/7/2025 1:46 PM, ltaylorsimp...@gmail.com wrote: -Original Message- From: Brian Cain Sent: Friday, February 28, 2025 11:26 PM To: qemu-devel@nongnu.org Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a

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