On 20-05-2024 11:43, Cédric Le Goater wrote:
On 5/15/24 19:41, Chalapathi V wrote:
In this commit Write a qtest pnv-spi-seeprom-test to check the
SPI transactions between spi controller and seeprom device.
Signed-off-by: Chalapathi V
---
tests/qtest/pnv-spi-seeprom-test.c | 129
Hello Cedric,
Thank You for reviewing the patch v3
Regards,
Chalapathi
On 20-05-2024 11:19, Cédric Le Goater wrote:
On 5/15/24 19:41, Chalapathi V wrote:
SPI controller device model supports a connection to a single SPI
responder.
This provide access to SPI seeproms, TPM, flash device
On 20-05-2024 11:19, Cédric Le Goater wrote:
On 5/15/24 19:41, Chalapathi V wrote:
SPI controller device model supports a connection to a single SPI
responder.
This provide access to SPI seeproms, TPM, flash device and an ADC
controller.
All SPI function control is mapped into the SPI
/5 will make it big. Hence made a
logical partition.
On Thu, 2024-05-16 at 11:33 -0500, Chalapathi V wrote:
In this commit SPI shift engine and sequencer logic is implemented.
Shift engine performs serialization and de-serialization according to
the
control by the sequencer and according
Hello Glen,
Thank You for reviewing the patch.
Regards,
Chalapathi
On 17-05-2024 21:57, Miles Glenn wrote:
Hi Chalapathi,
Looks good. Just some suggestions on readability and some
simplifications (see below).
Thanks,
Glenn
On Thu, 2024-05-16 at 11:33 -0500, Chalapathi V wrote:
SPI
data transmit and data receive control of the shift engine.
Signed-off-by: Chalapathi V
---
include/hw/ssi/pnv_spi.h| 28 +
hw/ppc/pnv_spi_controller.c | 1074 +++
hw/ppc/trace-events | 15 +
3 files changed, 1117 insertions(+)
diff --git a/include
In this commit Write a qtest pnv-spi-seeprom-test to check the
SPI transactions between spi controller and seeprom device.
Signed-off-by: Chalapathi V
---
tests/qtest/pnv-spi-seeprom-test.c | 129 +
tests/qtest/meson.build| 1 +
2 files changed, 130
)
/machine (powernv10-machine)
/peripheral-anon (container)
/device[0] (25csm04)
/WP#[0] (irq)
/ssi-gpio-cs[0] (irq)
(qemu) qom-get /machine/peripheral-anon /device[76] "parent_bus"
"/machine/chip[0]/pib_spic[2]/pnv-spi-bus.2"
Signed-off-by: Chalapathi V
to check the SPI transactions
between spi controller and seeprom device.
Test covered:
Ran make check.
Thank You,
Chalapathi
Chalapathi V (5):
ppc/pnv: Add SPI controller model
ppc/pnv: Extend SPI model
hw/block: Add Microchip's 25CSM04 to m25p80
hw/ppc: SPI controller wiring to P10
is modelled
which contains all SPI configuration and status registers as well as the hold
registers for data to be sent or having been received.
An existing QEMU SSI framework is used and SSI_BUS is created.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_xscom.h| 3 +
include/hw/ssi
reliable
and dependable nonvolatile memory storage is essential.
Signed-off-by: Chalapathi V
---
hw/block/m25p80.c | 3 +++
hw/ppc/Kconfig| 1 +
2 files changed, 4 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index 8dec134832..824a6c5c60 100644
--- a/hw/block/m25p80.c
+++ b/hw
Hello Cedric,
Thank You for reviewing v2 patches.
Regards,
Chalapathi
On 22-04-2024 20:33, Cédric Le Goater wrote:
On 4/9/24 19:56, Chalapathi V wrote:
In this commit
Creates SPI controller on p10 chip.
Create the keystore seeprom of type "seeprom-25csm04"
Connect the cs
On 16-04-2024 15:09, Cédric Le Goater wrote:
Hello,
Please rephrase the subject to something like:
"ppc/pnv: Extend SPI model ..."
Using a verb is preferable.
Sure. Will update. Thank You.
On 4/9/24 19:56, Chalapathi V wrote:
In this commit SPI shift engine and seque
On 15-04-2024 20:44, Cédric Le Goater wrote:
Hello Chalapathi
The subject could be rephrased to : "ppc/pnv: Add SPI controller model".
On 4/9/24 19:56, Chalapathi V wrote:
SPI controller device model supports a connection to a single SPI
responder.
This provide access to SPI see
_bus"
"/machine/chip[0]/pib_spic[2]/bus/pnv-spi-bus.2"
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_chip.h | 3 +++
hw/ppc/pnv.c | 36 +++-
2 files changed, 38 insertions(+), 1 deletion(-)
diff --git a/include/hw/ppc/pnv_chip.h b/i
In this commit Write a qtest pnv-spi-seeprom-test to check the
SPI transactions between spi controller and seeprom device.
Signed-off-by: Chalapathi V
---
tests/qtest/pnv-spi-seeprom-test.c | 126 +
tests/qtest/meson.build| 1 +
2 files changed, 127
is modelled
which contains all SPI configuration and status registers as well as the hold
registers for data to be sent or having been received.
An existing QEMU SSI framework is used and SSI_BUS is created.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_spi_controller.h | 55
bytes of 8 bits each (512Kbyte) and
is optimized for use in consumer and industrial applications where reliable
and dependable nonvolatile memory storage is essential.
This seeprom device is created from a parent "ssi-peripheral".
Signed-off-by: Chalapathi V
---
include/hw/misc/seeprom
CH6: Write a qtest pnv-spi-seeprom-test to check the SPI transactions
between spi controller and seeprom device.
Test covered:
Ran make check.
Thank You,
Chalapathi
Chalapathi V (6):
hw/ppc: remove SPI responder model
hw/ppc: SPI controller model - registers implementation
hw/ppc: SPI
data transmit and data receive control of the shift engine.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_spi_controller.h | 72 ++
hw/ppc/pnv_spi_controller.c | 1311 ++-
2 files changed, 1382 insertions(+), 1 deletion(-)
diff --git a/include/hw/ppc
-- Empty commit to align the patch numbers between PATCH v1 and PATCH v2.
SPI responder model is removed as pnv spi controller and seeprom is
implemented using QEMU SSI framework.
Signed-off-by: Chalapathi V
On 01-03-2024 22:06, Cédric Le Goater wrote:
Chalapathi,
On 3/1/24 17:17, Chalapathi V wrote:
Hello,
I would greatly appreciate the review comments/suggestions on PATCH V1.
Thank You and Regards,
I didn't forget but I lacked the time in this release cycle. Sorry
about that.
I have one
Hello,
I would greatly appreciate the review comments/suggestions on PATCH V1.
Thank You and Regards,
Chalapathi
On 07-02-2024 21:38, Chalapathi V wrote:
Hello,
In this series of patchset, SPI controller and responder models
for Power10 processor are modelled.
Serial peripheral interface
data transmit and data receive control of the shift engine.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_spi_controller.h | 58 ++
hw/ppc/pnv_spi_controller.c | 1274 ++-
2 files changed, 1331 insertions(+), 1 deletion(-)
diff --git a/include/hw/ppc
bytes of 8 bits each (512Kbyte) and
is optimized for use in consumer and industrial applications where reliable
and dependable nonvolatile memory storage is essential.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_spi_seeprom.h | 70 +++
hw/ppc/pnv_spi_seeprom.c | 989
that single responder is connected to
bus, hence chip_select is not modelled.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_spi_responder.h | 109 +++
hw/ppc/pnv_spi_responder.c | 166 +
hw/ppc/meson.build | 1 +
3 files
gisters.
PATCH3: SPI controller model: implement sequencer FSM and shift engine.
PATCH4: create SPI SEEPROM model.
PATCH5: Connect SPI controllers to p10 chip and create keystore seeprom
device on spi_bus2 of PIB_SPIC[2].
Thank You,
Chalapathi
Chalapathi V (5):
hw/ppc: SPI responder
This commit creates SPI controller to p10 chip and create the keystore seeprom
device on spi_bus2 of PIB_SPIC[2].
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_chip.h | 4
hw/ppc/pnv.c | 32
2 files changed, 36 insertions(+)
diff --git
is modelled
which contains all SPI configuration and status registers as well as the hold
registers for data to be sent or having been received.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_spi_controller.h | 43
include/hw/ppc/pnv_xscom.h | 3 +
hw/ppc/pnv_spi_controller.c
control registers are implemented.
This commit also implement the read/write method for the powerbus scom
registers
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_n1_chiplet.h | 32 ++
include/hw/ppc/pnv_xscom.h | 6 ++
hw/ppc/pnv_n1_chiplet.c | 173
This part of the patchset connects the nest1 chiplet model to p10 chip.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_chip.h | 2 ++
hw/ppc/pnv.c | 15 +++
2 files changed, 17 insertions(+)
diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
index
gisters.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_nest_pervasive.h | 32 +
include/hw/ppc/pnv_xscom.h | 3 +
hw/ppc/pnv_nest_pervasive.c | 208
hw/ppc/meson.build | 1 +
4 files changed, 244 insertions(+)
create mode 1
covered:
Ran make check && make check-avocado and found no obvious issues.
Thank You,
Chalapathi
Chalapathi V (3):
hw/ppc: Add pnv nest pervasive common chiplet model
hw/ppc: Add N1 chiplet model
hw/ppc: N1 chiplet wiring
include/hw/ppc/pnv_chip.h | 2 +
includ
gisters.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_nest_pervasive.h | 32 +
include/hw/ppc/pnv_xscom.h | 3 +
hw/ppc/pnv_nest_pervasive.c | 208
hw/ppc/meson.build | 1 +
4 files changed, 244 insertions(+)
create mode 1
control registers are implemented.
This commit also implement the read/write method for the powerbus scom
registers
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_n1_chiplet.h | 32 ++
include/hw/ppc/pnv_xscom.h | 6 ++
hw/ppc/pnv_n1_chiplet.c | 173
This part of the patchset connects the nest1 chiplet model to p10 chip.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_chip.h | 2 ++
hw/ppc/pnv.c | 15 +++
2 files changed, 17 insertions(+)
diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
index
gisters.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_nest_pervasive.h | 32 +
include/hw/ppc/pnv_xscom.h | 3 +
hw/ppc/pnv_nest_pervasive.c | 208
hw/ppc/meson.build | 1 +
4 files changed, 244 insertions(+)
create mode 1
This part of the patchset connects the nest1 chiplet model to p10 chip.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_chip.h | 2 ++
hw/ppc/pnv.c | 15 +++
2 files changed, 17 insertions(+)
diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
index
control registers are implemented.
This commit also implement the read/write method for the powerbus scom
registers
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_n1_chiplet.h | 33 ++
include/hw/ppc/pnv_xscom.h | 6 ++
hw/ppc/pnv_n1_chiplet.c | 173
make check-avocado and found no obvious issues.
Thank You,
Chalapathi
Chalapathi V (3):
hw/ppc: Add pnv nest pervasive common chiplet model
hw/ppc: Add N1 chiplet model
hw/ppc: N1 chiplet wiring
include/hw/ppc/pnv_chip.h | 2 +
include/hw/ppc/pnv_n1_chiplet.h | 33 +++
On 28-11-2023 12:18, Cédric Le Goater wrote:
On 11/27/23 18:13, Chalapathi V wrote:
The N1 chiplet handle the high speed i/o traffic over PCIe and others.
The N1 chiplet consists of PowerBus Fabric controller,
nest Memory Management Unit, chiplet control unit and more.
This commit creates
gisters.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_nest_pervasive.h | 36 +
include/hw/ppc/pnv_xscom.h | 3 +
hw/ppc/pnv_nest_pervasive.c | 219
hw/ppc/meson.build | 1 +
4 files changed, 259 insertions(+)
create mode 1
control registers are implemented.
This commit also implement the read/write method for the powerbus scom
registers
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_n1_chiplet.h | 35 +++
include/hw/ppc/pnv_xscom.h | 6 ++
hw/ppc/pnv_n1_chiplet.c | 171
This part of the patchset connects the nest1 chiplet model to p10 chip.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_chip.h | 2 ++
hw/ppc/pnv.c | 15 +++
2 files changed, 17 insertions(+)
diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
index
chiplet control scoms for N1 chiplet.
PATCH3: Connect N1 chiplet model to p10 chip.
Test covered:
These changes are tested on a single socket and 2 socket P10 machine.
Thank You,
Chalapathi
Chalapathi V (3):
hw/ppc: Add pnv nest pervasive common chiplet model
hw/ppc: Add N1 chiplet model
at 8:15 PM AEST, Chalapathi V wrote:
The nest1 chiplet handle the high speed i/o traffic over PCIe and others.
The nest1 chiplet consists of PowerBus Fabric controller,
nest Memory Management Unit, chiplet control unit and more.
This commit creates a nest1 chiplet model and initialize and realize
On 24-11-2023 16:42, Nicholas Piggin wrote:
On Fri Nov 24, 2023 at 8:15 PM AEST, Chalapathi V wrote:
This part of the patchset creates a common pervasive chiplet model where it
houses the common units of a chiplets.
The chiplet control unit is common across chiplets and this commit
chiplet control registers are implemented.
This commit also implement the read/write method for the powerbus scom
registers
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_nest_chiplet.h | 36 ++
include/hw/ppc/pnv_xscom.h| 6 +
hw/ppc/pnv_nest1_chiplet.c| 197
.
Thank You,
Chalapathi
Chalapathi V (3):
hw/ppc: Add pnv pervasive common chiplet units
hw/ppc: Add nest1 chiplet model
hw/ppc: Nest1 chiplet wiring
include/hw/ppc/pnv_chip.h | 2 +
include/hw/ppc/pnv_nest_chiplet.h | 36 +
include/hw/ppc/pnv_pervasive.h| 37
This part of the patchset creates a common pervasive chiplet model where it
houses the common units of a chiplets.
The chiplet control unit is common across chiplets and this commit implements
the pervasive chiplet model with chiplet control registers.
Signed-off-by: Chalapathi V
---
include
This part of the patchset connects the nest1 chiplet model to p10 chip.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_chip.h | 2 ++
hw/ppc/pnv.c | 14 ++
2 files changed, 16 insertions(+)
diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
index
From: Chalapathi V
This part of the patchset connects the nest1 chiplet model to p10 chip.
Signed-off-by: Chalapathi V
---
hw/ppc/pnv.c | 14 ++
include/hw/ppc/pnv_chip.h | 2 ++
2 files changed, 16 insertions(+)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index
From: Chalapathi V
This part of the patchset creates a common pervasive chiplet model where it
houses the common units of a chiplets.
The chiplet control unit is common across chiplets and this commit implements
the pervasive chiplet model with chiplet control registers.
Signed-off
From: Chalapathi V
The nest1 chiplet handle the high speed i/o traffic over PCIe and others.
The nest1 chiplet consists of PowerBus Fabric controller,
nest Memory Management Unit, chiplet control unit and more.
This commit creates a nest1 chiplet model and initialize and realize the
pervasive
From: Chalapathi V
Hello,
For modularity reasons the P10 processor chip is split into multiple
chiplets individually controlled and managed by the pervasive logic.
The boundaries of these chiplets are defined based on physical design
parameters like clock grids, the nature of the functional
chiplet control registers are implemented.
Signed-off-by: Chalapathi V
---
hw/ppc/meson.build| 1 +
hw/ppc/pnv_nest1_chiplet.c| 104 ++
include/hw/ppc/pnv_nest_chiplet.h | 39 +++
3 files changed, 144 insertions(+)
create mode 100644
for pervasive chiplet and initialize and realize in nest1 chiplet model.
/nest1_chiplet (pnv-nest1-chiplet)
/perv_chiplet (pnv-pervasive-chiplet)
/xscom-chiplet-control-regs[0] (memory-region)
Chalapathi V (3):
hw/ppc: Add pnv pervasive common chiplet units
hw/ppc: Add nest1
This part of the patchset creates a common pervasive chiplet model where it
houses the common units of a chiplets.
The chiplet control unit is common across chiplets and this commit implements
the pervasive chiplet model with chiplet control registers.
Signed-off-by: Chalapathi V
---
hw/ppc
This part of the patchset connects the nest1 chiplet model to p10 chip.
Signed-off-by: Chalapathi V
---
hw/ppc/pnv.c | 11 +++
include/hw/ppc/pnv_chip.h | 2 ++
2 files changed, 13 insertions(+)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index eb54f93986..a5abaf5608 100644
individually.
In this series, we create a nest1 chiplet model and implements the chiplet
control scom registers on nest1 chiplet. The chiplet control registers does
the initialization and configuration of a chiplet.
Thank You,
Chalapathi
Chalapathi V (3):
hw/ppc: Add pnv pervasive common
The nest1 chiplet handle the high speed i/o traffic over PCIe and others.
The nest1 chiplet consists of PowerBus Fabric controller,
nest Memory Management Unit, chiplet control unit and more.
This commit implements nest1 chiplet control registers.
Signed-off-by: Chalapathi V
---
hw/ppc
This part of the patchset connects the nest1 chiplet model to p10 chip.
Signed-off-by: Chalapathi V
---
hw/ppc/pnv.c | 11 +++
include/hw/ppc/pnv_chip.h | 2 ++
2 files changed, 13 insertions(+)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index eb54f93986..0e1c944753 100644
This part of the patchset creates a common pervasive chiplet model where it
houses the common units of a chiplets.
The chiplet control unit is common across chiplets and this commit implements
the chiplet control registers.
Signed-off-by: Chalapathi V
---
hw/ppc/meson.build | 1
-Create nest1 chiplet model and add nest1 chiplet control scoms.
-Implementation of chiplet control scoms are put in pnv_pervasive.c
as control scoms are common for all chiplets.
Signed-off-by: Chalapathi V
---
hw/ppc/meson.build| 2 +
hw/ppc/pnv.c | 11
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