On 8/9/23 19:35, Richard Henderson wrote:
+static const ARMCPRegInfo cortex_a710_cp_reginfo[] = {
+/* TODO: trapped by HCR_EL2.TIDCP */
+{ .name = "CPUACTLR4_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 3,
+ .access = PL1_RW, .type =
On Thu, Aug 10, 2023 at 4:21 AM Yuri Benditovich
wrote:
>
> ping
I've queued this.
Thanks
>
> On Tue, Aug 1, 2023 at 1:32 AM Yuri Benditovich
> wrote:
>>
>> Starting from 6.2 the kernel supports UDP segmentation offload, it
>> uses GSO_UDP_L4 to mark packets with UDP sermentation request
>>
On 8/9/23 19:38, gaosong wrote:
And, I will send a patch to Check CPUCFG.2.LSX, Thanks for you suggestion.
There are similar missing checks for CPUCFG.2 FP, FP_SP, FP_DP, LSPW and LAM.
Also note that loongarch_la464_initfn misses setting LSPW.
r~
在 2023/8/9 下午11:03, Richard Henderson 写道:
On 8/9/23 01:26, Jiajie Chen wrote:
LoongArch64-only instructions are marked with regard to the instruction
manual Table 2. LSX instructions are not marked for now for lack of
public manual.
I would expect LSX not to be affected by CPUCFG.1.ARCH, but
The cortex-a710 is a first generation ARMv9.0-A processor.
Signed-off-by: Richard Henderson
---
docs/system/arm/virt.rst | 1 +
hw/arm/virt.c| 1 +
target/arm/tcg/cpu64.c | 167 +++
3 files changed, 169 insertions(+)
diff --git
Support all of the easy GM block sizes.
Use direct memory operations, since the pointers are aligned.
While BS=2 (16 bytes, 1 tag) is a legal setting, that requires
an atomic store of one nibble. This is not difficult, but there
is also no point in supporting it until required.
Note that
Previously we hard-coded the blocksize with GMID_EL1_BS.
But the value we choose for -cpu max does not match the
value that cortex-a710 uses.
Mirror the way we handle dcz_blocksize.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 2 ++
target/arm/internals.h | 6
This is one of the first generation Armv9 cores, and gives us something
concrete to test in that area. Notably, it supports MTE.
The first patch is a bug fix of sorts for neoverse-v1, as we don't,
and won't, support FEAT_TRF.
The only thing missing for the a710 is FEAT_MPAM. I haven't looked
Self-hosted trace is out of scope for QEMU.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Richard Henderson
---
target/arm/tcg/cpu64.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 8019f00bc3..60e5f034d9 100644
---
This value is only 4 bits wide.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 88e5accda6..7fedbb34ba 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1074,7 +1074,8 @@
On Wed Aug 9, 2023 at 8:07 PM AEST, Maksim Kostin wrote:
> ppce500_reset_device_tree is registered for system reset, but after
> c4b075318eb1 this function rerandomizes rng-seed via
> qemu_guest_getrandom_nofail. And when loading a snapshot, it tries to read
> EVENT_RANDOM that doesn't exist, so
On 8/9/23 16:07, Helge Deller wrote:
+/* did qemu source code crashed? */
+if (unlikely(!h2g_valid(host_addr))) {
+qemu_show_backtrace(info);
+}
This won't do anything at all when reserved_va == 0,
i.e. 64-bit guest on 64-bit host, or any
/stffrdhrn/qemu.git tags/or1k-pull-request-20230809
for you to fetch changes up to 765fdc1e8355d4bae563b3b185c5f9d079384164:
target/openrisc: Set EPCR to next PC on FPE exceptions (2023-07-31 22:01:03
+0100)
OpenRISC FPU Fix
On Wed Aug 9, 2023 at 10:56 PM AEST, Cédric Le Goater wrote:
> Hello Nick,
>
> On 8/8/23 06:19, Nicholas Piggin wrote:
> > TCG does not maintain the DEC reigster in the SPR array, so it does get
> > migrated. TCG also needs to re-start the decrementer timer on the
> > destination machine.
> >
> >
On Tue, Aug 8, 2023 at 10:18 PM Akihiko Odaki
wrote:
> On 2023/08/09 11:11, Gurchetan Singh wrote:
> > This adds basic documentation for virtio-gpu.
> >
> > Suggested-by: Akihiko Odaki
> > Signed-off-by: Gurchetan Singh
> > ---
> > v2: - Incorporated suggestions by Akihiko Odaki
> > -
On Wed, Aug 9, 2023 at 5:29 AM Paolo Bonzini wrote:
>
> This series introduce a new installation command for mkvenv.py that
> retrieves the packages to be installed from a TOML file. This allows
> being more flexible in using the system version of a package, while at
> the same time using a
If there is an internal program error in qemu source code
which triggers a SIGSEGV, qemu will currently assume this
is a SIGSEGV of the target and print:
(hppa-chroot)root@p100:/# cat /proc/self/maps
**
ERROR:../../home/cvs/qemu/qemu/accel/tcg/cpu-exec.c:532:cpu_exec_longjmp_cleanup:
assertion
Drew,
On 8/3/23 09:05, Andrew Jones wrote:
On Thu, Aug 03, 2023 at 08:36:57AM -0300, Daniel Henrique Barboza wrote:
On 8/3/23 06:29, Andrew Jones wrote:
On Wed, Aug 02, 2023 at 03:00:58PM -0300, Daniel Henrique Barboza wrote:
cpu->cfg.mvendorid is a 32 bit field and kvm_set_one_reg()
/rth7680/qemu.git tags/pull-lu-20230809
for you to fetch changes up to b8002058c45a50d893c51cf62ec96c70128fc1eb:
linux-user: Fix openat() emulation to correctly detect accesses to /proc
(2023-08-09 09:31:30 -0700)
linux-user: Fixes
On 8/9/23 06:39, Klaus Jensen wrote:
From: Klaus Jensen
Hi,
The following changes since commit a8fc5165aab02f328ccd148aafec1e59fd1426eb:
Merge tag 'nvme-next-pull-request' ofhttps://gitlab.com/birkelund/qemu into
staging (2023-08-08 16:39:20 -0700)
are available in the Git repository
On Wed, Aug 09, 2023 at 10:22:50AM +, Jason Chien wrote:
> In pcie_bus_realize(), a root bus is realized as a PCIe bus and a non-root
> bus is realized as a PCIe bus if its parent bus is a PCIe bus. However,
> the child bus "dw-pcie" is realized before the parent bus "pcie" which is
> the root
-20230809
for you to fetch changes up to 765fdc1e8355d4bae563b3b185c5f9d079384164:
target/openrisc: Set EPCR to next PC on FPE exceptions (2023-07-31 22:01:03
+0100)
OpenRISC FPU Fix for 8.1
A patch to pass the correct exception
The architecture specification calls for the EPCR to be set to "Address
of next not executed instruction" when there is a floating point
exception (FPE). This was not being done, so fix it by using the same
pattern as syscall. Also, we move this logic down to be done for
instructions not in the
ping
On Tue, Aug 1, 2023 at 1:32 AM Yuri Benditovich
wrote:
> Starting from 6.2 the kernel supports UDP segmentation offload, it
> uses GSO_UDP_L4 to mark packets with UDP sermentation request
>
> v1->v2:
> Enable USO features by default starting from 8.1
> Move command-line parameters to the
In order for our emulation of MAP_FIXED_NOREPLACE to succeed within
linux-user target_mmap, we require a non-zero value. This does not
require host kernel support, merely the bit being defined.
MAP_FIXED_NOREPLACE was added with glibc 2.28. From repology.org:
Fedora 36: 2.35
This test fails when host page size != guest page size,
because qemu may not be able to directly map the file.
Fixes: a6341482695 ("tests/tcg: Add a test for info proc mappings")
Acked-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
tests/tcg/multiarch/gdbstub/test-proc-mappings.py |
New function that rejects unsupported map types and flags.
In 4b840f96 we should not have accepted MAP_SHARED_VALIDATE
without actually validating the rest of the flags.
Fixes: 4b840f96 ("linux-user: Populate more bits in mmap_flags_tbl")
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
The following changes since commit 32e07fddc6d989dc5fdff4f9c9e47cb1f3911904:
Merge tag 'pull-lu-20230808' of https://gitlab.com/rth7680/qemu into staging
(2023-08-08 14:10:07 -0700)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-lu-20230809
for you
From: Helge Deller
Fix a crash in qemu-user when running
cat /proc/self/maps
in a chroot, where /proc isn't mounted.
The problem was introduced by commit 3ce3dd8ca965 ("util/selfmap:
Rewrite using qemu/interval-tree.h") where in open_self_maps_1() the
function read_self_maps() is called
From: Helge Deller
In qemu we catch accesses to files like /proc/cpuinfo or /proc/net/route
and return to the guest contents which would be visible on a real system
(instead what the host would show).
This patch fixes a bug, where for example the accesses
cat /proccpuinfo
or
cd
Rather than using a zero tuple to end the table, use a macro
to apply ARRAY_SIZE and pass that on to the convert functions.
This fixes two bugs in which the conversion functions required
that both the target and host masks be non-zero in order to
continue, rather than require both target and host
Yeqi Fu writes:
> Introduce a new test for native calls to ensure their functionality.
> The process involves cross-compiling the test cases, building them
> as dynamically linked binaries, and running these binaries which
> necessitates the addition of the appropriate interpreter prefix.
>
>
Yeqi Fu writes:
> Introduce a new test for native calls to ensure their functionality.
> The process involves cross-compiling the test cases, building them
> as dynamically linked binaries, and running these binaries which
> necessitates the addition of the appropriate interpreter prefix.
>
>
Richard Henderson writes:
> On 8/8/23 07:17, Yeqi Fu wrote:
>> This commit addresses the need to parse symbols of native libraries.
>> The base address of a shared library is determined by the dynamic
>> linker. To simplify the process, we focus on the last three digits,
>> which reside within
On Wed, 9 Aug 2023 14:07:07 +0200
Laszlo Ersek wrote:
> On 8/8/23 17:40, Alex Williamson wrote:
> > On Tue, 8 Aug 2023 16:59:16 +0200
> > Laszlo Ersek wrote:
> >
> >> The Solarflare Communications SFC9220 NIC's physical function (PF) appears
> >> to expose an expansion ROM with the
Yeqi Fu writes:
> This commit implements tcg opcodes and helpers for extracting and
> invoke native functions.
>
> Signed-off-by: Yeqi Fu
> ---
> accel/tcg/tcg-runtime.h | 22 ++
> include/tcg/tcg-op-common.h | 11 +++
> include/tcg/tcg.h | 9 +++
> tcg/tcg-op.c
On Wed, Aug 9, 2023 at 8:11 AM Jonathan Cameron
wrote:
>
> On Tue, 8 Aug 2023 11:51:21 -0400
> Alistair Francis wrote:
>
> > The Security Protocol and Data Model (SPDM) Specification defines
> > messages, data objects, and sequences for performing message exchanges
> > over a variety of
On Wed, Aug 09, 2023 at 04:33:37PM +0200, Paolo Bonzini wrote:
> On Wed, Aug 9, 2023 at 3:53 PM Bastian Koppelmann
> wrote:
> > > diff --git a/tests/docker/dockerfiles/debian-tricore-cross.docker
> > > b/tests/docker/dockerfiles/debian-tricore-cross.docker
> > > index 269bfa8d423..5bd1963fb55
On 8/8/23 07:17, Yeqi Fu wrote:
This commit introduces support for native library calls on the
i386 target. When special instructions reserved for native calls
are encountered, the code now performs address translation and
generates the corresponding native call.
Signed-off-by: Yeqi Fu
---
On 8/9/23 08:53, Helge Deller wrote:
On 8/9/23 17:23, Richard Henderson wrote:
On 8/9/23 08:11, Helge Deller wrote:
Fix a crash in qemu-user when running
cat /proc/self/maps
in a chroot, where /proc isn't mounted.
The problem was introduced by commit 3ce3dd8ca965 ("util/selfmap:
On 8/8/23 07:17, Yeqi Fu wrote:
This commit addresses the need to parse symbols of native libraries.
The base address of a shared library is determined by the dynamic
linker. To simplify the process, we focus on the last three digits,
which reside within the same page and remain unaffected by
On 8/8/23 07:17, Yeqi Fu wrote:
+#if defined(i386) || defined(x86_64)
+/*
+ * An unused instruction is utilized to mark a native call.
+ */
+#define __CALL_EXPR ".byte 0x0f, 0xff;"
+#endif
This is 2 of the 3 (or more) bytes of the UD0 instruction.
At minimum you should include a third byte for
On 8/8/23 07:17, Yeqi Fu wrote:
+char *new_env_value = NULL;
+size_t new_env_len = strlen(entry->ev_var) + strlen(eq_sign)
++ strlen(separator) + 1;
+new_env_value = g_malloc(new_env_len);
+strcpy(new_env_value, entry->ev_var);
+
On 8/9/23 17:23, Richard Henderson wrote:
On 8/9/23 08:11, Helge Deller wrote:
Fix a crash in qemu-user when running
cat /proc/self/maps
in a chroot, where /proc isn't mounted.
The problem was introduced by commit 3ce3dd8ca965 ("util/selfmap:
Rewrite using qemu/interval-tree.h") where
Yeqi Fu writes:
> This commit implements the -native-bypass support in linux-user. The
> native_calls_enabled() function can be true only when the
> '-native-bypass' option is given.
>
> Signed-off-by: Yeqi Fu
> ---
> include/native/native.h | 9 +
> linux-user/main.c | 38
Yeqi Fu writes:
> Signed-off-by: Yeqi Fu
> ---
> include/qemu/envlist.h| 13 ++
> tests/unit/meson.build| 1 +
> tests/unit/test-envlist.c | 94 +++
> util/envlist.c| 71 -
> 4 files changed, 169
On 8/8/23 07:17, Yeqi Fu wrote:
Signed-off-by: Yeqi Fu
---
include/qemu/envlist.h| 13 ++
tests/unit/meson.build| 1 +
tests/unit/test-envlist.c | 94 +++
util/envlist.c| 71 -
4 files changed, 169
On 8/8/23 07:17, Yeqi Fu wrote:
+#define native_bypass_enabled() native_lib_path ? true : false
Need parenthesis for the expression, and possibly better as
(native_lib_path != NULL)
rather than ternary expression.
+#if defined(CONFIG_NATIVE_CALL)
+/* Set the library for native
From: Hyman Huang(黄勇)
The dirty limit feature has been introduced since the 8.1
QEMU release but has not reflected in the document, add a
section for that.
Signed-off-by: Hyman Huang(黄勇)
---
docs/devel/migration.rst | 70
1 file changed, 70
On Wed, Aug 09, 2023 at 06:02:52PM +0300, gudkov.and...@huawei.com wrote:
> > Not for the patch, I'm just curious about how the predication
> > decides the network throughput, I mean QEMU predicts
> > if migration will converge based on how fast it sends the data,
> > not the actual bandwidth of
Alex Bennée writes:
> Yeqi Fu writes:
>
>> Signed-off-by: Yeqi Fu
>> ---
>> configure | 57 +--
>> 1 file changed, 34 insertions(+), 23 deletions(-)
>>
>> diff --git a/configure b/configure
>> index 2b41c49c0d..a076583141 100755
>> ---
On 2023-07-31 at 12:21:57 -0400, Xiaoyao Li wrote:
> From: Chao Peng
>
> Currently only KVM_MEMORY_EXIT_FLAG_PRIVATE in flags is valid when
> KVM_EXIT_MEMORY_FAULT happens. It indicates userspace needs to do
> the memory conversion on the RAMBlock to turn the memory into desired
> attribute,
On 8/9/23 08:11, Helge Deller wrote:
Fix a crash in qemu-user when running
cat /proc/self/maps
in a chroot, where /proc isn't mounted.
The problem was introduced by commit 3ce3dd8ca965 ("util/selfmap:
Rewrite using qemu/interval-tree.h") where in open_self_maps_1() the
function
Yeqi Fu writes:
> This commit implements a shared library, where native functions are
> rewritten as special instructions. At runtime, user programs load
> the shared library, and special instructions are executed when
> native functions are called.
>
> Signed-off-by: Yeqi Fu
> ---
>
On Wed, Aug 09, 2023 at 11:20:11AM +0200, David Hildenbrand wrote:
> Hi Peter!
Hi, David,
>
> > > -fd = file_ram_open(mem_path, memory_region_name(mr), readonly,
> > > ,
> > > - errp);
> > > +fd = file_ram_open(mem_path, memory_region_name(mr), readonly,
> > > );
On 8/9/23 01:26, Jiajie Chen wrote:
Add la132 as a loongarch32 cpu type and allow virt machine to be used
with la132 instead of la464.
Due to lack of public documentation of la132, it is currently a
synthetic loongarch32 cpu model. Details need to be added in the future.
Signed-off-by: Jiajie
Fix a crash in qemu-user when running
cat /proc/self/maps
in a chroot, where /proc isn't mounted.
The problem was introduced by commit 3ce3dd8ca965 ("util/selfmap:
Rewrite using qemu/interval-tree.h") where in open_self_maps_1() the
function read_self_maps() is called and which returns NULL
On 8/9/23 01:26, Jiajie Chen wrote:
In VA32 mode, BL, JIRL and PC* instructions should sign-extend the low
32 bit result to 64 bits.
Signed-off-by: Jiajie Chen
---
target/loongarch/insn_trans/trans_arith.c.inc | 2 +-
target/loongarch/insn_trans/trans_branch.c.inc | 4 ++--
On 8/9/23 01:26, Jiajie Chen wrote:
When running in VA32 mode(!LA64 or VA32L[1-3] matching PLV), virtual
address is truncated to 32 bits before address mapping.
Signed-off-by: Jiajie Chen
Co-authored-by: Richard Henderson
---
target/loongarch/cpu.c| 16
On Sun, Aug 06, 2023 at 02:16:34PM +0800, Yong Huang wrote:
> On Fri, Aug 4, 2023 at 11:03 PM Andrei Gudkov
> wrote:
>
> > Introduces alternative argument calc-time-ms, which is the
> > the same as calc-time but accepts millisecond value.
> > Millisecond granularity allows to make predictions
On 8/9/23 01:26, Jiajie Chen wrote:
LoongArch64-only instructions are marked with regard to the instruction
manual Table 2. LSX instructions are not marked for now for lack of
public manual.
I would expect LSX not to be affected by CPUCFG.1.ARCH, but only by
CPUCFG.2.LSX.
Note that there
Hello Joel,
So we're re-using the same xscom ops as on P8. A quick look at the
definition of those 4 registers on P8 (0xb0020) and on P9/P10
(0x00090040) seem to show they are not the same though. Am i missing
something?
Fred
On 08/08/2023 10:34, Joel Stanley wrote:
From P9 on the LPC
Yeqi Fu writes:
> Signed-off-by: Yeqi Fu
> ---
> configure | 57 +--
> 1 file changed, 34 insertions(+), 23 deletions(-)
>
> diff --git a/configure b/configure
> index 2b41c49c0d..a076583141 100755
> --- a/configure
> +++ b/configure
> @@
On 8/9/23 01:26, Jiajie Chen wrote:
Add object class for future loongarch32 cpus. It is derived from the
loongarch64 object class.
Signed-off-by: Jiajie Chen
---
target/loongarch/cpu.c | 19 +++
target/loongarch/cpu.h | 1 +
2 files changed, 20 insertions(+)
Reviewed-by:
On 8/9/23 06:17, Mikhail Tyutin wrote:
Would not be better to get back to initial v1 approach when we clean
TLB_INVALID_MASK flag in
tlb_plugin_lookup()? It works well for those regions.
You're just as likely to get invalid data.
r~
On Wed, Aug 9, 2023 at 3:53 PM Bastian Koppelmann
wrote:
> > diff --git a/tests/docker/dockerfiles/debian-tricore-cross.docker
> > b/tests/docker/dockerfiles/debian-tricore-cross.docker
> > index 269bfa8d423..5bd1963fb55 100644
> > --- a/tests/docker/dockerfiles/debian-tricore-cross.docker
> >
On Sun, Aug 06, 2023 at 02:31:43PM +0800, Yong Huang wrote:
> On Sat, Aug 5, 2023 at 2:05 AM Markus Armbruster wrote:
>
> > Andrei Gudkov writes:
> >
> > > Introduces alternative argument calc-time-ms, which is the
> > > the same as calc-time but accepts millisecond value.
> > > Millisecond
On Wed, Aug 09, 2023 at 10:29:45AM +0200, Paolo Bonzini wrote:
> With the release of version 12 on June 10, 2023, Debian 10 is
> not supported anymore. Modify the cross compiler container to
> build on a newer version.
>
> Signed-off-by: Paolo Bonzini
> ---
>
On Wed, Aug 09, 2023 at 03:49:01PM +0200, Bastian Koppelmann wrote:
> On Wed, Aug 09, 2023 at 10:29:44AM +0200, Paolo Bonzini wrote:
> > The tricore tools are not detected when they are installed in
> > the host system, only if they are taken from an external
> > container. For this reason the
On Wed, Aug 09, 2023 at 10:29:44AM +0200, Paolo Bonzini wrote:
> The tricore tools are not detected when they are installed in
> the host system, only if they are taken from an external
> container. For this reason the build-tricore-softmmu job
> was not running the TCG tests.
>
> In addition
On Wed, 9 Aug 2023 21:20:48 +0800
"Wen, Qian" wrote:
> On 8/9/2023 7:14 PM, Igor Mammedov wrote:
> > On Wed, 9 Aug 2023 18:27:32 +0800
> > Qian Wen wrote:
> >
> >> The legacy topology enumerated by CPUID.1.EBX[23:16] is defined in SDM
> >> Vol2:
> >>
> >> Bits 23-16: Maximum number of
From: Klaus Jensen
nvme_directive_receive() does not check if an endurance group has been
configured (set) prior to testing if flexible data placement is enabled
or not.
Fix this.
Cc: qemu-sta...@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1815
Fixes: 73064edfb864
From: Klaus Jensen
The Reclaim Unit Update operation in I/O Management Receive does not
verify the presence of a configured endurance group prior to accessing
it.
Fix this.
Cc: qemu-sta...@nongnu.org
Fixes: 73064edfb864 ("hw/nvme: flexible data placement emulation")
Reviewed-by: Jesper Wendel
On Mon, 7 Aug 2023 22:31:35 +0800
Zhao Liu wrote:
> Hi Igor,
>
> On Mon, Aug 07, 2023 at 12:11:29PM +0200, Igor Mammedov wrote:
> > Date: Mon, 7 Aug 2023 12:11:29 +0200
> > From: Igor Mammedov
> > Subject: Re: [PATCH v2 2/3] hw/smbios: Fix thread count in type4
> > X-Mailer: Claws Mail 4.1.1
From: Klaus Jensen
Hi,
The following changes since commit a8fc5165aab02f328ccd148aafec1e59fd1426eb:
Merge tag 'nvme-next-pull-request' of https://gitlab.com/birkelund/qemu into
staging (2023-08-08 16:39:20 -0700)
are available in the Git repository at:
On 8/9/2023 7:14 PM, Igor Mammedov wrote:
> On Wed, 9 Aug 2023 18:27:32 +0800
> Qian Wen wrote:
>
>> The legacy topology enumerated by CPUID.1.EBX[23:16] is defined in SDM
>> Vol2:
>>
>> Bits 23-16: Maximum number of addressable IDs for logical processors in
>> this physical package.
>>
>> When
> On 8/2/23 06:08, Mikhail Tyutin wrote:
> > The fix is to clear TLB_INVALID_MASK bit in tlb_addr, as it happens in
> > other places e.g.
> > load_helper().
> >
> > Signed-off-by: Dmitriy Solovev
> > Signed-off-by: Mikhail Tyutin
> > ---
> > accel/tcg/cputlb.c | 2 +-
> > 1 file changed, 1
Hello Nick,
On 8/8/23 06:19, Nicholas Piggin wrote:
TCG does not maintain the DEC reigster in the SPR array, so it does get
migrated. TCG also needs to re-start the decrementer timer on the
destination machine.
Load and store the decrementer into the SPR when migrating. This works
for the
On Tue, 08 Aug 2023 16:17, Yeqi Fu wrote:
+arm and aarch64
+---
+HLT is an invalid instruction for userspace and usefully has 16
+bits of spare immeadiate data which we can stuff data in.
s/immeadiate/immediate
With that fix, you can add
Reviewed-by: Emmanouil Pitsidianakis
This patch needs a detailed commit message, since it's not obvious why
these changes are made at all. It'd also be helpful for reviewing.
General style comment for shell scripts: Always put curly braces around
variables even if they are unnecessary. a $source_path could become
The AT instruction is UNDEFINED if the {NSE,NS} configuration is
invalid. Add a function to check this on all AT instructions that apply
to an EL lower than 3.
Suggested-by: Peter Maydell
Signed-off-by: Jean-Philippe Brucker
---
target/arm/helper.c | 38 +++---
When HCR_EL2.E2H is enabled, TLB entries are formed using the EL2&0
translation regime, instead of the EL2 translation regime. The TLB VAE2*
instructions invalidate the regime that corresponds to the current value
of HCR_EL2.E2H.
At the moment we only invalidate the EL2 translation regime. This
A few patches to fix RME support and allow booting a realm guest, based
on "[PATCH v2 00/15] target/arm/ptw: Cleanups and a few bugfixes"
https://lore.kernel.org/all/20230807141514.19075-1-peter.mayd...@linaro.org/
Since v2:
* Updated the comment in patch 5. I also removed the check for
When FEAT_RME is implemented, these bits override the value of
CNT[VP]_CTL_EL0.IMASK in Realm and Root state. Move the IRQ state update
into a new gt_update_irq() function and test those bits every time we
recompute the IRQ state.
Since we're removing the IRQ state from some trace events, add a
GPC checks are not performed on the output address for AT instructions,
as stated by ARM DDI 0487J in D8.12.2:
When populating PAR_EL1 with the result of an address translation
instruction, granule protection checks are not performed on the final
output address of a successful translation.
At the moment we only handle Secure and Nonsecure security spaces for
the AT instructions. Add support for Realm and Root.
For AArch64, arm_security_space() gives the desired space. ARM DDI0487J
says (R_NYXTL):
If EL3 is implemented, then when an address translation instruction
that applies
In realm state, stage-2 translation tables are fetched from the realm
physical address space (R_PGRQD).
Signed-off-by: Jean-Philippe Brucker
Reviewed-by: Peter Maydell
---
target/arm/ptw.c | 26 ++
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git
On Tue, 8 Aug 2023 11:51:21 -0400
Alistair Francis wrote:
> The Security Protocol and Data Model (SPDM) Specification defines
> messages, data objects, and sequences for performing message exchanges
> over a variety of transport and physical media.
> -
>
On 8/8/23 17:40, Alex Williamson wrote:
> On Tue, 8 Aug 2023 16:59:16 +0200
> Laszlo Ersek wrote:
>
>> The Solarflare Communications SFC9220 NIC's physical function (PF) appears
>> to expose an expansion ROM with the following characteristics:
>>
>> (1) Single-image ROM, with only a legacy BIOS
On Tue Aug 8, 2023 at 1:02 PM AEST, Richard Henderson wrote:
> When a direct branch is out of range, we can load the destination for
> the indirect branch using PLA (for 16GB worth of buffer) and PLD from
> the TranslationBlock for everything larger.
>
> This means the patch affects exactly one
On Tue Aug 8, 2023 at 1:02 PM AEST, Richard Henderson wrote:
> With Power v3.1, we have pc-relative addressing and so
> do not require a register holding the current TB.
>
Acked-by: Nicholas Piggin
> Signed-off-by: Richard Henderson
> ---
> tcg/ppc/tcg-target.c.inc | 2 +-
> 1 file changed, 1
On Tue Aug 8, 2023 at 1:02 PM AEST, Richard Henderson wrote:
> The prefixed instruction has a pc-relative form to use here.
I don't understand this code very well but going by existing
relocs it looks okay.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: Richard Henderson
> ---
>
On Wed, 9 Aug 2023 18:27:32 +0800
Qian Wen wrote:
> The legacy topology enumerated by CPUID.1.EBX[23:16] is defined in SDM
> Vol2:
>
> Bits 23-16: Maximum number of addressable IDs for logical processors in
> this physical package.
>
> When launching the VM with -smp 256, the value written to
On Tue Aug 8, 2023 at 1:02 PM AEST, Richard Henderson wrote:
> When the offset is out of range of the non-prefixed insn, but
> fits the 34-bit immediate of the prefixed insn, use that.
>
The switch will fall through in some cases (at least opi == 0).
Should it have a default: break; to make that
On Tue, 2023-08-08 at 16:49 -0700, Richard Henderson wrote:
> This test fails when host page size != guest page size,
> because qemu may not be able to directly map the file.
>
> Fixes: a6341482695 ("tests/tcg: Add a test for info proc mappings")
> Signed-off-by: Richard Henderson
> ---
>
On Tue, Aug 08, 2023 at 05:16:12PM +0200, Klaus Jensen wrote:
> From: Klaus Jensen
>
> Fix two potential accesses to null pointers.
>
> Klaus Jensen (2):
> hw/nvme: fix null pointer access in directive receive
> hw/nvme: fix null pointer access in ruh update
>
> hw/nvme/ctrl.c | 10
In pcie_bus_realize(), a root bus is realized as a PCIe bus and a non-root
bus is realized as a PCIe bus if its parent bus is a PCIe bus. However,
the child bus "dw-pcie" is realized before the parent bus "pcie" which is
the root PCIe bus. Thus, the extended configuration space is not accessible
The legacy topology enumerated by CPUID.1.EBX[23:16] is defined in SDM
Vol2:
Bits 23-16: Maximum number of addressable IDs for logical processors in
this physical package.
When launching the VM with -smp 256, the value written to EBX[23:16] is
0 because of data overflow. If the guest only
ppce500_reset_device_tree is registered for system reset, but after
c4b075318eb1 this function rerandomizes rng-seed via
qemu_guest_getrandom_nofail. And when loading a snapshot, it tries to read
EVENT_RANDOM that doesn't exist, so we have an error:
qemu-system-ppc: Missing random event in the
Using the new ensuregroup command, the desired versions of meson and
sphinx can be placed in pythondeps.toml rather than configure.
The meson.install entry in pythondeps.toml matches the version that is
found in python/wheels. This ensures that mkvenv.py uses the bundled
wheel even if PyPI is
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