Module Name:src
Committed By: maya
Date: Wed Mar 7 20:48:00 UTC 2018
Modified Files:
src/sys/arch/mips/mips: locore.S
Log Message:
Remove now duplicate code for enabling FPU before reading FPU_ID
To generate a diff of this commit:
cvs rdiff -u -r1.216 -r1.217
Module Name:src
Committed By: maya
Date: Wed Mar 7 20:46:06 UTC 2018
Modified Files:
src/sys/arch/mips/mips: locore.S
Log Message:
Remove now duplicate code to read FPU_ID into t1
To generate a diff of this commit:
cvs rdiff -u -r1.215 -r1.216
Module Name:src
Committed By: maya
Date: Wed Mar 7 20:43:54 UTC 2018
Modified Files:
src/sys/arch/mips/mips: locore.S
Log Message:
Remove duplicate confused code for enabling 64bit addressing
To generate a diff of this commit:
cvs rdiff -u -r1.214 -r1.215
Module Name:src
Committed By: maya
Date: Wed Mar 7 15:56:34 UTC 2018
Modified Files:
src/sys/arch/mips/mips: locore.S
Log Message:
Add duplicate code to read the FPU ID.
enable & disable the FPU around it.
To generate a diff of this commit:
cvs rdiff -u -r1.213 -r1.214
Module Name:src
Committed By: maya
Date: Wed Mar 7 15:52:43 UTC 2018
Modified Files:
src/sys/arch/mips/mips: locore.S
Log Message:
Move the hpcmips L1 cache disable hack up
where another machine-specific hacks exists.
Note that no existing kernel seems to enable this
Module Name:src
Committed By: maya
Date: Wed Mar 7 15:49:45 UTC 2018
Modified Files:
src/sys/arch/mips/mips: locore.S
Log Message:
Add duplicate code that enables 64bit addressing under the right
macro conditions that is, _LP64.
The existing, previous code uses NOFPU as
Module Name:src
Committed By: maya
Date: Wed Mar 7 15:44:15 UTC 2018
Modified Files:
src/sys/arch/mips/mips: locore.S
Log Message:
Replace early interrupt disable code.
As suggested by dh, carefully disable interrupts before frobbing
interrupt mask, which might trigger
Module Name:src
Committed By: flxd
Date: Sat Mar 3 15:47:50 UTC 2018
Modified Files:
src/sys/arch/mips/mips: cache.c
Log Message:
Add missing call to mips_dcache_compute_align() affecting "modern" MIPS
(MIPS32{,R2}/MIPS64{,R2}). Thanks jmcneill@; OK skrll@.
To generate
Module Name:src
Committed By: bouyer
Date: Thu Feb 8 19:16:24 UTC 2018
Modified Files:
src/sys/arch/mips/include: locore.h
src/sys/arch/mips/mips: db_interface.c trap.c
Log Message:
Allow kdbpeek() to return failure. If it does, stop the stack trace.
Prevents an
Module Name:src
Committed By: mrg
Date: Tue Feb 6 09:33:45 UTC 2018
Modified Files:
src/sys/arch/mips/cavium/dev: octeon_pip.c
Log Message:
update for GCC 6:
hide octeon_pip_dump_regs_[] under OCTEON_ETH_DEBUG, the only user.
To generate a diff of this commit:
cvs
Module Name:src
Committed By: maya
Date: Fri Jan 26 05:29:43 UTC 2018
Modified Files:
src/sys/arch/mips/mips: locore_mips3.S
Log Message:
Don't warn about MIPS1 MULTIPROCESSOR in a mips3 file.
To generate a diff of this commit:
cvs rdiff -u -r1.113 -r1.114
Module Name:src
Committed By: maya
Date: Wed Jan 24 03:13:36 UTC 2018
Modified Files:
src/sys/arch/mips/mips: locore.S
Log Message:
Clarify this is a load delay nop.
To generate a diff of this commit:
cvs rdiff -u -r1.209 -r1.210 src/sys/arch/mips/mips/locore.S
Please
Module Name:src
Committed By: maya
Date: Wed Jan 24 03:11:30 UTC 2018
Modified Files:
src/sys/arch/mips/mips: locore.S
Log Message:
Add whitespace for clarity.
To generate a diff of this commit:
cvs rdiff -u -r1.208 -r1.209 src/sys/arch/mips/mips/locore.S
Please note
Module Name:src
Committed By: maya
Date: Tue Jan 23 06:57:49 UTC 2018
Modified Files:
src/sys/arch/mips/cavium: octeon_cpunode.c
Log Message:
if 0 out unused code which is currently breaking my local builds
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12
Module Name:src
Committed By: maya
Date: Mon Jan 22 23:20:26 UTC 2018
Modified Files:
src/sys/arch/mips/include: cpu.h
Log Message:
Don't attempt to dereference cpu_infos if ncpus == 0.
Instead use the already initialized cpu_info_store.
(Also, now we assume all ncpus
Module Name:src
Committed By: maya
Date: Mon Jan 22 21:56:47 UTC 2018
Modified Files:
src/sys/arch/mips/cavium: octeon_cpunode.c
Log Message:
Fix RCSID (hopefully)
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/mips/cavium/octeon_cpunode.c
Module Name:src
Committed By: flxd
Date: Mon Jan 22 18:15:57 UTC 2018
Modified Files:
src/sys/arch/mips/mips: bus_space_alignstride_chipdep.c
Log Message:
Use right variable as revealed by previous typo...
To generate a diff of this commit:
cvs rdiff -u -r1.30 -r1.31 \
Module Name:src
Committed By: flxd
Date: Sun Jan 21 16:38:25 UTC 2018
Modified Files:
src/sys/arch/mips/mips: bus_space_alignstride_chipdep.c
Log Message:
fix typo
To generate a diff of this commit:
cvs rdiff -u -r1.29 -r1.30 \
Module Name:src
Committed By: jmcneill
Date: Mon Jan 1 13:25:22 UTC 2018
Modified Files:
src/sys/arch/mips/cavium/dev: if_cnmac.c
Log Message:
Set and clear IFF_OACTIVE as necessary, and add support for queueing
multiple packets before performing a PKO doorbell write.
Module Name:src
Committed By: maya
Date: Fri Dec 29 09:27:01 UTC 2017
Modified Files:
src/sys/arch/mips/include: reg.h
src/sys/arch/mips/mips: process_machdep.c
Log Message:
Simplify, don't use ifdefs to optimize out DIAGNOSTIC assertions.
Make the test for the
Module Name:src
Committed By: maya
Date: Fri Dec 22 22:59:26 UTC 2017
Modified Files:
src/sys/arch/mips/mips: trap.c
Log Message:
Don't handle emulations overriding e_fault.
No existing emulations do this.
(COMPAT_IRIX did, but was removed)
To generate a diff of this
Module Name:src
Committed By: christos
Date: Sat Dec 9 03:22:33 UTC 2017
Modified Files:
src/sys/arch/mips/include: reg.h types.h
Log Message:
provide 32 and 64 bit register struct definitions.
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17
Module Name:src
Committed By: jmcneill
Date: Sun Nov 26 18:41:14 UTC 2017
Modified Files:
src/sys/arch/mips/cavium/dev: if_cnmac.c
Log Message:
Set ETHERCAP_VLAN_MTU capability flag.
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7
Module Name:src
Committed By: christos
Date: Mon Nov 6 19:17:43 UTC 2017
Modified Files:
src/sys/arch/mips/include: elf_machdep.h
Log Message:
Handle 64 bit kernels.
To generate a diff of this commit:
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/mips/include/elf_machdep.h
Module Name:src
Committed By: skrll
Date: Thu Sep 7 06:36:24 UTC 2017
Modified Files:
src/sys/arch/mips/include: vmparam.h
Log Message:
Don't define UVM_KM_VMFREELIST on mips as it excludes some memory
ranges unnecessarily.
PR/52501 - erlite quickly fails to allocate
Module Name:src
Committed By: mrg
Date: Thu Aug 24 23:45:08 UTC 2017
Modified Files:
src/sys/arch/mips/mips: bds_emul.S
Log Message:
mips_emul_daddi and mips_emul_daddiu don't exist, but there are
bcemul_daddi and bcemul_daddiu here that should be used. however,
Module Name:src
Committed By: maya
Date: Thu Aug 24 14:26:16 UTC 2017
Modified Files:
src/sys/arch/mips/mips: lock_stubs_llsc.S
Log Message:
Eliminate redundant load delays.
Machines that need load delays do not have ll/sc instructions.
To generate a diff of this
Module Name:src
Committed By: maya
Date: Tue Aug 22 07:09:00 UTC 2017
Modified Files:
src/sys/arch/mips/cavium/dev: if_cnmac.c
Log Message:
Reword warning message
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/mips/cavium/dev/if_cnmac.c
Please
Module Name:src
Committed By: maxv
Date: Sun Aug 20 11:06:36 UTC 2017
Modified Files:
src/sys/arch/mips/mips: cpu_subr.c
Log Message:
spl leak, found by mootja
To generate a diff of this commit:
cvs rdiff -u -r1.32 -r1.33 src/sys/arch/mips/mips/cpu_subr.c
Please note
Module Name:src
Committed By: maxv
Date: Sun Aug 20 11:05:24 UTC 2017
Modified Files:
src/sys/arch/mips/cavium/dev: octeon_gmx.c
Log Message:
as the xxx implicitly points out, there's a division by zero here, so
panic right away; found by mootja
To generate a diff of
Module Name:src
Committed By: maya
Date: Sun Aug 20 09:47:14 UTC 2017
Modified Files:
src/sys/arch/mips/mips: mipsX_subr.S
Log Message:
use meaningful name for errata hack, dedup
To generate a diff of this commit:
cvs rdiff -u -r1.103 -r1.104
Module Name:src
Committed By: maya
Date: Sun Aug 20 09:21:54 UTC 2017
Modified Files:
src/sys/arch/mips/mips: mipsX_subr.S
Log Message:
Don't need the errata workaround on user return
It's reported that the MMU will block such invalid reads in userland,
and it's only
Module Name:src
Committed By: maya
Date: Tue Aug 8 09:34:59 UTC 2017
Modified Files:
src/sys/arch/mips/mips: mipsX_subr.S
Log Message:
Remove whitespace I just introduced
To generate a diff of this commit:
cvs rdiff -u -r1.101 -r1.102
Module Name:src
Committed By: maya
Date: Tue Aug 8 09:33:41 UTC 2017
Modified Files:
src/sys/arch/mips/mips: mipsX_subr.S
Log Message:
In working around loongson errata clear BTB and RAS, same as
other operating systems.
15 Errata: Issue of Out-of-order in loongson
Module Name:src
Committed By: maxv
Date: Sun Jul 30 16:13:24 UTC 2017
Modified Files:
src/sys/arch/mips/include: svr4_machdep.h
src/sys/arch/mips/mips: svr4_machdep.c
Log Message:
Remove references to COMPAT_IRIX - does not exist anymore.
I believe svr4_machdep.h
Module Name:src
Committed By: christos
Date: Fri Jul 14 20:32:32 UTC 2017
Modified Files:
src/sys/arch/mips/mips: trap.c
Log Message:
Advance the PC on breakpoint instruction to avoid infinite loop DoS!
To generate a diff of this commit:
cvs rdiff -u -r1.243 -r1.244
Module Name:src
Committed By: christos
Date: Fri Jul 14 17:54:00 UTC 2017
Modified Files:
src/sys/arch/mips/mips: vm_machdep.c
Log Message:
KASSERT Fires for MIPS1, disable.
To generate a diff of this commit:
cvs rdiff -u -r1.158 -r1.159
Module Name:src
Committed By: skrll
Date: Sat Jun 24 07:00:37 UTC 2017
Modified Files:
src/sys/arch/mips/include: pte.h
Log Message:
Provide pte_set
To generate a diff of this commit:
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/mips/include/pte.h
Please note that diffs are
Module Name:src
Committed By: skrll
Date: Fri Jun 9 06:43:30 UTC 2017
Modified Files:
src/sys/arch/mips/mips: mips_machdep.c
Log Message:
Maintain the split of physical memory into the defined freelists, but
only force pool pages to VM_FREELIST_FIRST512M for non _LP64
Module Name:src
Committed By: skrll
Date: Fri Jun 9 06:39:24 UTC 2017
Modified Files:
src/sys/arch/mips/mips: pmap_machdep.c
Log Message:
Always use XKPHYS for pool pages on _LP64; otherwise use KSEG0
To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21
Module Name:src
Committed By: skrll
Date: Thu Jun 8 05:46:57 UTC 2017
Modified Files:
src/sys/arch/mips/mips: locore_mips1.S
Log Message:
Add a missing ".set at" to make previous build
To generate a diff of this commit:
cvs rdiff -u -r1.92 -r1.93
Module Name:src
Committed By: skrll
Date: Wed Jun 7 08:45:51 UTC 2017
Modified Files:
src/sys/arch/mips/mips: locore_mips1.S
Log Message:
fix tlb_record_asids 2nd arg to match usage - it's a maximum asid value
and not a mask
To generate a diff of this commit:
cvs rdiff
Module Name:src
Committed By: skrll
Date: Mon Jun 5 10:45:36 UTC 2017
Modified Files:
src/sys/arch/mips/mips: pmap_machdep.c
Log Message:
Fix the PMAP_NO_PV_UNCACHED pmap_md_vca_add case where the pmap_update
call would cause problems for pmap_remove_all case where the
Module Name:src
Committed By: skrll
Date: Fri May 19 07:43:31 UTC 2017
Modified Files:
src/sys/arch/mips/ingenic: apbus.c ingenic_com.c ingenic_dme.c
jzfb_regs.h jziic.c
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.18
Module Name:src
Committed By: skrll
Date: Thu May 18 13:20:37 UTC 2017
Modified Files:
src/sys/arch/mips/mips: pmap_machdep.c
Log Message:
Don't use index cache operations unnecessarily.
To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19
Module Name:src
Committed By: skrll
Date: Mon May 15 10:59:24 UTC 2017
Modified Files:
src/sys/arch/mips/mips: mipsX_subr.S
Log Message:
Fix off-by-one in tlb_record_asids
To generate a diff of this commit:
cvs rdiff -u -r1.99 -r1.100 src/sys/arch/mips/mips/mipsX_subr.S
Module Name:src
Committed By: skrll
Date: Sun May 14 15:36:46 UTC 2017
Modified Files:
src/sys/arch/mips/mips: pmap_machdep.c
Log Message:
Remove #if 0'ed old style cache handling in pmap_md_unmap_poolpage
To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18
Module Name:src
Committed By: skrll
Date: Sun May 14 11:46:22 UTC 2017
Modified Files:
src/sys/arch/mips/mips: pmap_machdep.c
Log Message:
Handle the maximum number of colors across [di]caches
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17
Module Name:src
Committed By: skrll
Date: Sun May 14 09:37:13 UTC 2017
Modified Files:
src/sys/arch/mips/mips: cache.c
Log Message:
Set mci_{,i}cache_alias_mask for all variants that can have virtual cache
aliases
Set ncolors appropriately
These align to dcache and
Module Name:src
Committed By: skrll
Date: Sun May 14 09:33:17 UTC 2017
Modified Files:
src/sys/arch/mips/mips: cache.c
Log Message:
Really fix typo that got dcache alias mask set from icache way_mask
To generate a diff of this commit:
cvs rdiff -u -r1.56 -r1.57
Module Name:src
Committed By: skrll
Date: Sun May 14 09:32:01 UTC 2017
Modified Files:
src/sys/arch/mips/mips: cache.c
Log Message:
Fix typo that got dcache alias mask set from icache way_mask
To generate a diff of this commit:
cvs rdiff -u -r1.55 -r1.56
Module Name:src
Committed By: skrll
Date: Fri May 12 06:49:31 UTC 2017
Modified Files:
src/sys/arch/mips/mips: pmap_machdep.c
Log Message:
Sprinkle some KASSERTs
To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/mips/mips/pmap_machdep.c
Please
Module Name:src
Committed By: skrll
Date: Fri May 12 06:43:42 UTC 2017
Modified Files:
src/sys/arch/mips/mips: pmap_machdep.c
Log Message:
Code style and add a comment
To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/mips/mips/pmap_machdep.c
Module Name:src
Committed By: skrll
Date: Fri May 12 06:38:18 UTC 2017
Modified Files:
src/sys/arch/mips/mips: pmap_machdep.c
Log Message:
Don't access pg before the KASSERT it's not NULL
To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14
Module Name:src
Committed By: skrll
Date: Thu May 11 09:09:54 UTC 2017
Modified Files:
src/sys/arch/mips/mips: vm_machdep.c
Log Message:
Fix non-DIAGNOSTIC build
To generate a diff of this commit:
cvs rdiff -u -r1.157 -r1.158 src/sys/arch/mips/mips/vm_machdep.c
Please
Module Name:src
Committed By: skrll
Date: Wed May 10 22:23:13 UTC 2017
Modified Files:
src/sys/arch/mips/mips: vm_machdep.c
Log Message:
Add a KASSERT
To generate a diff of this commit:
cvs rdiff -u -r1.156 -r1.157 src/sys/arch/mips/mips/vm_machdep.c
Please note that
Module Name:src
Committed By: skrll
Date: Wed May 10 22:19:31 UTC 2017
Modified Files:
src/sys/arch/mips/mips: vm_machdep.c
Log Message:
Make cpu_uarea_{alloc,free} conditional on PMAP_{,UN}MAP_POOLPAGE and
use PMAP_{,UN}_POOLPAGE to ensure cache aliases are handled
Module Name:src
Committed By: skrll
Date: Wed May 10 12:12:21 UTC 2017
Modified Files:
src/sys/arch/mips/mips: vm_machdep.c
Log Message:
Allow cpu_uarea_alloc to return NULL for non-system LWPs in the non-_LP64
case. That way TLB mapped KVA can be found by
Module Name:src
Committed By: skrll
Date: Wed May 10 11:27:14 UTC 2017
Modified Files:
src/sys/arch/mips/mips: vm_machdep.c
Log Message:
Improve comment wording.
To generate a diff of this commit:
cvs rdiff -u -r1.153 -r1.154 src/sys/arch/mips/mips/vm_machdep.c
Please
Module Name:src
Committed By: skrll
Date: Sun May 7 05:50:39 UTC 2017
Modified Files:
src/sys/arch/mips/mips: mipsX_subr.S
Log Message:
Check the TLB entry ASID against base (a0) and limit (a1), and not
limit (a1) and random register value (a2)
While here shave an
Module Name:src
Committed By: skrll
Date: Sun May 7 05:48:01 UTC 2017
Modified Files:
src/sys/arch/mips/mips: mipsX_subr.S
Log Message:
Save/restore pgMask in tlb_record_asids
To generate a diff of this commit:
cvs rdiff -u -r1.97 -r1.98
Module Name:src
Committed By: skrll
Date: Sun May 7 05:45:07 UTC 2017
Modified Files:
src/sys/arch/mips/mips: mips3_clock.c mips_dsp.c mips_fpu.c
mips_machdep.c
Log Message:
opt_multiprocessor.h police
To generate a diff of this commit:
cvs rdiff -u -r1.13
Module Name:src
Committed By: skrll
Date: Sun May 7 04:59:19 UTC 2017
Modified Files:
src/sys/arch/mips/mips: mipsX_subr.S
Log Message:
Call an ASID an ASID in comments
To generate a diff of this commit:
cvs rdiff -u -r1.96 -r1.97 src/sys/arch/mips/mips/mipsX_subr.S
Module Name:src
Committed By: skrll
Date: Sun May 7 04:14:20 UTC 2017
Modified Files:
src/sys/arch/mips/mips: cpu_subr.c pmap_machdep.c
Log Message:
KNF
To generate a diff of this commit:
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/mips/mips/cpu_subr.c
cvs rdiff -u -r1.12
Module Name:src
Committed By: skrll
Date: Sun May 7 04:12:35 UTC 2017
Modified Files:
src/sys/arch/mips/include: cpuregs.h
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.95 -r1.96 src/sys/arch/mips/include/cpuregs.h
Please note
Module Name:src
Committed By: skrll
Date: Thu Apr 27 20:05:09 UTC 2017
Modified Files:
src/sys/arch/mips/mips: cache_r5k.c
Log Message:
Typo in comment
To generate a diff of this commit:
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/mips/mips/cache_r5k.c
Please note that
Module Name:src
Committed By: skrll
Date: Thu Apr 27 19:40:55 UTC 2017
Modified Files:
src/sys/arch/mips/mips: cache_r4k_subr.S
Log Message:
Typo in comment
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/mips/mips/cache_r4k_subr.S
Please note
Module Name:src
Committed By: skrll
Date: Sat Apr 22 20:32:35 UTC 2017
Modified Files:
src/sys/arch/mips/mips: cache.c
Log Message:
Comment indentation
To generate a diff of this commit:
cvs rdiff -u -r1.54 -r1.55 src/sys/arch/mips/mips/cache.c
Please note that diffs
Module Name:src
Committed By: skrll
Date: Thu Mar 30 08:43:40 UTC 2017
Modified Files:
src/sys/arch/mips/cavium: octeon_intr.c
Log Message:
Indentation
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/mips/cavium/octeon_intr.c
Please note that
Module Name:src
Committed By: skrll
Date: Wed Mar 1 11:54:53 UTC 2017
Modified Files:
src/sys/arch/mips/mips: lock_stubs_ras.S
Log Message:
Can't profile ras_atomic_cas_noupdate
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9
Module Name:src
Committed By: chs
Date: Mon Feb 27 06:57:45 UTC 2017
Modified Files:
src/sys/arch/mips/mips: fp.S
Log Message:
in mips_emul_fp(), clear all pending FP exceptions rather than
just a particular one, otherwise the kernel can take another
FPU trap when it
Module Name:src
Committed By: chs
Date: Mon Feb 27 06:57:16 UTC 2017
Modified Files:
src/sys/arch/mips/include: fenv.h
Log Message:
fix fesetround() to set the FPSR to the desired value rather than
a pointer to a local variable. wrap the asm in inline functions so that
Module Name:src
Committed By: chs
Date: Mon Feb 27 06:56:03 UTC 2017
Modified Files:
src/sys/arch/mips/include: ieeefp.h
Log Message:
the FP_* rounding constants need to be different from the new FE_* constants
to preserve the ABI, so shift them as needed when using them.
Module Name:src
Committed By: chs
Date: Mon Feb 27 06:56:33 UTC 2017
Modified Files:
src/sys/arch/mips/mips: db_disasm.c
Log Message:
the second operand to cfc1/ctc1 isn't an FPU data register
so don't make it look like one.
To generate a diff of this commit:
cvs rdiff
Module Name:src
Committed By: christos
Date: Thu Feb 23 18:56:12 UTC 2017
Modified Files:
src/sys/arch/mips/include: ecoff_machdep.h
Log Message:
provide ecoff 32 defines.
To generate a diff of this commit:
cvs rdiff -u -r1.22 -r1.23
Module Name:src
Committed By: maya
Date: Wed Feb 22 13:34:39 UTC 2017
Modified Files:
src/sys/arch/mips/conf: Makefile.mips
Log Message:
leave the part for GCC >= 5.3 in.
Was a little over-eager and accidentally removed the else case.
To generate a diff of this commit:
Module Name:src
Committed By: maya
Date: Wed Feb 22 13:17:29 UTC 2017
Modified Files:
src/sys/arch/mips/conf: Makefile.mips
Log Message:
GC workaround for GCC 4.8 fixed in GCC 5+
To generate a diff of this commit:
cvs rdiff -u -r1.65 -r1.66
Module Name:src
Committed By: christos
Date: Fri Jan 27 17:22:16 UTC 2017
Modified Files:
src/sys/arch/mips/include: types.h
Log Message:
remove __HAVE_COMPAT_NETBSD32
To generate a diff of this commit:
cvs rdiff -u -r1.65 -r1.66 src/sys/arch/mips/include/types.h
Module Name:src
Committed By: christos
Date: Fri Jan 13 19:10:14 UTC 2017
Modified Files:
src/sys/arch/mips/include: fenv.h
Log Message:
making this use mips assembly is a good start!
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2
Module Name:src
Committed By: mrg
Date: Thu Dec 22 07:56:38 UTC 2016
Modified Files:
src/sys/arch/mips/mips: mips_machdep.c
Log Message:
fix lp64 kvm access for many kernel addresses.
in mm_md_kernacc() allow an address if it matches MIPS_KSEG0_P().
now a static n64
Module Name:src
Committed By: mrg
Date: Mon Nov 28 04:18:08 UTC 2016
Modified Files:
src/sys/arch/mips/cavium: octeon_intr.c
Log Message:
fix non-DIAG builds.
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/mips/cavium/octeon_intr.c
Please note
Module Name:src
Committed By: skrll
Date: Tue Nov 22 11:01:51 UTC 2016
Modified Files:
src/sys/arch/mips/include: vmparam.h
Log Message:
1TB is enough UVA for anyone... plus not all cpus can support more.
To generate a diff of this commit:
cvs rdiff -u -r1.56 -r1.57
Module Name:src
Committed By: skrll
Date: Sat Nov 19 09:05:50 UTC 2016
Modified Files:
src/sys/arch/mips/mips: mipsX_subr.S
Log Message:
Optimise the interrupt vector a litte. From matt@
To generate a diff of this commit:
cvs rdiff -u -r1.95 -r1.96
Module Name:src
Committed By: skrll
Date: Fri Nov 18 16:23:40 UTC 2016
Modified Files:
src/sys/arch/mips/mips: spl.S
Log Message:
Sprinkle MFC0_HAZARD for previous and PARANOIA
To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/mips/mips/spl.S
Module Name:src
Committed By: macallan
Date: Fri Nov 18 13:50:36 UTC 2016
Modified Files:
src/sys/arch/mips/mips: spl.S
Log Message:
don't blindly zero STATUS in order to disable interrupts, instead take care
to preserve bits like KX in case we catch an interrupt between
Module Name:src
Committed By: maya
Date: Fri Nov 11 16:49:30 UTC 2016
Modified Files:
src/sys/arch/mips/mips: spl.S
Log Message:
switch post-mfc0 call "hazard barrier" from NOP_L to MFC0_HAZARD.
this means it will be applied if MIPS3 too, and now with the prior
commit,
Module Name:src
Committed By: maya
Date: Fri Nov 11 16:45:14 UTC 2016
Modified Files:
src/sys/arch/mips/mips: spl.S
Log Message:
remove redundant NOP_L. we do not use the register immediately after
load, so it's not needed.
To generate a diff of this commit:
cvs rdiff
Module Name:src
Committed By: maya
Date: Fri Nov 11 16:41:32 UTC 2016
Modified Files:
src/sys/arch/mips/include: asm.h
Log Message:
switch mfc0_hazard to be superscalar nop, some mips3 are superscalar
and need this to do the right thing
To generate a diff of this
Module Name:src
Committed By: maya
Date: Wed Nov 9 11:50:09 UTC 2016
Modified Files:
src/sys/arch/mips/include: asm.h
src/sys/arch/mips/mips: locore.S mipsX_subr.S
Log Message:
Move MFC0_HAZARD definition to asm.h instead of defining it twice
To generate a diff
Module Name:src
Committed By: skrll
Date: Fri Nov 4 08:24:36 UTC 2016
Modified Files:
src/sys/arch/mips/include: vmparam.h
Log Message:
Cmoment formatting. No functional change.
To generate a diff of this commit:
cvs rdiff -u -r1.55 -r1.56
Module Name:src
Committed By: skrll
Date: Mon Oct 31 12:49:04 UTC 2016
Modified Files:
src/sys/arch/mips/include: cpu.h
src/sys/arch/mips/mips: cpu_subr.c
Log Message:
Pre-allocate some kcpuset_ts so that we don't try and allocate in the
wrong context.
To
Module Name:src
Committed By: skrll
Date: Mon Oct 31 12:27:23 UTC 2016
Modified Files:
src/sys/arch/mips/cavium: octeon_intr.c
Log Message:
Fixup IPI interrupt delivery and splsched mask so that
sys/uvm/pmap/pmap_tlb.c
541 KASSERTMSG(ci->ci_cpl >= IPL_SCHED,
Module Name:src
Committed By: maxv
Date: Sun Oct 16 10:57:58 UTC 2016
Modified Files:
src/sys/arch/mips/mips: cpu_exec.c
Log Message:
Remove unused (and buggy) function. Not even compile-tested, but I've
been told to go ahead anyway.
To generate a diff of this commit:
Module Name:src
Committed By: macallan
Date: Thu Oct 13 18:58:00 UTC 2016
Modified Files:
src/sys/arch/mips/mips: locore.S
Log Message:
include locore.h for MIPS3_PLUS, while there annotate some #else and #endif
To generate a diff of this commit:
cvs rdiff -u -r1.206
Module Name:src
Committed By: macallan
Date: Thu Oct 13 18:54:46 UTC 2016
Modified Files:
src/sys/arch/mips/mips: fp.S
Log Message:
include locore.h so MIPS3_PLUS is visible and we build support for MIPS-III
and newer FPUs as needed
no more SIGILLs on trunc.d.* with n32
Module Name:src
Committed By: macallan
Date: Thu Oct 13 18:52:30 UTC 2016
Modified Files:
src/sys/arch/mips/include: locore.h
Log Message:
sprinkle #ifndef __ASSEMBLER__ to make this file usable from .S - mostly for
macros like MIPS3_PLUS
To generate a diff of this
Module Name:src
Committed By: skrll
Date: Mon Oct 10 07:37:56 UTC 2016
Modified Files:
src/sys/arch/mips/mips: cache_r5k.c
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/mips/mips/cache_r5k.c
Please note that
Module Name:src
Committed By: skrll
Date: Mon Oct 10 07:37:17 UTC 2016
Modified Files:
src/sys/arch/mips/mips: cache_r5k.c
Log Message:
vaddr_t -> register_t in range cache ops
To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18
Module Name:src
Committed By: skrll
Date: Sat Oct 8 08:19:22 UTC 2016
Modified Files:
src/sys/arch/mips/mips: mips_fixup.c
Log Message:
Sign extend VA for cache operations.
OK matt@
To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19
Module Name:src
Committed By: ryo
Date: Wed Oct 5 15:39:31 UTC 2016
Modified Files:
src/sys/arch/mips/ralink: ralink_eth.c ralink_reg.h
Log Message:
KNF; indent, spaces and tabs.
No functional change.
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10
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