Module Name:src
Committed By: skrll
Date: Tue May 18 06:42:12 UTC 2021
Modified Files:
src/sys/arch/riscv/include: db_machdep.h
Log Message:
Use #define in this file
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/include/db_machdep.h
Module Name:src
Committed By: skrll
Date: Tue May 18 06:40:16 UTC 2021
Modified Files:
src/sys/arch/riscv/include: db_machdep.h
Log Message:
Remove argument names from function declaration prototypes.
Misc tidyup.
To generate a diff of this commit:
cvs rdiff -u -r1.3
Module Name:src
Committed By: skrll
Date: Sun May 16 09:02:04 UTC 2021
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
s/ENTRY/ENTRY_NP/ in a few places
To generate a diff of this commit:
cvs rdiff -u -r1.21 -r1.22 src/sys/arch/riscv/riscv/locore.S
Module Name:src
Committed By: jmcneill
Date: Wed May 5 12:47:02 UTC 2021
Added Files:
src/sys/arch/riscv/include: loadfile_machdep.h
Log Message:
Add loadfile_machdep.h for riscv
To generate a diff of this commit:
cvs rdiff -u -r0 -r1.1
Module Name:src
Committed By: skrll
Date: Mon May 3 20:07:57 UTC 2021
Modified Files:
src/sys/arch/riscv/include: types.h
Log Message:
Sort __HAVE_ #defines. NFCI.
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/riscv/include/types.h
Please
Module Name:src
Committed By: skrll
Date: Sat May 1 07:41:24 UTC 2021
Modified Files:
src/sys/arch/riscv/include: pmap.h pte.h vmparam.h
src/sys/arch/riscv/riscv: pmap_machdep.c
Log Message:
Fixup some pmap / VM related #defines and code
To generate a diff of
Module Name:src
Committed By: skrll
Date: Sat May 1 07:13:21 UTC 2021
Modified Files:
src/sys/arch/riscv/conf: Makefile.riscv kern.ldscript
Log Message:
Fixup kernel linking and provide a linker script with standard sections
and symbols
To generate a diff of this
Module Name:src
Committed By: skrll
Date: Sat May 1 07:11:12 UTC 2021
Modified Files:
src/sys/arch/riscv/riscv: autoconf.c
Log Message:
Enable interrupts at the end of cpu_configure
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3
Module Name:src
Committed By: skrll
Date: Sat May 1 07:10:34 UTC 2021
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
Quick hack to make this link
To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/riscv/riscv/locore.S
Please
Module Name:src
Committed By: skrll
Date: Sat May 1 07:09:55 UTC 2021
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
Provide riscvreg_satp_{read,write}
To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/riscv/include/sysreg.h
Module Name:src
Committed By: skrll
Date: Sat May 1 07:09:04 UTC 2021
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
Indent the FCSR_FRM value #defines
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/riscv/include/sysreg.h
Module Name:src
Committed By: skrll
Date: Sat May 1 07:06:54 UTC 2021
Modified Files:
src/sys/arch/riscv/include: param.h
Log Message:
Bump MSGBUFSIZE (if not defined)
Provide COHERENCY_UNIT and CACHE_LINE_SIZE
Also provide MAXCPUS
To generate a diff of this commit:
Module Name:src
Committed By: skrll
Date: Sat May 1 07:05:07 UTC 2021
Modified Files:
src/sys/arch/riscv/include: asm.h
Log Message:
Provide __CONCAT, __STRING and ___CONCAT
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/include/asm.h
Module Name:src
Committed By: skrll
Date: Sat May 1 06:53:09 UTC 2021
Modified Files:
src/sys/arch/riscv/include: locore.h
src/sys/arch/riscv/riscv: riscv_machdep.c
Log Message:
Sprinkle #ifdef FPE for now
To generate a diff of this commit:
cvs rdiff -u -r1.7
Module Name:src
Committed By: skrll
Date: Sat May 1 06:48:51 UTC 2021
Modified Files:
src/sys/arch/riscv/riscv: db_disasm.c
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/riscv/db_disasm.c
Please note
Module Name:src
Committed By: skrll
Date: Sat May 1 06:45:23 UTC 2021
Modified Files:
src/sys/arch/riscv/include: types.h
Log Message:
Make paddr_t/psize_t __uint64_t for both 32 and 64 bit ports
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11
Module Name:src
Committed By: skrll
Date: Tue Apr 20 10:15:34 UTC 2021
Modified Files:
src/sys/arch/riscv/riscv: db_disasm.c
Log Message:
KNF
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/riscv/db_disasm.c
Please note that diffs are not
Module Name:src
Committed By: skrll
Date: Tue Apr 20 10:01:37 UTC 2021
Modified Files:
src/sys/arch/riscv/riscv: db_disasm.c
Log Message:
compile fixes
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/riscv/db_disasm.c
Please note that
Module Name:src
Committed By: dholland
Date: Mon Apr 19 07:55:59 UTC 2021
Modified Files:
src/sys/arch/riscv/include: insn.h
src/sys/arch/riscv/riscv: db_disasm.c
Log Message:
Make the riscv disassembler work, as best as I can test from amd64 userspace.
To
Module Name:src
Committed By: dholland
Date: Wed Apr 14 06:32:20 UTC 2021
Modified Files:
src/sys/arch/riscv/include: db_machdep.h insn.h
src/sys/arch/riscv/riscv: db_disasm.c db_machdep.c
Log Message:
Add a ddb disassembler for riscv.
builds, but not really
Module Name:src
Committed By: skrll
Date: Sun Nov 15 08:09:56 UTC 2020
Modified Files:
src/sys/arch/riscv/include: pmap.h
Log Message:
This file is #define
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/include/pmap.h
Please note that
Module Name:src
Committed By: skrll
Date: Sat Nov 14 13:05:14 UTC 2020
Modified Files:
src/sys/arch/riscv/riscv: trap.c
Log Message:
Improve dump_trapframe output layout and fix printing of s6/s7
To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14
Module Name:src
Committed By: skrll
Date: Tue Nov 10 06:58:46 UTC 2020
Modified Files:
src/sys/arch/riscv/riscv: spl.S
Log Message:
Revamp to the point it builds, but needs more work
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5
Module Name:src
Committed By: skrll
Date: Sun Nov 8 10:08:28 UTC 2020
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
Fix register usage
To generate a diff of this commit:
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/riscv/riscv/locore.S
Please note that
Module Name:src
Committed By: skrll
Date: Sun Nov 8 08:12:17 UTC 2020
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
Fix a typo
To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/riscv/riscv/locore.S
Please note that diffs are
Module Name:src
Committed By: skrll
Date: Sun Nov 8 08:11:15 UTC 2020
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
Remove unnecessary local labels
To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/riscv/riscv/locore.S
Please
Module Name:src
Committed By: skrll
Date: Sun Nov 8 08:07:43 UTC 2020
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
Use correct instruction to load address of exception_userexit into RA
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17
Module Name:src
Committed By: skrll
Date: Sat Nov 7 14:48:46 UTC 2020
Modified Files:
src/sys/arch/riscv/include: vmparam.h
Log Message:
Use lower case for hex constants
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/include/vmparam.h
Module Name:src
Committed By: skrll
Date: Sat Nov 7 10:48:17 UTC 2020
Modified Files:
src/sys/arch/riscv/include: reg.h
Log Message:
Whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/riscv/include/reg.h
Please note that diffs are not
Module Name:src
Committed By: skrll
Date: Sat Nov 7 10:47:35 UTC 2020
Modified Files:
src/sys/arch/riscv/include: reg.h
Log Message:
Indent and annotate FP registers much like the general registers
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7
Module Name:src
Committed By: skrll
Date: Sat Nov 7 10:43:47 UTC 2020
Modified Files:
src/sys/arch/riscv/include: reg.h
Log Message:
Note if a register is Caller / Callee saved
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/include/reg.h
Module Name:src
Committed By: skrll
Date: Wed Nov 4 20:05:47 UTC 2020
Modified Files:
src/sys/arch/riscv/include: sysreg.h
src/sys/arch/riscv/riscv: genassym.cf locore.S riscv_machdep.c
Log Message:
Miscellaneous updates to reflect riscv-privileged-20190608.pdf
Module Name:src
Committed By: skrll
Date: Wed Nov 4 20:04:01 UTC 2020
Modified Files:
src/sys/arch/riscv/riscv: trap.c vm_machdep.c
Log Message:
Miscellaneous updates to reflect riscv-privileged-20190608.pdf
Some from zmcgrew@
To generate a diff of this commit:
cvs
Module Name:src
Committed By: skrll
Date: Wed Nov 4 07:51:09 UTC 2020
Modified Files:
src/sys/arch/riscv/include: frame.h
src/sys/arch/riscv/riscv: genassym.cf
Log Message:
Fix some of the previous - I must have compile tested the wrong tree
To generate a diff
Module Name:src
Committed By: skrll
Date: Wed Nov 4 07:41:34 UTC 2020
Modified Files:
src/sys/arch/riscv/include: reg.h
Log Message:
whitespace in comments
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/include/reg.h
Please note that
Module Name:src
Committed By: skrll
Date: Wed Nov 4 07:40:15 UTC 2020
Modified Files:
src/sys/arch/riscv/include: reg.h
Log Message:
typo in comment
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/include/reg.h
Please note that diffs are
Module Name:src
Committed By: skrll
Date: Wed Nov 4 07:09:46 UTC 2020
Modified Files:
src/sys/arch/riscv/conf: kern.ldscript
src/sys/arch/riscv/htif: htif.c htif_cons.c htif_disk.c htif_var.h
src/sys/arch/riscv/include: insn.h locore.h
Module Name:src
Committed By: skrll
Date: Wed Nov 4 06:56:56 UTC 2020
Modified Files:
src/sys/arch/riscv/conf: GENERIC files.riscv
src/sys/arch/riscv/include: frame.h locore.h sysreg.h
src/sys/arch/riscv/riscv: core_machdep.c db_machdep.c genassym.cf
Module Name:src
Committed By: skrll
Date: Wed Nov 4 06:24:44 UTC 2020
Modified Files:
src/sys/arch/riscv/include: reg.h
Log Message:
Remove incorrect comment
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/include/reg.h
Please note that
Module Name:src
Committed By: skrll
Date: Mon Nov 2 08:37:59 UTC 2020
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
Add SATP_MODE values
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/riscv/include/sysreg.h
Please note
Module Name:src
Committed By: skrll
Date: Mon Nov 2 08:36:54 UTC 2020
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
Whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/include/sysreg.h
Please note that diffs
Module Name:src
Committed By: skrll
Date: Sun Nov 1 21:09:48 UTC 2020
Modified Files:
src/sys/arch/riscv/include: sysreg.h
src/sys/arch/riscv/riscv: trap.c
Log Message:
Update CAUSE_* defines to reflect riscv-privileged-20190608.pdf
To generate a diff of this
Module Name:src
Committed By: skrll
Date: Sun Nov 1 21:06:22 UTC 2020
Modified Files:
src/sys/arch/riscv/riscv: trap.c
Log Message:
Remove unused variable
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/riscv/riscv/trap.c
Please note that
Module Name:src
Committed By: skrll
Date: Sun Nov 1 21:01:49 UTC 2020
Modified Files:
src/sys/arch/riscv/riscv: clock_machdep.c
Log Message:
Don't shadow 'hz'
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/riscv/clock_machdep.c
Please
Module Name:src
Committed By: skrll
Date: Sun Nov 1 20:56:24 UTC 2020
Modified Files:
src/sys/arch/riscv/riscv: trap.c
Log Message:
Typo in a trap name
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/riscv/riscv/trap.c
Please note that diffs
Module Name:src
Committed By: skrll
Date: Sun Nov 1 19:47:46 UTC 2020
Modified Files:
src/sys/arch/riscv/include: pte.h
Log Message:
Comments from zmcgrew@
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/include/pte.h
Please note that
Module Name:src
Committed By: skrll
Date: Sat Oct 31 15:18:09 UTC 2020
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
Use the 'mv' pseudo-instruction instead of the 'move' equivalent as 'mv'
is mentioned in the ISA documentation and it's used elsewhere.
Module Name:src
Committed By: skrll
Date: Mon Aug 10 06:53:11 UTC 2020
Modified Files:
src/sys/arch/riscv/include: pmap.h
Log Message:
Whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/include/pmap.h
Please note that diffs are
Module Name:src
Committed By: skrll
Date: Mon Apr 6 20:26:17 UTC 2020
Modified Files:
src/sys/arch/riscv/riscv: trap.c
Log Message:
Whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/riscv/trap.c
Please note that diffs are not
Module Name:src
Committed By: christos
Date: Sat Apr 4 21:13:20 UTC 2020
Modified Files:
src/sys/arch/riscv/include: byte_swap.h
Log Message:
silence lint.
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/include/byte_swap.h
Please note
Module Name:src
Committed By: skrll
Date: Sat Mar 14 16:12:16 UTC 2020
Modified Files:
src/sys/arch/riscv/conf: Makefile.riscv majors.riscv
src/sys/arch/riscv/include: asm.h elf_machdep.h fenv.h frame.h ieeefp.h
locore.h mcontext.h pte.h sysreg.h
Module Name:src
Committed By: mrg
Date: Wed Apr 17 11:01:19 UTC 2019
Modified Files:
src/sys/arch/riscv/include: int_fmtio.h
Log Message:
fix for riscv32.
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/include/int_fmtio.h
Please note
Module Name:src
Committed By: maya
Date: Tue Apr 16 07:40:03 UTC 2019
Modified Files:
src/sys/arch/riscv/include: math.h
Log Message:
RISC-V ELF psABI says ILP32 also defaults to 128bit long double.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3
Module Name:src
Committed By: maya
Date: Tue Apr 16 07:08:52 UTC 2019
Modified Files:
src/sys/arch/riscv/include: int_fmtio.h
Log Message:
We're now using gcc netbsd-stdint.h instead of our own definitions, so
match those with the format types
XXX wrong for 32bit.
XXX
Module Name:src
Committed By: maya
Date: Mon Apr 15 14:03:32 UTC 2019
Modified Files:
src/sys/arch/riscv/include: byte_swap.h
Log Message:
Avoid -Wconversion warnings
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/include/byte_swap.h
Module Name:src
Committed By: maya
Date: Sat Apr 13 15:57:31 UTC 2019
Modified Files:
src/sys/arch/riscv/include: ieee.h math.h
Log Message:
Our current configuration is that long double is 128bit, so reflect
that in the relevant headers.
Taken from sparc64.
To
Module Name:src
Committed By: maya
Date: Sat Apr 13 15:56:18 UTC 2019
Modified Files:
src/sys/arch/riscv/include: int_fmtio.h
Log Message:
Provide defines for the 64bit case.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2
Module Name:src
Committed By: maya
Date: Sat Apr 13 12:41:37 UTC 2019
Modified Files:
src/sys/arch/riscv/include: asm.h
Log Message:
Handle changes since the gcc riscv toolchain was upstreamed
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3
Module Name:src
Committed By: kamil
Date: Thu Apr 11 11:23:52 UTC 2019
Modified Files:
src/sys/arch/riscv/include: locore.h
Log Message:
Fix a typo in a comment
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/include/locore.h
Please note
Module Name:src
Committed By: dholland
Date: Sun Jan 27 18:00:06 UTC 2019
Modified Files:
src/sys/arch/riscv/conf: majors.riscv
Log Message:
This may have been cutpasted from evbmips, but we don't need to say so.
To generate a diff of this commit:
cvs rdiff -u -r1.5
Module Name:src
Committed By: christos
Date: Mon Apr 23 15:40:33 UTC 2018
Modified Files:
src/sys/arch/riscv/riscv: db_machdep.c
Log Message:
PR/53206: David Binderman: fix array bounds comparison in KASSERT.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2
Module Name:src
Committed By: maya
Date: Mon Feb 5 10:41:12 UTC 2018
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
Fix tyop
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/riscv/locore.S
Please note that diffs are not
Module Name:src
Committed By: kamil
Date: Mon Dec 5 07:24:16 UTC 2016
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
Fix cpu_switchto(9) prototype in a comment
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6
Module Name:src
Committed By: matt
Date: Fri Jun 26 14:20:11 UTC 2015
Modified Files:
src/sys/arch/riscv/include: lock.h
Log Message:
Fix cp error.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/include/lock.h
Please note that diffs are
Module Name:src
Committed By: matt
Date: Thu May 28 02:19:05 UTC 2015
Modified Files:
src/sys/arch/riscv/include: elf_machdep.h
Log Message:
add ELF64_MACHDEP_ID
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/include/elf_machdep.h
Please
Module Name:src
Committed By: matt
Date: Wed Apr 1 21:55:03 UTC 2015
Modified Files:
src/sys/arch/riscv/include: cpu.h
Log Message:
_KMEMUSER only needs struct cpu_info
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/include/cpu.h
Please
Module Name:src
Committed By: matt
Date: Wed Apr 1 21:55:33 UTC 2015
Modified Files:
src/sys/arch/riscv/include: mcontext.h
Log Message:
Add _REG_S0
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/include/mcontext.h
Please note that
Module Name:src
Committed By: matt
Date: Wed Apr 1 21:59:01 UTC 2015
Modified Files:
src/sys/arch/riscv/include: elf_machdep.h
Log Message:
Add two new relocs for compressed branches.
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4
Module Name:src
Committed By: matt
Date: Tue Mar 31 06:47:47 UTC 2015
Modified Files:
src/sys/arch/riscv/include: proc.h
src/sys/arch/riscv/riscv: genassym.cf locore.S
Log Message:
Optimize the exception handle a little bit more.
To generate a diff of this
Module Name:src
Committed By: matt
Date: Tue Mar 31 11:48:10 UTC 2015
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
Fix botch on putting user stack pointer into trapframe.
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4
Module Name:src
Committed By: matt
Date: Tue Mar 31 11:53:14 UTC 2015
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
Accept the one instruction penalty and just use PTR_LA instead of doing
the relocs ourselves.
To generate a diff of this commit:
cvs
Module Name:src
Committed By: matt
Date: Tue Mar 31 01:14:02 UTC 2015
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
No more fatc (replaced by sfence.vm instruction).
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3
Module Name:src
Committed By: matt
Date: Tue Mar 31 01:05:52 UTC 2015
Modified Files:
src/sys/arch/riscv/conf: Makefile.riscv
Log Message:
Use -mcmodel=medany to get PICish code.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2
Module Name:src
Committed By: matt
Date: Tue Mar 31 01:30:50 UTC 2015
Modified Files:
src/sys/arch/riscv/riscv: locore.S
Log Message:
Since there is only scratch system register for use on exception, come
up with a new scheme for its use. Use PTR_LA, INT_S/INT_L, etc.
Module Name:src
Committed By: matt
Date: Tue Mar 31 01:15:26 UTC 2015
Modified Files:
src/sys/arch/riscv/riscv: spl.S
Log Message:
Get curcpu() from L_CPU(tp)
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/riscv/spl.S
Please note that
Module Name:src
Committed By: matt
Date: Tue Mar 31 01:14:57 UTC 2015
Modified Files:
src/sys/arch/riscv/riscv: pmap_machdep.c
Log Message:
Use sfence.vm instruction and change ptbr cse to sptbr csr
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2
Module Name:src
Committed By: matt
Date: Tue Mar 31 01:12:47 UTC 2015
Modified Files:
src/sys/arch/riscv/riscv: genassym.cf
Log Message:
Add L_MD_TP
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cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/riscv/genassym.cf
Please note that diffs
Module Name:src
Committed By: matt
Date: Tue Mar 31 01:12:30 UTC 2015
Modified Files:
src/sys/arch/riscv/include: proc.h
Log Message:
Add a md_tp member to mdlwp so that the exception handler can temporarily
store the user's thread pointer before saving it in the
Module Name:src
Committed By: matt
Date: Tue Mar 31 01:11:42 UTC 2015
Modified Files:
src/sys/arch/riscv/include: cpu.h
Log Message:
Define curcpu() as lwp_getcpu(curlwp) since curlwp is always in the tp
(thread pointer) register.
To generate a diff of this commit:
cvs
Module Name:src
Committed By: matt
Date: Sun Mar 29 09:43:26 UTC 2015
Modified Files:
src/sys/arch/riscv/include: lock.h
Log Message:
Use C11 atomic builtins instead of __asm.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/include/lock.h
Module Name:src
Committed By: matt
Date: Fri Mar 27 06:57:21 UTC 2015
Modified Files:
src/sys/arch/riscv/include: asm.h elf_machdep.h mcontext.h reg.h
setjmp.h
Log Message:
Switch to new ABI (return values now in a0/a1; v0/v1 are no more)
To generate a diff
Module Name:src
Committed By: matt
Date: Fri Mar 27 23:26:14 UTC 2015
Modified Files:
src/sys/arch/riscv/include: elf_machdep.h
Log Message:
Fix one error and make life for ld.elf_so a little easier.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3
Module Name:src
Committed By: dennis
Date: Tue Oct 28 19:46:18 UTC 2014
Modified Files:
src/sys/arch/riscv/include: byte_swap.h
Log Message:
Correct 32 and 64 bit byte swap inlines.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2
Module Name:src
Committed By: dennis
Date: Tue Oct 28 20:25:36 UTC 2014
Modified Files:
src/sys/arch/riscv/include: byte_swap.h
Log Message:
Shave an instruction from the generated code for the 32 bit byte
swap inline. Prune 5 or 9 instructions (depending on what you
Module Name:src
Committed By: dennis
Date: Fri Oct 24 01:08:07 UTC 2014
Modified Files:
src/sys/arch/riscv/include: mcontext.h
Log Message:
Fix a typo: the PC is likely in _REG_PC
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2
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