Re: When did PCs stop using ISA Timer 1?
On Sat, Aug 27, 2022 at 7:15 AM Jonathan Gray wrote: > > On Fri, Aug 26, 2022 at 10:21:32PM -0500, Scott Cheloha wrote: > > I noticed that on non-LAPIC systems we program channel 0 in periodic > > mode with an initial count of 11932 to effect a 100hz clock interrupt. > > And then we also use that same channel to count time, but because we > > aren't using the full 16-bit range we need to do all this checking and > > incrementing to handle premature overflow to make it appear as though > > the full counter is being used. > > > > And I had this whimsical idea: gee, wouldn't it be so much easier to > > use channel 0 for clock interrupts and a different channel for > > counting time? > > > > But then I started reading and saw that channel 1 had a dedicated > > purpose in the bad old days. > > > > So I was left wondering when channel 1 stopped performing that task, > > and whether those systems (a) predate the APIC and (b) can even run > > OpenBSD at all. > > Attempting to use counter 1 would be more trouble than it is worth. Hi Scott, we discussed this off-list, but just to share here. There is a good writeup of how it all used to work here: https://retrocomputing.stackexchange.com/questions/1212/where-are-the-memory-controllers-for-ibm-5150-or-altair-8800 Quoting that site: "RAM refresh was done by a cyclic inserted DMA request using DMA channel 4 of the 8237 DMA controller, triggered by Timer 1 of the 8253 Programmable Interval Timer." That being said, later on channel 1 was used by video bios and some bioses, so really it can't be used by OS safely for anything. See: https://www.brokenthorn.com/Resources/OSDevPit.html "Many video cards and the BIOS may reprogram the second channel for their own uses. This channel was originally used for generating a timing pulse signal to signal the memory controller to refresh the DRAM memory. In modern times, this is no longer needed as the refresh is done by the memory controller. Because of this, there is no guarantee at what devices may use this counter." My guess is that any system with 32mb of RAM or more would be unlikely to to be a place where we have to worry about channel 1 being used for DRAM refresh. > > > > > > The PCH datasheets from 100 series and later only document counter 0 > > > and counter 2. > > > Right, these days some chipsets don't even provide channel 1 anymore. So either the system has channel 1 and it should be considered reserved, or the system may not have channel 1 in which case it's not available for use by the OS. In either case, the OS should not use this channel. p.s. we should probably update the comment in usr.sbin/vmd/i8253.c which currently states: 40: * Channels 1 and 2 can be used by the guest OS as regular timers,
Re: When did PCs stop using ISA Timer 1?
Jonathan Gray wrote: > On Fri, Aug 26, 2022 at 10:21:32PM -0500, Scott Cheloha wrote: > > I noticed that on non-LAPIC systems we program channel 0 in periodic > > mode with an initial count of 11932 to effect a 100hz clock interrupt. > > And then we also use that same channel to count time, but because we > > aren't using the full 16-bit range we need to do all this checking and > > incrementing to handle premature overflow to make it appear as though > > the full counter is being used. > > > > And I had this whimsical idea: gee, wouldn't it be so much easier to > > use channel 0 for clock interrupts and a different channel for > > counting time? > > > > But then I started reading and saw that channel 1 had a dedicated > > purpose in the bad old days. > > > > So I was left wondering when channel 1 stopped performing that task, > > and whether those systems (a) predate the APIC and (b) can even run > > OpenBSD at all. > > Attempting to use counter 1 would be more trouble than it is worth. I would not be surprised if there existed machines with broken counter 1 (in some subtle way).
Re: When did PCs stop using ISA Timer 1?
On Fri, Aug 26, 2022 at 10:21:32PM -0500, Scott Cheloha wrote: > I noticed that on non-LAPIC systems we program channel 0 in periodic > mode with an initial count of 11932 to effect a 100hz clock interrupt. > And then we also use that same channel to count time, but because we > aren't using the full 16-bit range we need to do all this checking and > incrementing to handle premature overflow to make it appear as though > the full counter is being used. > > And I had this whimsical idea: gee, wouldn't it be so much easier to > use channel 0 for clock interrupts and a different channel for > counting time? > > But then I started reading and saw that channel 1 had a dedicated > purpose in the bad old days. > > So I was left wondering when channel 1 stopped performing that task, > and whether those systems (a) predate the APIC and (b) can even run > OpenBSD at all. Attempting to use counter 1 would be more trouble than it is worth. > > What is the minimum chipset? 486? 586? You've been doing some > sprucing, so I am unsure. I know the 80386 is out. We have a minimum architecture level, not chipset. Our toolchain defaults to 586. This ensures that 64-bit atomic builtins are available. 586 includes cr4, cpuid, rdtsc, rdmsr etc As to when the APIC was introduced vol 3b of Intel's x86 SDM has: "The Advanced Programmable Interrupt Controller (APIC), referred to in this book as the local APIC, was introduced into the IA-32 processors with the Pentium processor (beginning with the 735/90 and 815/100 models) and is included in the Pentium 4, Intel Xeon, and P6 family processors. The features and functions of the local APIC are derived from the Intel 82489DX external APIC, which was used with the Intel486 and early Pentium processors. Additional refinements of the local APIC architecture were incorporated in the Pentium 4 and Intel Xeon processors." > > > The PCH datasheets from 100 series and later only document counter 0 > > and counter 2. > > > > 9 series and earlier datasheet has > > "The PCH contains three counters that have fixed uses." > > 100 series and later > > "The PCH contains two counters that have fixed uses." > > What does the PCH 9 series and earlier pertain to? What socket would > have it? 9 series is H97/Z97/X99 https://ark.intel.com/content/www/us/en/ark/products/series/98458/intel-9-series-chipsets.html https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/9-series-chipset-pch-datasheet.pdf
Re: When did PCs stop using ISA Timer 1?
On Sat, Aug 27, 2022 at 11:33:58AM +1000, Jonathan Gray wrote: > On Fri, Aug 26, 2022 at 11:09:19AM -0500, Scott Cheloha wrote: > > Hi, > > > > TLDR: > > > > 1. When did PCs stop using ISA Timer 1 to trigger DRAM refresh? > > > > 2. Are any PCs that rely on ISA Timer 1 for DRAM refresh capable of > >running OpenBSD as it exists today? > > > > Long version: > > > > I have a history question for the list. Maybe one of you hardware > > jocks or history buffs can help me out. > > > > So, in the IBM AT/PC and, later, all ISA-compatible systems, the ISA > > timer (an i8253 or compatible clock) has 3 independent 16-bit > > counters. > > > > The first, Timer 0, is available for use by the operating system. > > > > The second, Timer 1, was traditionally programmed by the BIOS at a > > particular rate to trigger DRAM refresh. > > > > The third, Timer 2, is usually wired up to the PC speaker and may be > > used by the operating system to produce primitive sound effects. > > > > I found a more detailed explanation of what Timer 1 actually did in > > this book: > > > > https://ia601901.us.archive.org/12/items/ISA_System_Architecture/ISA_System_Architecture.pdf > > > > > ISA System Architecture Third Edition (1995) > > > Chapter 24: ISA Timers > > > p. 471 > > > > > > Refresh Timer (Timer 1) > > > > > > The refresh timer, or timer 1, is a programmable frequency source. The > > > same 1.19318MHz signal (used by timer 0) provides the refresh timer's > > > clock input. The programmer specifies a divisor to be divided into > > > the input clock to yield the desired output frequency. During the > > > POST, a divisor of 0012h, or a decimal 18, is written to the refresh > > > timer at I/O address 0041h. The input clock frequency of 1.19318MHz is > > > therefore divided by 18 to yield an output frequency of 66287.77Hz, > > > or a pulse every 15.09 microseconds. > > > > > > This is the refresh request signal that triggers the DRAM refresh > > > logic to become bus master once every 15.09 microseconds so it can > > > refresh another row in DRAM memory throughout the system. For more > > > information on DRAM refresh, refer to the chapter entitled "RAM > > > Memory: Theory of Operation." > > > > This is fascinating. > > > > But obviously this is no longer true in modern PCs. The ISA bus is > > still emulated in modern PCs, and DRAM in modern PCs still needs > > refreshing, but they don't rely on the emulated ISA timer to make it > > happen. > > > > So, when did PCs stop using ISA Timer 1 for DRAM refresh? > > > > The IBM AT/PC was built around the 80286. Was it with the advent of > > the 80386 (1985)? The 80486 (1989)? P5 (1993)? P6 (1995)? Later? > > > > Was the change independent of a particular processor generation jump? > > Like, maybe a technological advance in the state of the art in DRAM > > obsoleted the use of ISA Timer 1 for refresh? > > > > And then, more importantly, are any machines that rely on ISA Timer 1 > > for DRAM refresh actually capable of running OpenBSD as it exists > > today? > > What difference does it make? We don't use counter 1. I noticed that on non-LAPIC systems we program channel 0 in periodic mode with an initial count of 11932 to effect a 100hz clock interrupt. And then we also use that same channel to count time, but because we aren't using the full 16-bit range we need to do all this checking and incrementing to handle premature overflow to make it appear as though the full counter is being used. And I had this whimsical idea: gee, wouldn't it be so much easier to use channel 0 for clock interrupts and a different channel for counting time? But then I started reading and saw that channel 1 had a dedicated purpose in the bad old days. So I was left wondering when channel 1 stopped performing that task, and whether those systems (a) predate the APIC and (b) can even run OpenBSD at all. What is the minimum chipset? 486? 586? You've been doing some sprucing, so I am unsure. I know the 80386 is out. > The PCH datasheets from 100 series and later only document counter 0 > and counter 2. > > 9 series and earlier datasheet has > "The PCH contains three counters that have fixed uses." > 100 series and later > "The PCH contains two counters that have fixed uses." What does the PCH 9 series and earlier pertain to? What socket would have it? (I didn't even know Intel had documented this, thanks.)
Re: When did PCs stop using ISA Timer 1?
Jonathan Gray wrote: >> What difference does it make? We don't use counter 1. > > The PCH datasheets from 100 series and later only document counter 0 > and counter 2. > > 9 series and earlier datasheet has > "The PCH contains three counters that have fixed uses." > 100 series and later > "The PCH contains two counters that have fixed uses." In other words: Since that counter was previously used for a well-defined purpose but then stopped being used for that case, there may be chipset vendors who decided to REMOVE or BREAK the hardware... I think you can assume nothing about it. This question can only be answered by finding a body of code which reliably uses it.
Re: When did PCs stop using ISA Timer 1?
On Fri, Aug 26, 2022 at 11:09:19AM -0500, Scott Cheloha wrote: > Hi, > > TLDR: > > 1. When did PCs stop using ISA Timer 1 to trigger DRAM refresh? > > 2. Are any PCs that rely on ISA Timer 1 for DRAM refresh capable of >running OpenBSD as it exists today? > > Long version: > > I have a history question for the list. Maybe one of you hardware > jocks or history buffs can help me out. > > So, in the IBM AT/PC and, later, all ISA-compatible systems, the ISA > timer (an i8253 or compatible clock) has 3 independent 16-bit > counters. > > The first, Timer 0, is available for use by the operating system. > > The second, Timer 1, was traditionally programmed by the BIOS at a > particular rate to trigger DRAM refresh. > > The third, Timer 2, is usually wired up to the PC speaker and may be > used by the operating system to produce primitive sound effects. > > I found a more detailed explanation of what Timer 1 actually did in > this book: > > https://ia601901.us.archive.org/12/items/ISA_System_Architecture/ISA_System_Architecture.pdf > > > ISA System Architecture Third Edition (1995) > > Chapter 24: ISA Timers > > p. 471 > > > > Refresh Timer (Timer 1) > > > > The refresh timer, or timer 1, is a programmable frequency source. The > > same 1.19318MHz signal (used by timer 0) provides the refresh timer's > > clock input. The programmer specifies a divisor to be divided into > > the input clock to yield the desired output frequency. During the > > POST, a divisor of 0012h, or a decimal 18, is written to the refresh > > timer at I/O address 0041h. The input clock frequency of 1.19318MHz is > > therefore divided by 18 to yield an output frequency of 66287.77Hz, > > or a pulse every 15.09 microseconds. > > > > This is the refresh request signal that triggers the DRAM refresh > > logic to become bus master once every 15.09 microseconds so it can > > refresh another row in DRAM memory throughout the system. For more > > information on DRAM refresh, refer to the chapter entitled "RAM > > Memory: Theory of Operation." > > This is fascinating. > > But obviously this is no longer true in modern PCs. The ISA bus is > still emulated in modern PCs, and DRAM in modern PCs still needs > refreshing, but they don't rely on the emulated ISA timer to make it > happen. > > So, when did PCs stop using ISA Timer 1 for DRAM refresh? > > The IBM AT/PC was built around the 80286. Was it with the advent of > the 80386 (1985)? The 80486 (1989)? P5 (1993)? P6 (1995)? Later? > > Was the change independent of a particular processor generation jump? > Like, maybe a technological advance in the state of the art in DRAM > obsoleted the use of ISA Timer 1 for refresh? > > And then, more importantly, are any machines that rely on ISA Timer 1 > for DRAM refresh actually capable of running OpenBSD as it exists > today? What difference does it make? We don't use counter 1. The PCH datasheets from 100 series and later only document counter 0 and counter 2. 9 series and earlier datasheet has "The PCH contains three counters that have fixed uses." 100 series and later "The PCH contains two counters that have fixed uses."
When did PCs stop using ISA Timer 1?
Hi, TLDR: 1. When did PCs stop using ISA Timer 1 to trigger DRAM refresh? 2. Are any PCs that rely on ISA Timer 1 for DRAM refresh capable of running OpenBSD as it exists today? Long version: I have a history question for the list. Maybe one of you hardware jocks or history buffs can help me out. So, in the IBM AT/PC and, later, all ISA-compatible systems, the ISA timer (an i8253 or compatible clock) has 3 independent 16-bit counters. The first, Timer 0, is available for use by the operating system. The second, Timer 1, was traditionally programmed by the BIOS at a particular rate to trigger DRAM refresh. The third, Timer 2, is usually wired up to the PC speaker and may be used by the operating system to produce primitive sound effects. I found a more detailed explanation of what Timer 1 actually did in this book: https://ia601901.us.archive.org/12/items/ISA_System_Architecture/ISA_System_Architecture.pdf > ISA System Architecture Third Edition (1995) > Chapter 24: ISA Timers > p. 471 > > Refresh Timer (Timer 1) > > The refresh timer, or timer 1, is a programmable frequency source. The > same 1.19318MHz signal (used by timer 0) provides the refresh timer's > clock input. The programmer specifies a divisor to be divided into > the input clock to yield the desired output frequency. During the > POST, a divisor of 0012h, or a decimal 18, is written to the refresh > timer at I/O address 0041h. The input clock frequency of 1.19318MHz is > therefore divided by 18 to yield an output frequency of 66287.77Hz, > or a pulse every 15.09 microseconds. > > This is the refresh request signal that triggers the DRAM refresh > logic to become bus master once every 15.09 microseconds so it can > refresh another row in DRAM memory throughout the system. For more > information on DRAM refresh, refer to the chapter entitled "RAM > Memory: Theory of Operation." This is fascinating. But obviously this is no longer true in modern PCs. The ISA bus is still emulated in modern PCs, and DRAM in modern PCs still needs refreshing, but they don't rely on the emulated ISA timer to make it happen. So, when did PCs stop using ISA Timer 1 for DRAM refresh? The IBM AT/PC was built around the 80286. Was it with the advent of the 80386 (1985)? The 80486 (1989)? P5 (1993)? P6 (1995)? Later? Was the change independent of a particular processor generation jump? Like, maybe a technological advance in the state of the art in DRAM obsoleted the use of ISA Timer 1 for refresh? And then, more importantly, are any machines that rely on ISA Timer 1 for DRAM refresh actually capable of running OpenBSD as it exists today? -Scott
