Yes, I remember that thread.
Anyway, Hal, are you suggesting to use the 3.2GHz clock to crank up the
counting speed? OK, strange, but can be a way...
On Wed, Dec 7, 2011 at 1:23 AM, Bob Camp wrote:
> Hi
>
> There was a point in time where a general purpose board could have been
> done on a group
Hi
There was a point in time where a general purpose board could have been done on
a group basis. The discussion of that offended some on the list. That prevented
it from being done in a timely manner. The funds that would have gone to the
project went to a closed design that is not available.
> At the moment I'm in the 2.5nS resolution range and successfully made a
> GPSDO that my company uses for the DVB-T synchronization needs. Next step
> will be to use a Maxim/Dallas delay line to hardware correct the PPS by the
> negative sawtooth and try to improve the TDC resolution. Maybe a sma
I have read the two papers about the wave union TDC but still wonder if
anything reasonable could be done without:
1) place every single gate by hand on the target silicon
2) heavy postprocess the data to obtain results
Something like: I have a Spartan3, the WebTool suite from Xilinx and, yes,
I ha
On Tue, 6 Dec 2011 17:06:43 -0500
"Bob Camp" wrote:
> It's the "wave union" one that the Fermi labs papers talk about. We started
> talking about a group design on one a while back. Ultimately it got taken
> off list
What is the status of that?
I would try to help if i didnt know that i hav
06, 2011 5:05 PM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] Help with TCXO
On Tue, 6 Dec 2011 21:47:24 +0100
Azelio Boriani wrote:
> I have read about the two main delay line techniques: the vernier delay
> line and the tapped delay line. These require
f Attila Kinali
Sent: Tuesday, December 06, 2011 4:52 PM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] Help with TCXO
On Tue, 6 Dec 2011 16:43:37 -0500
"Bob Camp" wrote:
> With reasonable calibration, it looks like you can get below 200 ps. You
&g
On Tue, 6 Dec 2011 21:47:24 +0100
Azelio Boriani wrote:
> I have read about the two main delay line techniques: the vernier delay
> line and the tapped delay line. These require a sort of on-the-fly
> calibration virtually for every sample you get because of the temperature
> and power supply dep
On Tue, 6 Dec 2011 16:43:37 -0500
"Bob Camp" wrote:
> With reasonable calibration, it looks like you can get below 200 ps. You
> will need to boost the clock up to ~ 400 MHz with one of the internal PLL's
> to get it to "fit" in a reasonable sized device.
With which design would that be?
:time-nuts-boun...@febo.com] On
Behalf Of Azelio Boriani
Sent: Tuesday, December 06, 2011 3:47 PM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] Help with TCXO
I have read about the two main delay line techniques: the vernier delay
line and the tapped delay line. These re
ent: Tuesday, December 06, 2011 10:25 AM
> To: Discussion of precise time and frequency measurement
> Subject: Re: [time-nuts] Help with TCXO
>
> Yes, with an analog interpolator you can. Without an analog interpolator
> and without using the vernier delay line (and other tricks like
-Original Message-
From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] On
Behalf Of Azelio Boriani
Sent: Tuesday, December 06, 2011 10:25 AM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] Help with TCXO
Yes, with an analog interpolator you
Yes, with an analog interpolator you can. Without an analog interpolator
and without using the vernier delay line (and other tricks like that), the
FPGA can only get to nS resolution so far (for example, in a Spartan3 or
equivalent). To implement a vernier delay line you need also to control the
lo
On Tue, 29 Nov 2011 11:23:26 +1100
Michael Malloy wrote:
> let me know if you want schematics for my other designs
I'm always interested in learning from others.
So, if it would be not too much a hassle, i'd greatly
appreciate if you could publish yous schematics/designs.
Especially, if you can
On Tue, 29 Nov 2011 16:09:34 +0100
Azelio Boriani wrote:
> FPGA time interval counter? With an analog interpolator? No? Then, at most,
> you will get a nS resolution. I have a 2.5nS resolution TIC with 100MHz
> clock using four phases from the Xilinx DCM in a Spartan3.
I'm quite sure you can do
FPGA time interval counter? With an analog interpolator? No? Then, at most,
you will get a nS resolution. I have a 2.5nS resolution TIC with 100MHz
clock using four phases from the Xilinx DCM in a Spartan3.
On Tue, Nov 29, 2011 at 1:23 AM, Michael Malloy wrote:
> Ok great thank you very much I w
Ok great thank you very much I will go get some 74HC14 today if possible
and replace them, I will also upload a schematic, and a smaller picture
i tried running on a bread board with a 4000 CMOS CD40106
the output looked like a square wave through a diode to LP filter not
good, like spikes
not wha
Ok to answer part of the original question.
Indeed I have see the "clipped sine wave" as you stated and it has no
negative component.
Numbers of vectrons and other xtal oscilators look like that. No negative
supply nor transformers so thats what you tend to get. Its normal. But as
you say feed into
On Mon, 28 Nov 2011 19:28:37 +1100
Michael Malloy wrote:
> I was pretty sure that the 4000 CMOS range was only really good sub
> 1Mhz I am wrong here? please correct me
> thats why I chose the 74HC series as its high speed CMOS??
High speed is a very relative term here. It's high speed compared
On Mon, 28 Nov 2011 19:29:41 +1100
Michael Malloy wrote:
> On Mon, Nov 28, 2011 at 7:14 PM, Michael Malloy wrote:
> > yeah it is squaring up, but not great I have already designed the
> > circuit boards, hmm
> > maybe if i replace the 74HC04 with a 74HC14 (schmitt trigger input)
> > which I do n
Sorry. Read:
"Or use a line-receiver if the oscillators is buffered internal."
- Henry
Michael Malloy schrieb:
its a shame i cannot post the picture i took is there any way to be
able to send my oscilloscope picture its 800k thats the problem
--
ehydra.dyndns.info
__
A 50K picture should fit the problem.
I successfully use 4000 series for amplifying a 5MHz PSK signal. The
HEF4x is a little faster than HCFx.
Or use a line-receiver if the oscillators is not buffered internal.
- Henry
Michael Malloy schrieb:
its a shame i cannot post the picture i took is
its a shame i cannot post the picture i took is there any way to be
able to send my oscilloscope picture its 800k thats the problem
On Mon, Nov 28, 2011 at 7:29 PM, Michael Malloy wrote:
> On Mon, Nov 28, 2011 at 7:14 PM, Michael Malloy wrote:
>> yeah it is squaring up, but not great I have alre
On Mon, Nov 28, 2011 at 7:14 PM, Michael Malloy wrote:
> yeah it is squaring up, but not great I have already designed the
> circuit boards, hmm
> maybe if i replace the 74HC04 with a 74HC14 (schmitt trigger input)
> which I do not have
> I did make a surface mount single gate schmitt trig after t
I was pretty sure that the 4000 CMOS range was only really good sub
1Mhz I am wrong here? please correct me
thats why I chose the 74HC series as its high speed CMOS??
On Mon, Nov 28, 2011 at 6:58 PM, ehydra wrote:
> Maybe the HC04 oscillates but the experimenter doesn't see it. Or
> misunderstood
Maybe the HC04 oscillates but the experimenter doesn't see it. Or
misunderstood that ICs have to be seen from top, not bottom like
transistors.
It is better to use an HCU04. Even a 4069UB should work at 8MHz@5V. I
would prefer 100K feedback and several stages AC-coupled.
The 5V is nominal, s
On Mon, 28 Nov 2011 16:15:37 +1100
Michael Malloy wrote:
> Hi all I ordered a 8.192MHZ TCXO 1.0PPM
> Now it was supposed to have a clipped sine wave output? however it
> looks more like a saw tooth, I assumed a clipped sine would be a sine
> wave with the peaks clipped, I am running this through
Hi all I ordered a 8.192MHZ TCXO 1.0PPM
Now it was supposed to have a clipped sine wave output? however it
looks more like a saw tooth, I assumed a clipped sine would be a sine
wave with the peaks clipped, I am running this through
a 150pF cap and then using a inverter amplifier i.e. 74HC04 with a
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