Yes, with an analog interpolator you can. Without an analog interpolator and without using the vernier delay line (and other tricks like that), the FPGA can only get to nS resolution so far (for example, in a Spartan3 or equivalent). To implement a vernier delay line you need also to control the logic translator and the technology fitter and know by heart your logic chip. Maybe one day they pop up with a time-nut FPGA compiler that is aware of intentionally-placed delay lines and stuff like this.
On Tue, Dec 6, 2011 at 3:43 PM, Attila Kinali <[email protected]> wrote: > On Tue, 29 Nov 2011 11:23:26 +1100 > Michael Malloy <[email protected]> wrote: > > > let me know if you want schematics for my other designs > > I'm always interested in learning from others. > So, if it would be not too much a hassle, i'd greatly > appreciate if you could publish yous schematics/designs. > Especially, if you can write a few words on what your > design decisions were. > > Attila Kinali > -- > The trouble with you, Shev, is you don't say anything until you've saved > up a whole truckload of damned heavy brick arguments and then you dump > them all out and never look at the bleeding body mangled beneath the heap > -- Tirin, The Dispossessed, U. Le Guin > > _______________________________________________ > time-nuts mailing list -- [email protected] > To unsubscribe, go to > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
