Re: [time-nuts] TIC model
R2 is dominated by the adc sample switch on resistance and thus has a relatively high tempco (~4000ppm/C). C2 has a relatively low tempco (~100ppm/C or so) To reduce the effect of the sample switch on resistance tempco on the gain tempco of the TIC R1 C1 need to be proportioned so that R2 has little effect on the gain temcpo. R1 = 470 ohm, C1 = 1nF (NPO) appears to be about right for a 2.5MHz synchroniser clock and the PIC you intend to use. This should reduce the effect of the sample switch on resistance tempco by a factor of 10 or more. The minimum value of R1 is governed by the output resistance of the tristate buffer and its tempco. Bruce Bob Stewart wrote: Hi Bruce, What are the tradeoffs with using different values for R1? I have no practical experience at this, so all I can do is rely on the models. Does the fact that R2 is in the PIC, and C1 is so tiny, make the value of R1 of less importance? On my PIC, they list C1 as 5pf, R2 as effectively about 7K, and C2 120pf. Bob From: Bruce Griffithsbruce.griffi...@xtra.co.nz To: Discussion of precise time and frequency measurementtime-nuts@febo.com Sent: Tuesday, February 18, 2014 9:35 PM Subject: Re: [time-nuts] TIC model The attached circuit schematic illustrates how this might be implemented. Faster logic devices can be substituted. R2, C2 approximate the equivalent input circuit of the ADC. R2, C2 values will vary for each ADC. The Shift register which acts as a synchroniser and produces various trigger signals is clocked at 10MHz (assumed to be the uP instruction cycle clock rate) The RC network charge time varies between 1 and 2 shift register clock periods ( ie a charge time from 100ns to 200ns). Sampling a time stamp counter clocked at the same frequency as the shift register is only required if the GPSDO local oscillator has a potential initial offset of 100ppb or more. If missing PPS detection is required then a PPS time stamp counter with a range of several seconds is desirable. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] TIC model
Now you've lost me. What 2.5 MHz synchronizer clock? Everything I have external to the PIC is 10MHz. The PIC is running HSPLL at 40MHz, though I don't think that makes any difference to this. Bob From: Bruce Griffiths bruce.griffi...@xtra.co.nz To: Bob Stewart b...@evoria.net; Discussion of precise time and frequency measurement time-nuts@febo.com Sent: Thursday, February 20, 2014 3:07 AM Subject: Re: [time-nuts] TIC model R2 is dominated by the adc sample switch on resistance and thus has a relatively high tempco (~4000ppm/C). C2 has a relatively low tempco (~100ppm/C or so) To reduce the effect of the sample switch on resistance tempco on the gain tempco of the TIC R1 C1 need to be proportioned so that R2 has little effect on the gain temcpo. R1 = 470 ohm, C1 = 1nF (NPO) appears to be about right for a 2.5MHz synchroniser clock and the PIC you intend to use. This should reduce the effect of the sample switch on resistance tempco by a factor of 10 or more. The minimum value of R1 is governed by the output resistance of the tristate buffer and its tempco. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] TIC model
For a 10MHz synchroniser clock A C1 value of around 220pF or so should be appropriate. The exact value depends on the ADC reference voltage. A n ADC reference less than 5V may be useful. I'll run some simulations to check the sensitivity to R2's tempco. Bruce Bob Stewart wrote: Now you've lost me. What 2.5 MHz synchronizer clock? Everything I have external to the PIC is 10MHz. The PIC is running HSPLL at 40MHz, though I don't think that makes any difference to this. Bob From: Bruce Griffithsbruce.griffi...@xtra.co.nz To: Bob Stewartb...@evoria.net; Discussion of precise time and frequency measurementtime-nuts@febo.com Sent: Thursday, February 20, 2014 3:07 AM Subject: Re: [time-nuts] TIC model R2 is dominated by the adc sample switch on resistance and thus has a relatively high tempco (~4000ppm/C). C2 has a relatively low tempco (~100ppm/C or so) To reduce the effect of the sample switch on resistance tempco on the gain tempco of the TIC R1 C1 need to be proportioned so that R2 has little effect on the gain temcpo. R1 = 470 ohm, C1 = 1nF (NPO) appears to be about right for a 2.5MHz synchroniser clock and the PIC you intend to use. This should reduce the effect of the sample switch on resistance tempco by a factor of 10 or more. The minimum value of R1 is governed by the output resistance of the tristate buffer and its tempco. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] TIC model
Hi Bruce, What are the tradeoffs with using different values for R1? I have no practical experience at this, so all I can do is rely on the models. Does the fact that R2 is in the PIC, and C1 is so tiny, make the value of R1 of less importance? On my PIC, they list C1 as 5pf, R2 as effectively about 7K, and C2 120pf. Bob From: Bruce Griffiths bruce.griffi...@xtra.co.nz To: Discussion of precise time and frequency measurement time-nuts@febo.com Sent: Tuesday, February 18, 2014 9:35 PM Subject: Re: [time-nuts] TIC model The attached circuit schematic illustrates how this might be implemented. Faster logic devices can be substituted. R2, C2 approximate the equivalent input circuit of the ADC. R2, C2 values will vary for each ADC. The Shift register which acts as a synchroniser and produces various trigger signals is clocked at 10MHz (assumed to be the uP instruction cycle clock rate) The RC network charge time varies between 1 and 2 shift register clock periods ( ie a charge time from 100ns to 200ns). Sampling a time stamp counter clocked at the same frequency as the shift register is only required if the GPSDO local oscillator has a potential initial offset of 100ppb or more. If missing PPS detection is required then a PPS time stamp counter with a range of several seconds is desirable. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] TIC model
Another variation is to use a single 125 style buffer device (eg 74LVC1G125) to charge and discharge a capacitor (in reality an RC network when the ADC input is taken into account) via a series resistor. The input to the buffer is driven by the input to a conventional synchroniser whilst the buffer output enable is driven by the synchroniser output. The buffer output being enabled whilst the synchroniser output is low (for a 0- 1 PPS input transition) and disabled whenever the synchroniser output is high. This ensures that the capacitor network is discharged to zero between PPS events without requiring an additional device (or a resistor) to discharge the RC network. The capcitor reset level sensitivity to leakage currents is greatly reduced over that when a 1M discharge resistor is used. The nonlinearity can be calibrated by using a statistical fill the buckets technique. This requires a relatively noisy test signal generator (RC oscillator??) to drive the synchroniser input. However its essential to ensure that this oscillator isnt injection locked to the synchroniser clock. Bruce Lars Walenius wrote: Hi Bruce You are absolute right that it is wise to put some time in the estimation of such effects as asynchronous Clocks. An iteration between thinking and building seems always to be necessary but we all have different capabilities for that. For the Arduino I came to an end with the interrupts as I am not good at uP´s. The Arduino GPSDO has two interrupts. One is synchronous with the 10MHz and comes from timer1 overflows. The other is synchronous with the 1PPS. So it is three asynchronous clocks right now in the GPSDO controller. As I understand my problem it is that an interrupt takes some time to execute and if you get the two interrupts to close you will have a problem with timing as you can´t execute both at the same time? Of course the easy solution could be to have the needed resoulution higher than the time it takes to execute the interrupts but in the GPSDO I want a resolution of 200ns (5MHz Clock) and the shortest interrupt is 3us. I would be glad if somebody (Chris?) could have a look in the Aduino GPSDO code to see if it possible to get rid of the uncertainty due to the interrupts from the timer1 overflow. Another question: Does a PIC not need overflow interrupts to count say 500 counts as I do in the Arduino? Lars From: Bruce Griffiths Sent: söndag den 16 februari 2014 20:14 To: time-nuts@febo.com The response time to an external asynchronous interrupt is never deterministic. The external interrupt has to be synchronous with the uP clock to avoid the non deterministic synchronisation delay. Even when the external event is synchronous with the clock input to the uP and the uP uses a divider to produce its internal clock then there is the issue of divider phase shift. This phase shift can lead to sampling the waveform before the peak across the sampling cap. This is far from ideal, its better to sample at or slightly after the peak when the sensitivity to timing variations is far smaller. To complicate the issue further the time of occurrence of the peak is temperature dependent and the sampling switch on resistance is nonlinear so that peak delay varies with temperature and input signal amplitude. Its generally quicker and cheaper to estimate the magnitude of such effects and make appropriate choices than just build a sequence of breadboards each of which then needs to be extensively characterised. Bruce Chris Albertson wrote: You all are inventing problem. Solve them AFTER you find a problem you can measure. Interrupts are not an issue on a UP like the AVR because they are completely deterministic. It don't matter the lenth of time as long as it is 100% deterministic and predictable. On a multi-tasking OS running on a super scaler CPU you have unknowable latentcy but this is not the problem on a chip that does one machine cycle per clock cycle. On Sat, Feb 15, 2014 at 6:50 PM, Brian Lloydbr...@lloyd.com wrote: On Sat, Feb 15, 2014 at 7:10 PM, Tom Van Baakt...@leapsecond.com wrote: For Arduino and other less fortunate uC you can always use external chips to obtain optimal and jitter-free charge/discharge timing. I'm not that familiar with Atmel chips; could capture/compare be used instead of interrupts somehow? One should investigate the Propeller. -- Brian Lloyd, WB6RQN/J79BPL 706 Flightline Drive Spring Branch, TX 78070 br...@lloyd.com +1.916.877.5067 ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and
Re: [time-nuts] TIC model
On Sat, Feb 15, 2014 at 7:10 PM, Tom Van Baak t...@leapsecond.com wrote: For Arduino and other less fortunate uC you can always use external chips to obtain optimal and jitter-free charge/discharge timing. I'm not that familiar with Atmel chips; could capture/compare be used instead of interrupts somehow? One should investigate the Propeller. -- Brian Lloyd, WB6RQN/J79BPL 706 Flightline Drive Spring Branch, TX 78070 br...@lloyd.com +1.916.877.5067 ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] TIC model
You all are inventing problem. Solve them AFTER you find a problem you can measure. Interrupts are not an issue on a UP like the AVR because they are completely deterministic. It don't matter the lenth of time as long as it is 100% deterministic and predictable. On a multi-tasking OS running on a super scaler CPU you have unknowable latentcy but this is not the problem on a chip that does one machine cycle per clock cycle. On Sat, Feb 15, 2014 at 6:50 PM, Brian Lloyd br...@lloyd.com wrote: On Sat, Feb 15, 2014 at 7:10 PM, Tom Van Baak t...@leapsecond.com wrote: For Arduino and other less fortunate uC you can always use external chips to obtain optimal and jitter-free charge/discharge timing. I'm not that familiar with Atmel chips; could capture/compare be used instead of interrupts somehow? One should investigate the Propeller. -- Brian Lloyd, WB6RQN/J79BPL 706 Flightline Drive Spring Branch, TX 78070 br...@lloyd.com +1.916.877.5067 ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. -- Chris Albertson Redondo Beach, California ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] TIC model
The response time to an external asynchronous interrupt is never deterministic. The external interrupt has to be synchronous with the uP clock to avoid the non deterministic synchronisation delay. Even when the external event is synchronous with the clock input to the uP and the uP uses a divider to produce its internal clock then there is the issue of divider phase shift. This phase shift can lead to sampling the waveform before the peak across the sampling cap. This is far from ideal, its better to sample at or slightly after the peak when the sensitivity to timing variations is far smaller. To complicate the issue further the time of occurrence of the peak is temperature dependent and the sampling switch on resistance is nonlinear so that peak delay varies with temperature and input signal amplitude. Its generally quicker and cheaper to estimate the magnitude of such effects and make appropriate choices than just build a sequence of breadboards each of which then needs to be extensively characterised. Bruce Chris Albertson wrote: You all are inventing problem. Solve them AFTER you find a problem you can measure. Interrupts are not an issue on a UP like the AVR because they are completely deterministic. It don't matter the lenth of time as long as it is 100% deterministic and predictable. On a multi-tasking OS running on a super scaler CPU you have unknowable latentcy but this is not the problem on a chip that does one machine cycle per clock cycle. On Sat, Feb 15, 2014 at 6:50 PM, Brian Lloydbr...@lloyd.com wrote: On Sat, Feb 15, 2014 at 7:10 PM, Tom Van Baakt...@leapsecond.com wrote: For Arduino and other less fortunate uC you can always use external chips to obtain optimal and jitter-free charge/discharge timing. I'm not that familiar with Atmel chips; could capture/compare be used instead of interrupts somehow? One should investigate the Propeller. -- Brian Lloyd, WB6RQN/J79BPL 706 Flightline Drive Spring Branch, TX 78070 br...@lloyd.com +1.916.877.5067 ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] TIC model
Hi Bruce You are absolute right that it is wise to put some time in the estimation of such effects as asynchronous Clocks. An iteration between thinking and building seems always to be necessary but we all have different capabilities for that. For the Arduino I came to an end with the interrupts as I am not good at uP´s. The Arduino GPSDO has two interrupts. One is synchronous with the 10MHz and comes from timer1 overflows. The other is synchronous with the 1PPS. So it is three asynchronous clocks right now in the GPSDO controller. As I understand my problem it is that an interrupt takes some time to execute and if you get the two interrupts to close you will have a problem with timing as you can´t execute both at the same time? Of course the easy solution could be to have the needed resoulution higher than the time it takes to execute the interrupts but in the GPSDO I want a resolution of 200ns (5MHz Clock) and the shortest interrupt is 3us. I would be glad if somebody (Chris?) could have a look in the Aduino GPSDO code to see if it possible to get rid of the uncertainty due to the interrupts from the timer1 overflow. Another question: Does a PIC not need overflow interrupts to count say 500 counts as I do in the Arduino? Lars From: Bruce Griffiths Sent: söndag den 16 februari 2014 20:14 To: time-nuts@febo.com The response time to an external asynchronous interrupt is never deterministic. The external interrupt has to be synchronous with the uP clock to avoid the non deterministic synchronisation delay. Even when the external event is synchronous with the clock input to the uP and the uP uses a divider to produce its internal clock then there is the issue of divider phase shift. This phase shift can lead to sampling the waveform before the peak across the sampling cap. This is far from ideal, its better to sample at or slightly after the peak when the sensitivity to timing variations is far smaller. To complicate the issue further the time of occurrence of the peak is temperature dependent and the sampling switch on resistance is nonlinear so that peak delay varies with temperature and input signal amplitude. Its generally quicker and cheaper to estimate the magnitude of such effects and make appropriate choices than just build a sequence of breadboards each of which then needs to be extensively characterised. Bruce Chris Albertson wrote: You all are inventing problem. Solve them AFTER you find a problem you can measure. Interrupts are not an issue on a UP like the AVR because they are completely deterministic. It don't matter the lenth of time as long as it is 100% deterministic and predictable. On a multi-tasking OS running on a super scaler CPU you have unknowable latentcy but this is not the problem on a chip that does one machine cycle per clock cycle. On Sat, Feb 15, 2014 at 6:50 PM, Brian Lloydbr...@lloyd.com wrote: On Sat, Feb 15, 2014 at 7:10 PM, Tom Van Baakt...@leapsecond.com wrote: For Arduino and other less fortunate uC you can always use external chips to obtain optimal and jitter-free charge/discharge timing. I'm not that familiar with Atmel chips; could capture/compare be used instead of interrupts somehow? One should investigate the Propeller. -- Brian Lloyd, WB6RQN/J79BPL 706 Flightline Drive Spring Branch, TX 78070 br...@lloyd.com +1.916.877.5067 ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] TIC model
Another question: Does a PIC not need overflow interrupts to count say 500 counts as I do in the Arduino? Lars, For precision work you must avoid having more than one interrupt. Otherwise there is the chance both will occur at or too near the same time and introduce unexpected latency. There are a couple of solutions. 1) Use a chip with capture h/w so you don't need an interrupt for critical time measurements. 2) Handle timer rollover in software (as in polling) to avoid timer interrupts. 3) Keep track of time with instruction counting instead of an overflowing and interrupting timer. 4) Avoid overflows and interrupts by using time intervals instead of elapsed time. 5) Use a chip with multiple cores with at most one interrupt per core (or a propeller chip with no interrupts at all). The other point to make is interrupt latency. Aside from the sub-cycle h/w synchronization jitter (which is always present) each microcontroller family has a certain number of instruction cycles of latency before your interrupt code executes. In the case of the PIC, this is a fixed number, which is why something like the picPET can be accurate to one cycle. From what I've read the AVR does not have fixed latency, due to its variable- or multi-cycle instructions. Consequently your interrupt handler has both h/w jitter and s/w jitter. To most people this is who-cares. But when you're counting nanoseconds these details matter a lot. Many uC these days have CCP (capture/compare) in h/w, which pushes the problem of timing to bare hardware instead of being tied to instruction timing or interrupts. So if the chip you're using has CCP, by all means use that. That way your 1PPS timing is done in h/w and your s/w only has one timer interrupt to deal with. /tvb ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] TIC model
Tom tried to steer me to the PICTIC recently, and I sort of brushed him off, because, quite frankly I didn't understand. Now that I've really looked at it, it's a much better idea than using a dsPIC33 and brute-forcing it. But, I don't really need everything the PICTIC offers so I started doing surgery, and this is what I've come up with. The nsVolts would feed one of the 10-bit ADC channels of the 18F2220 on the VE2ZAZ board, and the 1PPS signal does the obvious. I had no idea what to use for the RC, so I used smaller and smaller values till LTSpiceIV showed a large range over 360 degrees of phase. I realize that's probably a bad idea, but I have no point of reference, nor do I probably need the accuracy that would otherwise imply. The 1PPS input passes through the enabled tri-state buffers U2A and U2C to charge the cap until the Q output from the D-flop is sent high from the 10MHz signal and disables U2C. When the 1PPS goes low, the cap is discharged and the D-FLop is reset. In practice, the chips would be 74AC types. I could only find LTSpiceIV models for 74HCT chips. LTSpice says it's workable, but in practice, I don't know. It might be finicky or unstable. Any comments would be welcome. http://www.evoria.net/AE6RV/TIC/TIC.png Bob - AE6RV ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] TIC model
Bob Stewart wrote: Tom tried to steer me to the PICTIC recently, and I sort of brushed him off, because, quite frankly I didn't understand. Now that I've really looked at it, it's a much better idea than using a dsPIC33 and brute-forcing it. But, I don't really need everything the PICTIC offers so I started doing surgery, and this is what I've come up with. The nsVolts would feed one of the 10-bit ADC channels of the 18F2220 on the VE2ZAZ board, and the 1PPS signal does the obvious. I had no idea what to use for the RC, so I used smaller and smaller values till LTSpiceIV showed a large range over 360 degrees of phase. I realize that's probably a bad idea, but I have no point of reference, nor do I probably need the accuracy that would otherwise imply. The 1PPS input passes through the enabled tri-state buffers U2A and U2C to charge the cap until the Q output from the D-flop is sent high from the 10MHz signal and disables U2C. When the 1PPS goes low, the cap is discharged and the D-FLop is reset. In practice, the chips would be 74AC types. I could only find LTSpiceIV models for 74HCT chips. LTSpice says it's workable, but in practice, I don't know. It might be finicky or unstable. Any comments would be welcome. http://www.evoria.net/AE6RV/TIC/TIC.png Bob - AE6RV ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. You should also include the effect of the A/D converter sampling capacitance and saampling switch series resistace in the model. Since the RC time constant of the sampling switch and associated sampling capacitor can be 1us or more (temparature and Vcc dependent) the voltage waveform at the sampling capacitor differs significantly from that predicted by your simple modeel. Aside from the nonlinearity due to the non constant charging current the principle limitation on the resolution is due to the variable interrupt latency for ADCs where the conversion is triggered by software. This problem can be avoided if the ADC conversion can be triggered directly by an external signal. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] TIC model
Bob Stewart wrote: Tom tried to steer me to the PICTIC recently, and I sort of brushed him off, because, quite frankly I didn't understand. Now that I've really looked at it, it's a much better idea than using a dsPIC33 and brute-forcing it. But, I don't really need everything the PICTIC offers so I started doing surgery, and this is what I've come up with. The nsVolts would feed one of the 10-bit ADC channels of the 18F2220 on the VE2ZAZ board, and the 1PPS signal does the obvious. I had no idea what to use for the RC, so I used smaller and smaller values till LTSpiceIV showed a large range over 360 degrees of phase. I realize that's probably a bad idea, but I have no point of reference, nor do I probably need the accuracy that would otherwise imply. The 1PPS input passes through the enabled tri-state buffers U2A and U2C to charge the cap until the Q output from the D-flop is sent high from the 10MHz signal and disables U2C. When the 1PPS goes low, the cap is discharged and the D-FLop is reset. In practice, the chips would be 74AC types. I could only find LTSpiceIV models for 74HCT chips. LTSpice says it's workable, but in practice, I don't know. It might be finicky or unstable. Any comments would be welcome. http://www.evoria.net/AE6RV/TIC/TIC.png Bob - AE6RV Bruce Griffiths wrote: You should also include the effect of the A/D converter sampling capacitance and saampling switch series resistace in the model. Since the RC time constant of the sampling switch and associated sampling capacitor can be 1us or more (temparature and Vcc dependent) the voltage waveform at the sampling capacitor differs significantly from that predicted by your simple modeel. Aside from the nonlinearity due to the non constant charging current the principle limitation on the resolution is due to the variable interrupt latency for ADCs where the conversion is triggered by software. This problem can be avoided if the ADC conversion can be triggered directly by an external signal. Bruce What Bruce says is really important. For the ATmega328 the datasheet says 14pF sampling capacitance and nothing about temperature coefficient. It also specifies a series resistance 1..100k. So not very precise. If it is 100k the time constant is 1400ns! I have tested several boards and they seem to behave similar with my 1nF NPO capacitor. With a 47pF I guess it is more uncertain. I also recommend you to test your model in the real world. I have used two good OCXOs and/or rubidiums with a small offset. Say 1E-9 offset that gives 1nS per sec. One of the channels have had a divider for example HC390s or the excellent PICDIVs from Tom Van Baak to output 1PPS. I have also applied a heat gun near the circuit to test that the circuit doesn´t drift with temperature. A reasonable goal is to have less than 1LSB drift with a couple of degrees change. This test I have done with the same source for both 10MHz and 1PPS and a high reading from the ADC. What Bruce says about interrupts is also worth to check in real life as “jitter” due to unexpected interrupts or different timing may give problem. In the Arduino GPSDO the timer1 overflow interrupt may delay the 1PPS interrupt about 3us and delay the ADC conversion 3us. This is not so critical as it sounds as the ADC input is not changing at this time. For me this jitter gives more problem with the timer1 Reading. This jitter is not so easy to to test as it in the Arduino GPSDO program only happens every 1024secs and if you are (un)lucky it may not be seen at all depending on startpoint of timer1 relative to the 1PPS. Lars ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] TIC model
What Bruce says about interrupts is also worth to check in real life as “jitter” due to unexpected interrupts or different timing may give problem. In the Arduino GPSDO the timer1 overflow interrupt may delay the 1PPS interrupt about 3us and delay the ADC conversion 3us. This is not so critical as it sounds as the ADC input is not changing at this time. For me this jitter gives more problem with the timer1 Reading. This jitter is not so easy to to test as it in the Arduino GPSDO program only happens every 1024secs and if you are (un)lucky it may not be seen at all depending on startpoint of timer1 relative to the 1PPS. Lars For those working on microcontroller-based interpolators, you might want to contact Richard McCorkle; I know he has developed a number of other versions since he released the PICTIC II to time-nuts some years ago. One of the reasons he and I and others enjoy working with PIC's is that they have extremely short interrupt latency and no interrupt jitter. Now, I would not recommend anyone switching from Arduino to a PIC, but a working PIC solution may provide an example of what can be done, if nothing else. For Arduino and other less fortunate uC you can always use external chips to obtain optimal and jitter-free charge/discharge timing. I'm not that familiar with Atmel chips; could capture/compare be used instead of interrupts somehow? /tvb ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] TIC model
Hi Lars, I'm lucky in that I'm starting with a PIC running internally at 40MHz. So I think timing is not going to be a real problem. But after getting a response from Richard, I'm concerned about flaws in the spice chip models. I'm also a bit concerned about breadboarding, but come to think of it, in that link you gave me the guy used dead-bug assembly. So maybe that's not a big concern. I suppose the next thing I need to do is experiment with using the ADC to grab the voltage from the incoming 1PPS pulse. Mine stays high for 50ms, so it should be an easy place to start. In fact, there are lot of things I can do with the 1PPS and an RC to get some experience working with the ADC. Bob From: Lars Walenius lars.walen...@hotmail.com To: time-nuts@febo.com time-nuts@febo.com Sent: Saturday, February 15, 2014 5:13 PM Subject: Re: [time-nuts] TIC model What Bruce says is really important. For the ATmega328 the datasheet says 14pF sampling capacitance and nothing about temperature coefficient. It also specifies a series resistance 1..100k. So not very precise. If it is 100k the time constant is 1400ns! I have tested several boards and they seem to behave similar with my 1nF NPO capacitor. With a 47pF I guess it is more uncertain. I also recommend you to test your model in the real world. I have used two good OCXOs and/or rubidiums with a small offset. Say 1E-9 offset that gives 1nS per sec. One of the channels have had a divider for example HC390s or the excellent PICDIVs from Tom Van Baak to output 1PPS. I have also applied a heat gun near the circuit to test that the circuit doesn´t drift with temperature. A reasonable goal is to have less than 1LSB drift with a couple of degrees change. This test I have done with the same source for both 10MHz and 1PPS and a high reading from the ADC. What Bruce says about interrupts is also worth to check in real life as “jitter” due to unexpected interrupts or different timing may give problem. In the Arduino GPSDO the timer1 overflow interrupt may delay the 1PPS interrupt about 3us and delay the ADC conversion 3us. This is not so critical as it sounds as the ADC input is not changing at this time. For me this jitter gives more problem with the timer1 Reading. This jitter is not so easy to to test as it in the Arduino GPSDO program only happens every 1024secs and if you are (un)lucky it may not be seen at all depending on startpoint of timer1 relative to the 1PPS. Lars ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] TIC model
Bob, I have versions of the picPET that capture an ADC reading along with a timestamp. I used this with one of Richard's simpler interpolator designs. There's some info at http://leapsecond.com/pic/picpet2.htm and the projects aren't final yet but you can contact me or Richard directly. /tvb - Original Message - From: Bob Stewart b...@evoria.net To: Discussion of precise time and frequency measurement time-nuts@febo.com Sent: Saturday, February 15, 2014 5:19 PM Subject: Re: [time-nuts] TIC model Hi Lars, I'm lucky in that I'm starting with a PIC running internally at 40MHz. So I think timing is not going to be a real problem. But after getting a response from Richard, I'm concerned about flaws in the spice chip models. I'm also a bit concerned about breadboarding, but come to think of it, in that link you gave me the guy used dead-bug assembly. So maybe that's not a big concern. I suppose the next thing I need to do is experiment with using the ADC to grab the voltage from the incoming 1PPS pulse. Mine stays high for 50ms, so it should be an easy place to start. In fact, there are lot of things I can do with the 1PPS and an RC to get some experience working with the ADC. Bob From: Lars Walenius lars.walen...@hotmail.com To: time-nuts@febo.com time-nuts@febo.com Sent: Saturday, February 15, 2014 5:13 PM Subject: Re: [time-nuts] TIC model What Bruce says is really important. For the ATmega328 the datasheet says 14pF sampling capacitance and nothing about temperature coefficient. It also specifies a series resistance 1..100k. So not very precise. If it is 100k the time constant is 1400ns! I have tested several boards and they seem to behave similar with my 1nF NPO capacitor. With a 47pF I guess it is more uncertain. I also recommend you to test your model in the real world. I have used two good OCXOs and/or rubidiums with a small offset. Say 1E-9 offset that gives 1nS per sec. One of the channels have had a divider for example HC390s or the excellent PICDIVs from Tom Van Baak to output 1PPS. I have also applied a heat gun near the circuit to test that the circuit doesn´t drift with temperature. A reasonable goal is to have less than 1LSB drift with a couple of degrees change. This test I have done with the same source for both 10MHz and 1PPS and a high reading from the ADC. What Bruce says about interrupts is also worth to check in real life as “jitter” due to unexpected interrupts or different timing may give problem. In the Arduino GPSDO the timer1 overflow interrupt may delay the 1PPS interrupt about 3us and delay the ADC conversion 3us. This is not so critical as it sounds as the ADC input is not changing at this time. For me this jitter gives more problem with the timer1 Reading. This jitter is not so easy to to test as it in the Arduino GPSDO program only happens every 1024secs and if you are (un)lucky it may not be seen at all depending on startpoint of timer1 relative to the 1PPS. Lars ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] TIC model
Hi Tom, I appreciate the offer. I may wind up taking you up on it. But, I'm more interested in doing the project than getting an interpolator that works; if you get my meaning. So I'll just plod along at my own speed on this. I may wind up with questions in the future. I'll address them to the list, you, or Richard as seems appropriate, if that's OK. Bob From: Tom Van Baak t...@leapsecond.com To: Discussion of precise time and frequency measurement time-nuts@febo.com Sent: Saturday, February 15, 2014 7:33 PM Subject: Re: [time-nuts] TIC model Bob, I have versions of the picPET that capture an ADC reading along with a timestamp. I used this with one of Richard's simpler interpolator designs. There's some info at http://leapsecond.com/pic/picpet2.htm and the projects aren't final yet but you can contact me or Richard directly. /tvb - Original Message - From: Bob Stewart b...@evoria.net To: Discussion of precise time and frequency measurement time-nuts@febo.com Sent: Saturday, February 15, 2014 5:19 PM Subject: Re: [time-nuts] TIC model Hi Lars, I'm lucky in that I'm starting with a PIC running internally at 40MHz. So I think timing is not going to be a real problem. But after getting a response from Richard, I'm concerned about flaws in the spice chip models. I'm also a bit concerned about breadboarding, but come to think of it, in that link you gave me the guy used dead-bug assembly. So maybe that's not a big concern. I suppose the next thing I need to do is experiment with using the ADC to grab the voltage from the incoming 1PPS pulse. Mine stays high for 50ms, so it should be an easy place to start. In fact, there are lot of things I can do with the 1PPS and an RC to get some experience working with the ADC. Bob From: Lars Walenius lars.walen...@hotmail.com To: time-nuts@febo.com time-nuts@febo.com Sent: Saturday, February 15, 2014 5:13 PM Subject: Re: [time-nuts] TIC model What Bruce says is really important. For the ATmega328 the datasheet says 14pF sampling capacitance and nothing about temperature coefficient. It also specifies a series resistance 1..100k. So not very precise. If it is 100k the time constant is 1400ns! I have tested several boards and they seem to behave similar with my 1nF NPO capacitor. With a 47pF I guess it is more uncertain. I also recommend you to test your model in the real world. I have used two good OCXOs and/or rubidiums with a small offset. Say 1E-9 offset that gives 1nS per sec. One of the channels have had a divider for example HC390s or the excellent PICDIVs from Tom Van Baak to output 1PPS. I have also applied a heat gun near the circuit to test that the circuit doesn´t drift with temperature. A reasonable goal is to have less than 1LSB drift with a couple of degrees change. This test I have done with the same source for both 10MHz and 1PPS and a high reading from the ADC. What Bruce says about interrupts is also worth to check in real life as “jitter” due to unexpected interrupts or different timing may give problem. In the Arduino GPSDO the timer1 overflow interrupt may delay the 1PPS interrupt about 3us and delay the ADC conversion 3us. This is not so critical as it sounds as the ADC input is not changing at this time. For me this jitter gives more problem with the timer1 Reading. This jitter is not so easy to to test as it in the Arduino GPSDO program only happens every 1024secs and if you are (un)lucky it may not be seen at all depending on startpoint of timer1 relative to the 1PPS. Lars ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] TIC model
Rather then trying to model the capacitor why not build a reliable clock and sample the clock before and after the signal you are trying to measure. In other words you calibrate using a (say) 1 uSec pulse. That would cover the case of passive parts aging. On Sat, Feb 15, 2014 at 3:13 PM, Lars Walenius lars.walen...@hotmail.comwrote: Bob Stewart wrote: Tom tried to steer me to the PICTIC recently, and I sort of brushed him off, because, quite frankly I didn't understand. Now that I've really looked at it, it's a much better idea than using a dsPIC33 and brute-forcing it. But, I don't really need everything the PICTIC offers so I started doing surgery, and this is what I've come up with. The nsVolts would feed one of the 10-bit ADC channels of the 18F2220 on the VE2ZAZ board, and the 1PPS signal does the obvious. I had no idea what to use for the RC, so I used smaller and smaller values till LTSpiceIV showed a large range over 360 degrees of phase. I realize that's probably a bad idea, but I have no point of reference, nor do I probably need the accuracy that would otherwise imply. The 1PPS input passes through the enabled tri-state buffers U2A and U2C to charge the cap until the Q output from the D-flop is sent high from the 10MHz signal and disables U2C. When the 1PPS goes low, the cap is discharged and the D-FLop is reset. In practice, the chips would be 74AC types. I could only find LTSpiceIV models for 74HCT chips. LTSpice says it's workable, but in practice, I don't know. It might be finicky or unstable. Any comments would be welcome. http://www.evoria.net/AE6RV/TIC/TIC.png Bob - AE6RV Bruce Griffiths wrote: You should also include the effect of the A/D converter sampling capacitance and saampling switch series resistace in the model. Since the RC time constant of the sampling switch and associated sampling capacitor can be 1us or more (temparature and Vcc dependent) the voltage waveform at the sampling capacitor differs significantly from that predicted by your simple modeel. Aside from the nonlinearity due to the non constant charging current the principle limitation on the resolution is due to the variable interrupt latency for ADCs where the conversion is triggered by software. This problem can be avoided if the ADC conversion can be triggered directly by an external signal. Bruce What Bruce says is really important. For the ATmega328 the datasheet says 14pF sampling capacitance and nothing about temperature coefficient. It also specifies a series resistance 1..100k. So not very precise. If it is 100k the time constant is 1400ns! I have tested several boards and they seem to behave similar with my 1nF NPO capacitor. With a 47pF I guess it is more uncertain. I also recommend you to test your model in the real world. I have used two good OCXOs and/or rubidiums with a small offset. Say 1E-9 offset that gives 1nS per sec. One of the channels have had a divider for example HC390s or the excellent PICDIVs from Tom Van Baak to output 1PPS. I have also applied a heat gun near the circuit to test that the circuit doesn´t drift with temperature. A reasonable goal is to have less than 1LSB drift with a couple of degrees change. This test I have done with the same source for both 10MHz and 1PPS and a high reading from the ADC. What Bruce says about interrupts is also worth to check in real life as jitter due to unexpected interrupts or different timing may give problem. In the Arduino GPSDO the timer1 overflow interrupt may delay the 1PPS interrupt about 3us and delay the ADC conversion 3us. This is not so critical as it sounds as the ADC input is not changing at this time. For me this jitter gives more problem with the timer1 Reading. This jitter is not so easy to to test as it in the Arduino GPSDO program only happens every 1024secs and if you are (un)lucky it may not be seen at all depending on startpoint of timer1 relative to the 1PPS. Lars ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. -- Chris Albertson Redondo Beach, California ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
