On 03/05/2014 08:00 PM, Chin Liang See wrote:
On Wed, 2014-03-05 at 19:47 +0100, Michal Simek wrote:
Hi Pavel,
2014-03-05 17:13 GMT+01:00 Pavel Machek pa...@denx.de:
Hi!
Also I expect that you can change all pins for
uarts/ethernets/spi/i2c/etc
Changes:
1. L2 cache is being invalidated by Boot ROM code for e6500 core.
So removing the invalidation from start.S
2. Clear the LAW and corresponding configuration for CPC. Boot ROM
code uses it as hosekeeping area.
3. For Secure boot, CPC is configured as SRAM and used as house
keeping
In case of secure boot from NAND, the DDR is initialized by the
BootROM using the config words (CF_WORDS) in the CF_HEADER
and u-boot image is copied from NAND to DDR by the BootROM.
So, CONFIG_SYS_RAMBOOT has been defined for Secure Boot from NAND.
Signed-off-by: Aneesh Bansal
Hello Tom, Albert,
It is not clear to me when we should change the board status
from Active to Orphan.
(Could you show me the basic guideline, Tom ? or Albert ?)
There are many boards without maintainers, which are still Active.
This is a known, and so far, open,
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
Changes in v2:
- Split into 2 patches
- Add ARC architecture
README | 5 +
1 file changed, 5 insertions(+)
diff --git a/README b/README
index 2efba4a..0e04964 100644
--- a/README
+++ b/README
@@ -132,6 +132,10 @@ Directory
Commit 54e458de deleted qi_lb60 board support
because of the incompatible license issue.
There is no board with XBurst CPU.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
Cc: Daniel Schwierzeck daniel.schwierz...@gmail.com
---
Changes in v2:
- Split into two patches
README
Hi everyone,
I searched the Internet but the help I found didn't work. I hope someone here
may know how to fix it, here's the situation:
I have this ARM9 SAM9G25 which is accessed by its ttyS0. I
want to disable all of the output, that was made during the U-Boot (v.
2010.06)
boot, to
Hi Heiko,
Heiko Schocher wrote:
Hello Hannes,
Am 06.03.2014 15:24, schrieb Hannes Petermaier:
On 2014-03-06 14:58, Heiko Schocher wrote:
Hello Hannes,
Am 06.03.2014 14:39, schrieb Hannes Petermaier:
- Adds support for a minimal framebuffer driver of TI's AM335x SoC
to be compatible with
Dear colleagues,
Has anyone tried to build NAND SPL support on imx6. Does it work?
Best regards,
Andy
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For Chin Liang See
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
drivers/mtd/nand/denali_nand.c | 42 +++---
drivers/mtd/nand/denali_nand.h | 3 +++
2 files changed, 22 insertions(+), 23 deletions(-)
diff --git a/drivers/mtd/nand/denali_nand.c
Hello Chin,
+/* setups the HW to perform the data DMA */
+static void denali_setup_dma_sequence(int op)
+{
+ const int page_count = 1;
+ uint32_t mode;
+ uint32_t addr = (uint32_t)denali.buf.dma_buf;
+
+ flush_dcache_range(addr, addr + sizeof(denali.buf.dma_buf));
+
+
On Fri, Mar 07, 2014 at 05:38:40PM +0900, Masahiro Yamada wrote:
Hello Tom, Albert,
It is not clear to me when we should change the board status
from Active to Orphan.
(Could you show me the basic guideline, Tom ? or Albert ?)
There are many boards without maintainers,
Hi Tom,
On Thu, 6 Mar 2014 11:22:16 -0500, Tom Rini tr...@ti.com wrote:
On Thu, Mar 06, 2014 at 10:45:22AM -0500, Tom Rini wrote:
Hey,
The following changes since commit cc07294bc704694ae33db75b25ac557e5917a83f:
arm: am335x: DXR2: Reset SMSC LAN9303 switch via GPIO upon bootup
This patch set enables support for device tree on all Exynos4 based boards.
DT support is enabled on Exynos mipi dsim and sdhci drives.
Common board.c file is reused for all functions common for
Exynos4 boards. Board specific files are implemented in the board files.
Origen, Universal, Trats and
This patch adds api to decode peripheral id based on interrupt number.
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
CC: Minkyu Kang mk7.k...@samsung.com
---
Changes for v5:
- none
Changes for v4:
- none
Changes for v3:
- none
This patch adds the new exynos_lcd_misc_init() function for optional
lcd specific initialisation.
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
---
Changes for v5:
- changed the name of
This patch enables parsing mipi data from device tree.
Non device tree case is still supported.
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
---
Changes for v5:
- add exynos_mipi_dsi.txt file with
This patch enables support for device tree for sdhci driver.
Non DT case is still supported.
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
---
Changes for v5:
- none
Changes for v4:
- none
Changes
The checkboard function's implementation is common for all
DT supporting boards and should be placed in the board common file.
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
Cc: Chander Kashyap k.chan...@samsung.com
Cc: Rajeshwari S
This patch adds common dtsi file and config header for all
Exynos 4 based boards.
Patch additionaly adds board specific (weak) functions for
board_early_init_f and board_power_init functions.
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
Signed-off-by: Kyungmin Park
This patch enables sdhci initialisation and misc_init_r in common board
file for all exynos 4 based boards.
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
---
Changes for v5:
- none
Changes for v4:
This patch moves board specific max77686 init function from
common board to smdk5250 board file.
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
Cc: Rajeshwari S Shinde rajeshwar...@samsung.com
Cc: Rajeshwari Birje
This patch enables to run Origen board on device tree.
Uart, DRAM and MMC init functions are removed as their
generic replacements form the common board file are used.
The config file is modified to contain only board specific options.
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
This patch enables to run Trats board on device tree.
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
CC: Minkyu Kang mk7.k...@samsung.com
CC: Lukasz Majewski l.majew...@samsung.com
---
Changes for v5:
- changed the name of
This patch enables to run Universal board on device tree.
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
Acked-by: Przemyslaw Marczak p.marc...@samsung.com
---
Changes for v5:
- changed the name of
This patch enables to run Trats2 board on device tree.
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
CC: Minkyu Kang mk7.k...@samsung.com
---
Changes for v5:
- changed the name of exynos_lcd_panel_init to exynos_lcd_misc_init
Changes
Hi Tom,
On Thu, 6 Mar 2014 08:39:32 -0700, Tom Warren
twarren.nvi...@gmail.com wrote:
Albert,
Please pull u-boot-tegra/master into ARM/master. Thanks!
./MAKEALL -s tegra AOK, checkpatch.pl is clean, and ./MAKEALL -a arm only
shows failures that were already present in ARM/master.
The
Hi Michal,
On Fri, 2014-03-07 at 09:12 +0100, Michal Simek wrote:
On 03/05/2014 08:00 PM, Chin Liang See wrote:
On Wed, 2014-03-05 at 19:47 +0100, Michal Simek wrote:
Hi Pavel,
2014-03-05 17:13 GMT+01:00 Pavel Machek pa...@denx.de:
Hi!
Also I expect that
Hi Masahiro,
On Fri, 2014-03-07 at 21:58 +0900, Masahiro Yamada wrote:
Hello Chin,
+/* setups the HW to perform the data DMA */
+static void denali_setup_dma_sequence(int op)
+{
+ const int page_count = 1;
+ uint32_t mode;
+ uint32_t addr = (uint32_t)denali.buf.dma_buf;
+
Hi Tom,
[snip]
+ fdt_high=0x\0 \
Please don't do this, set it to the top of kernel low mem.
The EVM may have up to 8GB of DDR and u-boot can see the first 2GB
with physical address range 0x8000-0x.
If we don't use the
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 03/07/2014 11:41 AM, Andrianov, Vitaly wrote:
Hi Tom,
[snip]
+ fdt_high=0x\0 \
Please don't do this, set it to the top of kernel low mem.
The EVM may have up to 8GB of DDR and u-boot can
This patch removes following two functions:
- lcd_getbgcolor(...)
not used somewhere outside lcd.c, internally we use now the global
variable lcd_color_bg (was return value of function before)
- lcd_getfgcolor(...)
not used in any place of u-boot
Signed-off-by: Hannes Petermaier
- Adds support for 32-bit organized framebuffers to the LCD-framework.
Signed-off-by: Hannes Petermaier oe5...@oevsv.at
Cc: ag...@denx.de
---
Changes for v2:
- separated from 'function-cleanup' changes
---
common/lcd.c | 35 ---
include/lcd.h | 17
- fix: return-value of 'i2c_set_bus_speed' was interpreted wrong
Signed-off-by: Hannes Petermaier oe5...@oevsv.at
---
board/BuR/kwb/board.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/BuR/kwb/board.c b/board/BuR/kwb/board.c
index 8aa16bc..8fb5e68 100644
---
Hi Ian ..
You would have a repository with these updates where I could play with git,
compile and test my cubieboard2 using kernel 3.14.rc5
I'm waiting! to test your boot!
thank you
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On 03/07/2014 05:23 AM, Aneesh Bansal wrote:
Changes:
1. L2 cache is being invalidated by Boot ROM code for e6500 core.
So removing the invalidation from start.S
2. Clear the LAW and corresponding configuration for CPC. Boot ROM
code uses it as hosekeeping area.
3. For Secure boot, CPC
On Fri, 2014-03-07 at 18:53 +0530, Aneesh Bansal wrote:
Changes:
1. L2 cache is being invalidated by Boot ROM code for e6500 core.
So removing the invalidation from start.S
2. Clear the LAW and corresponding configuration for CPC. Boot ROM
code uses it as hosekeeping area.
3. For
On Fri, 2014-03-07 at 10:30 -0800, York Sun wrote:
On 03/07/2014 05:23 AM, Aneesh Bansal wrote:
Changes:
1. L2 cache is being invalidated by Boot ROM code for e6500 core.
So removing the invalidation from start.S
2. Clear the LAW and corresponding configuration for CPC. Boot ROM
Hi,
Thanks for your time,
Please find following comments:
1. Current solution (u-boot):
- It is possible to specify your own dfu_alt_info environment
variable when you call dfu command.
2. Speed improvement - section Making it faster from:
On Thu, 2014-03-06 at 03:24 -0600, Bansal Aneesh-B39320 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Wednesday, March 05, 2014 11:30 PM
To: Bansal Aneesh-B39320
Cc: Sun York-R58495; Wolfgang Denk; u-boot@lists.denx.de; Gupta
Ruchika-R66431
Subject: Re: [U-Boot]
On 03/07/2014 10:54 AM, Scott Wood wrote:
On Fri, 2014-03-07 at 10:30 -0800, York Sun wrote:
On 03/07/2014 05:23 AM, Aneesh Bansal wrote:
Changes:
1. L2 cache is being invalidated by Boot ROM code for e6500 core.
So removing the invalidation from start.S
2. Clear the LAW and corresponding
On Fri, 2014-03-07 at 10:58 -0800, York Sun wrote:
On 03/07/2014 10:54 AM, Scott Wood wrote:
On Fri, 2014-03-07 at 10:30 -0800, York Sun wrote:
On 03/07/2014 05:23 AM, Aneesh Bansal wrote:
Changes:
1. L2 cache is being invalidated by Boot ROM code for e6500 core.
So removing the
On 03/07/2014 10:57 AM, Scott Wood wrote:
On Thu, 2014-03-06 at 03:24 -0600, Bansal Aneesh-B39320 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Wednesday, March 05, 2014 11:30 PM
To: Bansal Aneesh-B39320
Cc: Sun York-R58495; Wolfgang Denk; u-boot@lists.denx.de; Gupta
On 03/07/2014 11:00 AM, Scott Wood wrote:
On Fri, 2014-03-07 at 10:58 -0800, York Sun wrote:
On 03/07/2014 10:54 AM, Scott Wood wrote:
On Fri, 2014-03-07 at 10:30 -0800, York Sun wrote:
On 03/07/2014 05:23 AM, Aneesh Bansal wrote:
Changes:
1. L2 cache is being invalidated by Boot ROM code
On 02/28/2014 12:48 AM, Prabhakar Kushwaha wrote:
With the default value of MDIO_CLK_DIV generatee MDC is too high and It is
violating the IEEE specs much higher than 2.5Mhz.
Although there is errata(A-006260) for EMI2(MDIO2), but same errata is
been hit on EMI1(MDIO1). unfortunately this
On 02/27/2014 06:22 PM, Prabhakar Kushwaha wrote:
T1040RDB and T1042RDB_PI has CPLD. Here CPLD controls board mux/features.
This support of CPLD includes
- files and register defintion
- Commands to swtich alternate bank and default bank
Signed-off-by: Prabhakar Kushwaha
On Wed, Mar 5, 2014 at 3:22 AM, Stefano Babic sba...@denx.de wrote:
Hi Tim,
On 05/03/2014 12:06, Stefano Babic wrote:
On 13/02/2014 08:48, Tim Harvey wrote:
Gateworks Ventana is a product family based on the i.MX6. This
patch adds support for all boards in the Ventana family. Where
[snip]
+Build instructions:
+===
+
+To build u-boot.bin
+ make k2hk_evm_config
+ make u-boot-spi.gph
+
+To build u-boot-spi.gph
+ make k2hk_evm_config
+ make u-boot-spi.gph
We need to use CONFIG_SPL_TARGET so that make all just works.
I am assuming we need to do
#define
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 03/07/2014 04:21 PM, Murali Karicheri wrote:
[snip]
+Build instructions:
+===
+
+To build u-boot.bin
+ make k2hk_evm_config
+ make u-boot-spi.gph
+
+To build u-boot-spi.gph
+ make k2hk_evm_config
+ make u-boot-spi.gph
On 03/03/2014 12:58 AM, Shaveta Leekha wrote:
Most of the I2C slaves support accesses in the typical style
viz.read/write series of bytes at particular address offset.
These transactions are currently supportd in the
i2c driver using i2c_read and i2c_write APIs. I2C EEPROMs,
RTC, etc fall in
Hi Masahiro,
On 5 March 2014 00:59, Masahiro Yamada yamad...@jp.panasonic.com wrote:
Many (but not all) of Blackfin boards give -O2 option
to compile under lib/ directory.
That means lib/ should be speed-optimized,
whereas other parts should be size-optimized.
We want to keep the same
On 5 March 2014 00:59, Masahiro Yamada yamad...@jp.panasonic.com wrote:
Before this commit, USE_PRIVATE_LIBGCC was defined in
arch-specific config.mk and referenced in
arch/$(ARCH)/lib/Makefile.
We are not happy about parsing config.mk again and again.
We have to keep the same behavior with
On 5 March 2014 00:59, Masahiro Yamada yamad...@jp.panasonic.com wrote:
We want to change the build system to include config.mk
only from ./Makefile and spl/Makefile.
We must prepare for that in this commit.
$(src) is a moving target and not handy for our purpose.
We must replace it with a
On 5 March 2014 01:49, Masahiro Yamada yamad...@jp.panasonic.com wrote:
checkthumb makes sense only for ARM architecture.
Move it to arch/arm/config.mk.
To make sure gcc supports THUMB mode before beginning build,
run checkthumb during archprepare.
Signed-off-by: Masahiro Yamada
On 5 March 2014 01:49, Masahiro Yamada yamad...@jp.panasonic.com wrote:
checkgcc4 is used only for PowerPC.
Move it to arch/powerpc/config.mk.
To make sure gcc is new enough before beginning build,
run checkgcc4 during archprepare.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
On Sat, Mar 01, 2014 at 10:16:10PM -0700, Stephen Warren wrote:
The following shell command fails:
if test -z $x; then echo zero; else echo non-zero; fi
(assuming $x does not exist, it prints non-zero rather than zero).
... since $x expands to nothing, and the argument is completely
On Wed, Mar 05, 2014 at 04:59:38PM +0900, Masahiro Yamada wrote:
Before this commit, USE_PRIVATE_LIBGCC was defined in
arch-specific config.mk and referenced in
arch/$(ARCH)/lib/Makefile.
We are not happy about parsing config.mk again and again.
We have to keep the same behavior with a
On Wed, Mar 05, 2014 at 04:59:39PM +0900, Masahiro Yamada wrote:
We want to change the build system to include config.mk
only from ./Makefile and spl/Makefile.
We must prepare for that in this commit.
$(src) is a moving target and not handy for our purpose.
We must replace it with a fixed
On Wed, Mar 05, 2014 at 05:49:23PM +0900, Masahiro Yamada wrote:
checkgcc4 is used only for PowerPC.
Move it to arch/powerpc/config.mk.
To make sure gcc is new enough before beginning build,
run checkgcc4 during archprepare.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
On Wed, Mar 05, 2014 at 05:25:37PM +0900, Masahiro Yamada wrote:
All mips32 boards define CONFIG_MIPS32 in config headers
except malta boards which define it in boards.cfg.
We can consolidate them by defining it in
arch/mips/cpu/mips32/config.mk.
CONFIG_MIPS64 definition can be moved to
On Wed, Mar 05, 2014 at 05:49:22PM +0900, Masahiro Yamada wrote:
checkthumb makes sense only for ARM architecture.
Move it to arch/arm/config.mk.
To make sure gcc supports THUMB mode before beginning build,
run checkthumb during archprepare.
Signed-off-by: Masahiro Yamada
On Tue, Mar 04, 2014 at 05:24:09PM +0200, Vasili Galka wrote:
From: Vasili Galka vvv...@gmail.com
Signed-off-by: Vasili Galka vas...@visionmap.com
Applied to u-boot/master, thanks!
--
Tom
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On Wed, Mar 05, 2014 at 05:40:10PM +0900, Masahiro Yamada wrote:
Before this commit, CONFIG_MPC8260 and CONFIG_8260
were used mixed-up.
All boards with mpc8260 cpu defined both of them:
- CONFIG_MPC8260 was defined in board config headers
and include/common.h
- CONFIG_8260 was
On Tue, Mar 04, 2014 at 03:56:12PM +0800, Haijun.Zhang wrote:
There was wrong phy_mask for AR8021 device,
so the AR8021 can't be probed correctly.
Changed it from 0x4f to 0x40.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
Applied to u-boot/master, thanks!
--
Tom
On Tue, Mar 04, 2014 at 03:34:35PM +0100, Stefan Roese wrote:
As ppc4xx currently only supports the deprecated nand_spl infrastructure
and nobody seems to have time / resources to port this over to the newer
SPL infrastructure, lets remove NAND booting completely.
This should not affect the
On Tue, Mar 04, 2014 at 03:52:35PM -0500, Tom Rini wrote:
When importing a checksummed area we need to be told how big the area in
question is so that we know that will match the size of the area which
the checksum is generated against.
Reported-by: Pierre AUBERT p.aub...@staubli.com
On Wed, Mar 05, 2014 at 04:59:37PM +0900, Masahiro Yamada wrote:
Many (but not all) of Blackfin boards give -O2 option
to compile under lib/ directory.
That means lib/ should be speed-optimized,
whereas other parts should be size-optimized.
We want to keep the same behavior,
but do not
On Wed, Mar 05, 2014 at 04:59:40PM +0900, Masahiro Yamada wrote:
Kbuild brought about many advantages for us but a significant
performance regression was reported by Simon Glass.
After some discussions and analysis, it turned out
its main cause is in $(call cc-option,...).
Historically,
On Tue, Mar 04, 2014 at 11:36:51AM +0900, Masahiro Yamada wrote:
config.tmp is never generated
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
Cc: Michal Simek michal.si...@xilinx.com
Acked-by: Michal Simek michal.si...@xilinx.com
Applied to u-boot/master, thanks!
--
Tom
On Thu, Feb 27, 2014 at 10:01:28PM -0700, Stephen Warren wrote:
Delete the temporary variables that are used to save unit-test results
from the environment after running the test. This prevents polluting
the environment, or growing it too much.
Signed-off-by: Stephen Warren
On Sat, Mar 01, 2014 at 10:18:00PM -0700, Stephen Warren wrote:
The unit-test for hush's test -e currently relies upon being run in
the U-Boot build directory, because it tests for the existence of a file
that exists in that directory.
Fix this by explicitly creating the file we use for the
On Thu, Feb 27, 2014 at 01:27:02PM -0700, Stephen Warren wrote:
From: Stephen Warren swar...@nvidia.com
For Ethernet/USB RX packets, the ASIX HW pads odd-sized packets so that
they have an even size. Currently, asix_recv() does remove this padding,
and asic_send() adds equivalent padding in
On 02/17/2014 07:28 PM, Zhao Qiang wrote:
CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address.
Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address,
and CONFIG_SYS_QE_FW_ADDR for QE microcode address.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
On 02/26/2014 02:36 AM, Shaveta Leekha wrote:
1) SerDes2 Refclks have been set properly to make
PCIe SATA to work as it work on SerDes refclk of 100MHz
2) Mask the SerDes's device reset request before changing
the Refclks for SerDes1 and SerDes2 for PLL locks to
happen
On 02/26/2014 02:36 AM, Shaveta Leekha wrote:
1) Add new SerDes1 protocols having Aurora in them
2) Add VSC cross point connections for Aurora to work with
CPRI and SGMIIs
3) Configure VSC crossbar switch to connect SerDes1
lanes to aurora on board, by checking SerDes1 protocols
4)
On 02/16/2014 07:08 PM, Poonam Aggrwal wrote:
On B4860 and B4420, some serdes protocols can be used with LC VCO as
well as Ring VCO options.
Addded Alternate options with LC VCO for such protocols.
For example protocol 0x2a on srds 1 becomes 0x29 if it is LC VCO.
The alternate option has
On 02/26/2014 02:37 AM, Shaveta Leekha wrote:
- B4860 has two PLL per SerDes whereas B4420 has one PLL
per SerDes, add their defines in
arch/powerpc/include/asm/config_mpc85xx.h
Signed-off-by: Shaveta Leekha shav...@freescale.com
---
Applied to u-boot-mpc85xx/master.
On 02/26/2014 02:37 AM, Shaveta Leekha wrote:
- Change setting of SerDes2 refclk2 to have the default value
as it is coming on board that is 156.25MHz, for XFI to work
- Also change PLL_NUM variable to the one defined in
config_mpc85xx.h for B4860 and B4420
Signed-off-by:
On 02/26/2014 02:38 AM, Shaveta Leekha wrote:
SerDes PLLs may not lock reliably at 5 G VCO configuration(A006384)
and at cold temperatures(A006475), workaround recalibrate the
PLLs with some SerDes configuration
Both these errata are only applicable for b4 rev1.
So, make workaround for
On 02/26/2014 12:59 AM, Suresh Gupta wrote:
USB spec says that the minimum disconnect threshold should be
over 525 mV. However, internal USB PHY threshold value is below
this specified value. Due to this some devices disconnect at
run-time. Hence, phy settings are
On 03/05/2014 11:07 PM, Shengzhou Liu wrote:
- change QIXIS timing parameter CONFIG_SYS_CS3_FTIM2 to 8 from 0.
- fix EMI2 for t2080qds, which was caused by adding t2081qds.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
Applied to u-boot-mpc85xx/master. Thanks.
York
On 02/19/2014 07:16 AM, Rommel G Custodio wrote:
This implements stashing of bootstage timing data to FDT and automatic
timing reporting. To enable define CONFIG_BOOTSTAGE_FDT and
CONFIG_BOOTSTAGE_REPORT respectively.
Signed-off-by: Rommel G Custodio sessyargc+u-b...@gmail.com
---
Applied
On 03/04/2014 11:04 PM, Shengzhou Liu wrote:
T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC.
It works in two mode: standalone mode and PCIe endpoint mode.
T2080PCIe-RDB Feature Overview
--
Processor:
- T2080 SoC integrating four
On 01/30/2014 02:09 AM, Priyanka Jain wrote:
T1040 SoC has SCFG (Supplement Configuration) Block which provides
chip specific configuration and status support. The base address of
SCFG block in T1040 is 0xfc000.
SCFG contains SCFG_PIXCLKCR (DIU pixel clock control register)
at offset 0x28.
On 02/26/2014 02:41 AM, Priyanka Jain wrote:
T1040 has internal display interface unit (DIU) for driving video.
T1040QDS supports video mode via
-LCD using TI enconder
-HDMI type interface via HDMI encoder
Chrontel, CH7301C encoder which is I2C programmable is used as
HDMI connector on
On 02/25/2014 08:08 PM, Priyanka Jain wrote:
Update following DDR related settings for T1040RDB, T1042RDB_PI
-Correct number of chip selects to two as t1040 supports
two Chip selects.
-Update board_specific_parameters udimm structure with settings
derived via calibration.
-Update
Tom,
The following changes since commit e4b87e5b1d026bd010e2ba3abbf89561e8320287:
Merge branch 'master' of git://git.denx.de/u-boot-nand-flash (2014-03-04
21:23:42 -0500)
are available in the git repository at:
git://git.denx.de/u-boot-mpc85xx.git master
for you to fetch changes up to
On Fri, Mar 07, 2014 at 03:09:23PM -0800, York Sun wrote:
Tom,
The following changes since commit e4b87e5b1d026bd010e2ba3abbf89561e8320287:
Merge branch 'master' of git://git.denx.de/u-boot-nand-flash (2014-03-04
21:23:42 -0500)
are available in the git repository at:
On Fri, 2014-03-07 at 08:44 -0800, Ezaul Zillmer wrote:
You would have a repository with these updates where I could play with
git,
compile and test my cubieboard2 using kernel 3.14.rc5
git://gitorious.org/ijc/u-boot.git ahci-sunxi
It is based on jwrdegoede/sunxi-next.
Ian.
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