Hi Gabriel,
On Thu, Feb 26, 2015 at 12:27 AM, Gabriel Huau cont...@huau-gabriel.fr wrote:
Hi Bin,
On 02/24/2015 11:52 PM, Bin Meng wrote:
Hi Gabriel,
On Mon, Feb 16, 2015 at 5:55 AM, Gabriel Huau cont...@huau-gabriel.fr
wrote:
Configure the pinctrl as it required to make some IO
On Thu, 2015-02-26 at 22:35 -0600, Bansal Aneesh-B39320 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Thursday, February 26, 2015 3:43 AM
To: Bansal Aneesh-B39320
Cc: u-boot@lists.denx.de; Sun York-R58495; Gupta Ruchika-R66431
Subject: Re: [U-Boot, 1/2, v4]
Hi Gabriel,
On Thu, Feb 26, 2015 at 12:27 AM, Gabriel Huau cont...@huau-gabriel.fr wrote:
Hi Bin,
On 02/24/2015 11:52 PM, Bin Meng wrote:
Hi Gabriel,
On Mon, Feb 16, 2015 at 5:55 AM, Gabriel Huau cont...@huau-gabriel.fr
wrote:
Configure the pinctrl as it required to make some IO
Hi Bin,
On 02/26/2015 07:30 PM, Bin Meng wrote:
Hi Gabriel,
On Thu, Feb 26, 2015 at 12:27 AM, Gabriel Huau cont...@huau-gabriel.fr wrote:
Hi Bin,
On 02/24/2015 11:52 PM, Bin Meng wrote:
Hi Gabriel,
On Mon, Feb 16, 2015 at 5:55 AM, Gabriel Huau cont...@huau-gabriel.fr
wrote:
Configure the
1. esbc_validate command is meant for validating header and
signature of images (Boot Script and ESBC uboot client).
SHA-256 and RSA operations are performed using SEC block in HW.
This command works on both PBL based and Non PBL based Freescale
platforms.
Freescale sfp has been used for mpc8xxx. It will be used
for ARM-based SoC as well. This patch moves the CCSR defintion of
sfp_regs to common include.
This patch also defines ccsr_sfp_regs definition for newer
versions of SFP.
Signed-off-by: Ruchika Gupta
The Security Monitor is the SOC’s central reporting point for
security-relevant events such as the success or failure of boot
software validation and the detection of potential security compromises.
The API's for transition of Security states have been added
which will be used in case of SECURE
On Thu, Feb 26, 2015 at 9:19 PM, Nikolay Dimitrov picmas...@mail.bg wrote:
Hi Otavio,
On 02/26/2015 11:02 PM, Otavio Salvador wrote:
On Thu, Feb 26, 2015 at 4:58 PM, Fabio Estevam
fabio.este...@freescale.com wrote:
Add EXT4 support.
Signed-off-by: Fabio Estevam
Hi,
On 02/24/2015 09:02 AM, Michal Simek wrote:
Add basic Xilinx ZynqMP arm64 support.
Serial and SD is supported.
It supports emulation platfrom ep108 and QEMU.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
MAINTAINERS | 6 ++
Hi Dave,
On Thu, Feb 26, 2015 at 9:05 PM, DaveKucharczyk
david.kucharc...@gmail.com wrote:
I would like to debug from the earliest possible point pre-relocation (for
educational reasons). Couple questions
In the Makefile, where do I place the following flags...
-Os #-fomit-frame-pointer
-Original Message-
From: Wood Scott-B07421
Sent: Thursday, February 26, 2015 3:43 AM
To: Bansal Aneesh-B39320
Cc: u-boot@lists.denx.de; Sun York-R58495; Gupta Ruchika-R66431
Subject: Re: [U-Boot, 1/2, v4] powerpc/mpc85xx: SECURE BOOT- NAND
secure boot target for P3041
[Reposting
Hi Dave,
On Thu, Feb 26, 2015 at 3:19 PM, DaveKucharczyk
david.kucharc...@gmail.com wrote:
Benoît Thébaudeau-2 wrote
Also, check the CONFIG_SYS_TEXT_BASE of your board. From your log, I'm
wondering if it's not set too high, resulting in an overlap of the
pre- and post-relocation addresses
I think I've been able to narrow down, a bit, where the issue is coming from.
mmc_set_blocklen led me to mmc_send_cmd which showed that there is
the CONFIG_MMC_TRACE I could use.
A notable difference between hardkernel's u-boot and mainline was the
uint flags; was no longer in the mmc_cmd
Hi Albert,
On Thu, Feb 26, 2015 at 11:38 AM, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
Hello Benoît,
On Thu, 26 Feb 2015 00:56:00 +0100, Benoît Thébaudeau
benoit.thebaudeau@gmail.com wrote:
Dear Dave Kucharczyk,
On Wed, Feb 25, 2015 at 11:08 PM, DaveKucharczyk
esbc_validate command uses various IP Blocks: Security Monitor, CAAM block
and SFP registers. Hence the respective CONFIG's are enabled.
Apart from these CONFIG_SHA_PROG_HW_ACCEL and CONFIG_RSA are also enabled.
Signed-off-by: Gaurav Rana gaurav.r...@freescale.com
---
Changes in v3:
No change.
-Original Message-
From: Wood Scott-B07421
Sent: Friday, February 27, 2015 10:22 AM
To: Bansal Aneesh-B39320
Cc: u-boot@lists.denx.de; Sun York-R58495; Gupta Ruchika-R66431
Subject: Re: [U-Boot, 1/2, v4] powerpc/mpc85xx: SECURE BOOT- NAND
secure boot target for P3041
On Thu,
Remove dependency of rsa_mod_exp from CONFIG_FIT_SIGNATURE.
As rsa modular exponentiation is an independent module
and can be invoked independently.
Signed-off-by: Gaurav Rana gaurav.r...@freescale.com
Reviewed-by: Simon Glass s...@chromium.org
CC: Simon Glass s...@chromium.org
---
Changes in v2:
Hi Otavio,
On 02/26/2015 11:02 PM, Otavio Salvador wrote:
On Thu, Feb 26, 2015 at 4:58 PM, Fabio Estevam
fabio.este...@freescale.com wrote:
Add EXT4 support.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
Acked-by: Otavio Salvador ota...@ossystems.com.br
And sorry for not notice
Hi,
On 26-02-15 12:08, Gábor Nyers wrote:
The Jesurun Q5 has a black plastic casing with the approximate dimensions of
100mm x 100mm x 24mm with rounded edges. In terms of hardware it features an
Allwinner A10 SoC with 1GB RAM and 8GB of NAND flash. The storage capacity can
be extended up to
Add EXT2/EXT4 and BOUNCE_BUFFER support.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
Changes since v1:
- Newly introduced in this series
include/configs/mx6sabre_common.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/configs/mx6sabre_common.h
On Thu, 26 Feb 2015 08:50:09 -0600
Nishanth Menon n...@ti.com wrote:
On Thu, Feb 26, 2015 at 1:40 AM, Siarhei Siamashka
siarhei.siamas...@gmail.com wrote:
On Wed, 25 Feb 2015 14:55:08 -0600
Nishanth Menon n...@ti.com wrote:
Hi,
The third incarnation of this series to address various
Hi,
I am trying to display a BMP image on a Samsung Chromebook (snow), but I get
wrong colors. The image is displayed but colors are bad.
I used my own image and images provided in tools/logos/ folder, thay are all ok
on the Sabrelite board (HDMI output) but displayed in bad colors on the
User Mass Storage is very useful for flashing the on-board eMMC.
Add support for it.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
Changes since v1:
- Remove EXT2/EXT4 and BOUNCE_BUFFER support
include/configs/mx6sabre_common.h | 14 ++
1 file changed, 14
On Tue, 24 Feb 2015 12:25:50 -0700
Stephen Warren swar...@wwwdotorg.org wrote:
On 02/24/2015 10:41 AM, Alban Bedel wrote:
On Tue, 24 Feb 2015 10:00:43 -0700
Stephen Warren swar...@wwwdotorg.org wrote:
On 02/24/2015 09:44 AM, Alban Bedel wrote:
Older controllers don't implement Device
On Thu, Feb 26, 2015 at 1:40 AM, Siarhei Siamashka
siarhei.siamas...@gmail.com wrote:
On Wed, 25 Feb 2015 14:55:08 -0600
Nishanth Menon n...@ti.com wrote:
Hi,
The third incarnation of this series to address various ideas of
previous V2 series. I will skip the full blurb and point to V1/V2
Hi Marco,
On Mon, Feb 23, 2015 at 11:34 AM, Marco Cavallini
m.cavall...@koansoftware.com wrote:
Please provide a commit log.
Signed-off-by: Marco Cavallini m.cavall...@koansoftware.com
---
arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 18 ++
1 file changed, 18
hi Mark,
You did very detailed analysis of the cache beheaviour. Yes, this patch
is not perfect.
But it did fix the actually existed bug. I will try to describe it more clearly
in the following.
-Original Messages-
From: Mark Rutland mark.rutl...@arm.com
Sent Time: 2015-02-11
Hi Albert,
On 26 February 2015 at 03:34, Albert ARIBAUD albert.u.b...@aribaud.net wrote:
Hello Albert,
On Wed, 25 Feb 2015 21:57:36 +0100, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
Hello Simon,
On Wed, 25 Feb 2015 07:00:23 -0700, Simon Glass s...@chromium.org
wrote:
Hi Albert,
Benoît Thébaudeau-2 wrote
Also, check the CONFIG_SYS_TEXT_BASE of your board. From your log, I'm
wondering if it's not set too high, resulting in an overlap of the
pre- and post-relocation addresses occupied by your binary in the
256-MiB case.
BINGO!!! Good catch Benoît, thank you. I changed
2015-02-26 11:17 GMT+01:00 Paul Burton paul.bur...@imgtec.com:
On Thu, Feb 19, 2015 at 01:50:23PM +, Matthew Fortune wrote:
Hi Daniel,
The spec for MIPS Unified Hosting Interface is available here:
http://prplfoundation.org/wiki/MIPS_documentation
As we have previously discussed, this
Hello Simon,
On Thu, 26 Feb 2015 08:57:05 -0700, Simon Glass s...@chromium.org
wrote:
Hi Albert,
On 26 February 2015 at 03:34, Albert ARIBAUD albert.u.b...@aribaud.net
wrote:
Hello Albert,
On Wed, 25 Feb 2015 21:57:36 +0100, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
Hello
Hi Albert,
On 26 February 2015 at 10:06, Albert ARIBAUD albert.u.b...@aribaud.net wrote:
Hello Simon,
On Thu, 26 Feb 2015 08:57:05 -0700, Simon Glass s...@chromium.org
wrote:
Hi Albert,
On 26 February 2015 at 03:34, Albert ARIBAUD albert.u.b...@aribaud.net
wrote:
Hello Albert,
On
Follow the register macros in the LSI specification book.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
Changes in v5:
- Newly added
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/mach-uniphier/include/mach/sc-regs.h| 12 ++--
Deassert the reset signal and provide the clock for STDMAC core.
This is necessary for the USB 2.0 host controllers.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
Changes in v5:
- Newly added
Changes in v4: None
Changes in v3: None
Changes in v2: None
configs/ph1_ld4_defconfig | 18 +-
configs/ph1_pro4_defconfig | 18 +-
configs/ph1_sld8_defconfig | 18
Since commit 0e7368c6c426 (kbuild: prepare for moving headers into
mach-*/include/mach), we can replace #include asm/arch/*.h with
mach/*.h so we do not need to create the symbolic link during the
build.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
Changes in v5: None
Changes in
Move
arch/arm/cpu/armv7/uniphier/* - arch/arm/mach-uniphier/*
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
Changes in v5: None
Changes in v4: None
Changes in v3:
- Newly added
Changes in v2: None
MAINTAINERS | 2 +-
Now UniPhier SoCs only work with CONFIG_SPL and the function
sbc_init() is called from SPL.
The conditional #if !defined(CONFIG_SPL_BUILD) has no point
any more.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/mach-uniphier/ph1-pro4/sbc_init.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
This is already set up in crt0.S. We don't need a new structure and don't
really want one in the 'data' section of the image, since it will be empty
and crt0.S's changes will be ignored.
As an interim measure, remove it only if CONFIG_DM is not defined. This
allows us to press ahead with driver
Because uniphier_ehci_reset() is only called from ehci-uniphier.c,
it can be a static function there.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
Acked-by: Marek Vasut ma...@denx.de
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
My main motivations for this commit are:
[1] Follow the arch/arm/Makefile style of Linux Kernel
[2] Maintain compiler options systematically
Currently, we give -march=* and -mtune=* options inconsistently:
Only some of the CPUs pass -march=* and -mtune=* options.
By collecting such options
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
Changes in v5:
- Newly added
Changes in v4: None
Changes in v3: None
Changes in v2: None
Kconfig| 2 +-
arch/arm/mach-uniphier/Kconfig | 3 +++
include/configs/uniphier.h | 2 --
3 files changed, 4
Now UniPhier platform highly depends on Device Tree configuration
(CONFIG_OF_CONTROL is select'ed by Kconfig). Since the EHCI is only
used on main U-Boot, we can drop platform devices of the EHCI
controllers. We still keep UART platform devices because they might
be useful for SPL.
This series includes a few more patches aimed at getting rid of gdata, the
parallel global_data structure introduced on some ARM boards.
It also collects together the other patches which have been sent previously,
so that everything is in one place.
I would like get this agreed and applied to
Each way of the system cache has 256 entries for PH1-Pro4 and older
SoCs, whereas 512 entries for PH1-Pro5 and newer SoCs. The line
size is still 128 byte. Thus, the way size is 32KB/64KB for old/new
SoCs.
To keep lowlevel_init SoC-independent, set BOOT_RAM_SIZE to the
constant value 32KB. It
On 02/03/2015 06:00 AM, Vijay Rai wrote:
T1040D4RDB is a Freescale reference board that hosts the T1040 SoC.
It is similar to T1040RDB board with the following differences :
- Has DDR4 memory
- PHY ports have different PHY addresses
- RTC support
- Both QE-TDM and
Hi Guillaume,
which imageformat (bpp) do you have?
which u-boot framebuffer driver is used ?
best regards,
HAnnes
On 2015-02-26 17:52, Guillaume Gardet wrote:
Hi,
I am trying to display a BMP image on a Samsung Chromebook (snow), but
I get wrong colors. The image is displayed but colors are
When CONFIG_SYS_MALLOC_SIMPLE is defined, free() is a static inline. Make
sure that the export interface still builds in this case.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v5: None
Changes in v4:
- Add new patch to make the export interface support CONFIG_SYS_MALLOC_SIMPLE
Use the full driver model GPIO and serial drivers in SPL now that these are
supported. Since device tree is not available they will use platform data.
Remove the special SPL GPIO function as it is no longer needed.
This is all in one commit to maintain bisectability.
Signed-off-by: Simon Glass
This code is duplicated in ph1-ld4/sg_init.c and ph1-pro4/sg_init.c.
Merge the same code into a new file, memconf.c.
The helper functions no longer have to be placed in the header file.
Also, move them into memconf.c.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
Changes in v5:
This function was intended for MN2WS0235 (what we call PH1-Pro4TV).
On that SoC, MPLL is already running on the power-on reset and it
makes sense to stop the PLL at early boot-up.
On the other hand, PH1-Pro4(R) does not have SC_MPLLOSCCTL register,
so this function has no point.
Signed-off-by:
This is necessary to use the xHCI cores for PH1-Pro4.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/mach-uniphier/ph1-pro4/pinctrl.c | 7 +++
1 file changed, 7 insertions(+)
diff --git
Two support card variants are used with UniPhier reference boards:
- 1 chip select support card (original CPLD)
- 3 chip selects support card (ARIMA-compatible CPLD)
Currently, the former is only supported on PH1-Pro4, but it can be
expanded to PH1-LD4, PH1-sLD8 with a little code change.
Support xHCI host driver used on Panasonic UniPhier platform.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
Acked-by: Marek Vasut ma...@denx.de
---
Changes in v5: None
Changes in v4:
- use fdtdec_find_aliases_for_id() to get the offset to the node
Changes in v3: None
Changes in v2:
Split the current clkrst_init() into two functions:
- early_clkrst_init(): called from SPL
Deassert the reset signals of the memory controller and some other
basic cores.
- clkrst_init(): called from main U-boot
Deassert the reset signals that are necessary for the access to
For all the UniPhier SoCs so far, the reset signal of the NAND core
is automatically deasserted after the PLL gets stabled.
(The bit 2 of SC_RSTCTRL is default to one.)
This causes a fatal problem on the NAND controller of PH1-LD4.
For that SoC, the NAND I/O pins are not set up yet at the
Hi Albert,
2015-02-26 6:14 GMT+09:00 Albert ARIBAUD albert.u.b...@aribaud.net:
I'm fine with the patch's goal and principle, but it does not seem to
apply properly to u-boot-arm/master. Can you have a look?
Sure.
I've just posted v2:
http://patchwork.ozlabs.org/patch/444028/
It should
EHCI host controllers have a common register interface.
We may wish to implement a generic EHCI driver someday.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/dts/uniphier-ph1-ld4.dtsi | 8
Each USB port corresponds to the following IP core:
port0: xHCI (0x65a0) SS+HS
port1: xHCI (0x65c0) HS (SS PHY is not implemented)
port2: EHCI (0x5a800100) HS
port3: EHCI (0x5a810100) HS
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
Changes in v5: None
Changes in v4:
PH1-Pro4 includes both EHCI and xHCI IP cores.
Unfortunately, U-Boot cannot enable EHCI and xHCI support
simultaneously. Some users may wish Super-Speed connection.
Disable CONFIG_USB_EHCI_HCD and enable CONFIG_USB_XHCI_HCD.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
Changes
The 3CS support card (CONFIG_DCC_MICRO_SUPPORT_CARD) used to be used
very often before, but it is recently getting a minority. Swith to
the 1CS support card (CONFIG_PFC_MICRO_SUPPORT_CARD).
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
Changes in v5: None
Changes in v4: None
On 02/26/2015 10:03 AM, Alban Bedel wrote:
On Tue, 24 Feb 2015 12:25:50 -0700
Stephen Warren swar...@wwwdotorg.org wrote:
On 02/24/2015 10:41 AM, Alban Bedel wrote:
On Tue, 24 Feb 2015 10:00:43 -0700
Stephen Warren swar...@wwwdotorg.org wrote:
On 02/24/2015 09:44 AM, Alban Bedel wrote:
This function has grown into something of a monster. Some boards are setting
up a console and DRAM here in SPL. This requires global_data which should be
set up in one place (crt0.S).
There is no need for SPL to use s_init() for anything since board_init_f()
is called immediately afterwards.
Move arch/arm/include/asm/arch-uniphier/*
- arch/arm/mach-uniphier/include/mach/*
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
Changes in v5: None
Changes in v4: None
Changes in v3:
- Newly added
Changes in v2: None
MAINTAINERS
This series contains:
- bug fixes and refactoring of SBC init code
- add missing reset controls
- support 1CS support card for all the SoCs
- add xHCI driver
Masahiro Yamada (26):
ARM: UniPhier: move SoC sources to mach-uniphier
ARM: UniPhier: move SoC headers to
We do not have to set the LCR register every time we change the
baud-rate. We just need to set it up once in the probe function.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
Changes in v5:
- Newly addd
Changes in v4: None
Changes in v3: None
Changes in v2: None
For PH1-Pro4, the 8 bit write access to LCR register (offset = 0x11)
is not working correctly. As a side effect, it also modifies MCR
register (offset = 0x10) and results in unexpected behavior.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
Changes in v5:
- Newly added
Changes
At present SPL uses a single stack, either CONFIG_SPL_STACK or
CONFIG_SYS_INIT_SP_ADDR. Since some SPL features (such as MMC and
environment) require a lot of stack, some boards set CONFIG_SPL_STACK to
point into SDRAM. They then set up SDRAM very early, before board_init_f(),
so that the larger
This is necessary to use the USB 3.0 host controllers on PH1-Pro4.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/mach-uniphier/include/mach/sc-regs.h | 11 ++-
On Thu, Feb 26, 2015 at 1:50 PM, Fabio Estevam
fabio.este...@freescale.com wrote:
User Mass Storage is very useful for flashing the on-board eMMC.
Add support for it.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
Acked-by: Otavio Salvador ota...@ossystems.com.br
--
Otavio
Hi,
On Thu, Feb 26, 2015 at 4:37 AM, Daniel Schwierzeck
daniel.schwierz...@gmail.com wrote:
2015-02-26 11:17 GMT+01:00 Paul Burton paul.bur...@imgtec.com:
On Thu, Feb 19, 2015 at 01:50:23PM +, Matthew Fortune wrote:
Hi Daniel,
The spec for MIPS Unified Hosting Interface is available
On Thu, 26 Feb 2015 12:08:15 +0100
Gábor Nyers gny...@opensuse.org wrote:
The Jesurun Q5 has a black plastic casing with the approximate dimensions of
100mm x 100mm x 24mm with rounded edges. In terms of hardware it features an
Allwinner A10 SoC with 1GB RAM and 8GB of NAND flash. The storage
User Mass Storage is very useful for flashing the on-board eMMC.
Add support for it.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
Acked-by: Otavio Salvador ota...@ossystems.com.br
---
Changes since v2:
- None
Changes since v1:
- Remove EXT2/EXT4 and BOUNCE_BUFFER support
Add EXT4 support.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
Changes since v2:
- Fix subject and commit log to only mention ext4
Changes since v1:
- Newly introduced in this series
include/configs/mx6sabre_common.h | 2 ++
1 file changed, 2 insertions(+)
diff --git
I would like to debug from the earliest possible point pre-relocation (for
educational reasons). Couple questions
In the Makefile, where do I place the following flags...
-Os #-fomit-frame-pointer -g -fno-schedule-insns -fno-schedule-insns2
I've added the flags in a few different spots, but
Add USB Mass Storage support. This is useful for flashing the on-board eMMC.
Signed-off-by: Soeren Moch sm...@web.de
---
Cc: Stefano Babic sba...@denx.de
---
include/configs/tbs2910.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/include/configs/tbs2910.h
On Thu, Feb 26, 2015 at 1:50 PM, Fabio Estevam
fabio.este...@freescale.com wrote:
Add EXT2/EXT4 and BOUNCE_BUFFER support.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
Acked-by: Otavio Salvador ota...@ossystems.com.br
--
Otavio Salvador O.S. Systems
Hi Fabio,
On 02/26/2015 06:50 PM, Fabio Estevam wrote:
Add EXT2/EXT4 and BOUNCE_BUFFER support.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
Changes since v1:
- Newly introduced in this series
include/configs/mx6sabre_common.h | 2 ++
1 file changed, 2 insertions(+)
diff
On Thu, Feb 26, 2015 at 4:58 PM, Fabio Estevam
fabio.este...@freescale.com wrote:
Add EXT4 support.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
Acked-by: Otavio Salvador ota...@ossystems.com.br
And sorry for not notice the mistake in the commit log.
--
Otavio Salvador
.Hi Fabio,
On Wed, Feb 25, 2015 at 11:05 PM, Fabio Estevam feste...@gmail.com wrote:
I have just tested top of tree U-boot and my mx53loco board boots fine.
That's because CONFIG_HAS_VBAR is set for ARMv7. There may be an
issue, though: according to Freescale, the TrustZone security
extensions
On Wed, Feb 18, 2015 at 09:14:03AM +0100, Jan Kiszka wrote:
[...]
+ENTRY(psci_cpu_off)
+ bl psci_cpu_off_common
+
+ mrc p15, 0, r1, c0, c0, 5 @ MPIDR
+ and r1, r1, #7 @ number of CPUs in cluster
+
+ get_csr_reg r1, r2, r3
+
+ ldr
On Wed, Feb 18, 2015 at 09:14:03AM +0100, Jan Kiszka wrote:
[...]
diff --git a/arch/arm/cpu/armv7/tegra124/ap.c
b/arch/arm/cpu/armv7/tegra124/ap.c
[...]
+void ap_pm_init(void)
+{
+ struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
+ struct pmc_ctlr *pmc = (struct
Hello Stephen,
diff --git a/include/configs/chromeos.h b/include/configs/chromeos.h
+/* Stringify a token */
+#ifndef STRINGIFY
+#define _STRINGIFY(x) #x
+#define STRINGIFY(x)_STRINGIFY(x)
+#endif
Shouldn't that be in some common header so it isn't ever duplicated?
Hi Vincent,
On 26/02/15 08:27, Vincent wrote:
Hi,
I finally hacked my way through U-boot and I managed to add raspberry's
boot code inside U-boot so that it can start as usual when using kernel_old
= 1. I don't think
we want this as a final solution but it made me understand a few things
I tried what Stephen suggested, and just changing CONFIG_SYS_TEXT_BASE to
0x0 (with kernel_old=1) does not work: the board display some garbage on
the uart then hangs. The content of the garbage makes me thinks that
nothing is done to handle the four cores in this setting which ends up
badly. I
Hi,
While building vexpress_aemv8a_defconfig, I get the following error:
u-boot contains unexpected relocations: R_AARCH64_ABS64
R_AARCH64_RELATIVE
Makefile:1258: recipe for target 'checkarmreloc' failed
On Thu, Feb 19, 2015 at 01:50:23PM +, Matthew Fortune wrote:
Hi Daniel,
The spec for MIPS Unified Hosting Interface is available here:
http://prplfoundation.org/wiki/MIPS_documentation
As we have previously discussed, this is an ideal place to
define the handover of device tree data
Hello Benoît,
On Thu, 26 Feb 2015 00:56:00 +0100, Benoît Thébaudeau
benoit.thebaudeau@gmail.com wrote:
Dear Dave Kucharczyk,
On Wed, Feb 25, 2015 at 11:08 PM, DaveKucharczyk
david.kucharc...@gmail.com wrote:
Fabio Estevam-2 wrote
Also, you said that your 512MB board version works
Oh and I don't think there is a TZ Address space controller on the
raspberry, or at least I am not aware of any.
2015-02-26 10:32 GMT+01:00 Vincent vincent.si...@gmail.com:
I tried what Stephen suggested, and just changing CONFIG_SYS_TEXT_BASE to
0x0 (with kernel_old=1) does not work: the
Hi Alexey,
The fastboot reboot-bootloader command is defined to
re-enter into fastboot mode after rebooting into
bootloader. This command is usually used after updating
bootloader via fastboot.
This commit implements only a generic side of the
command - setting of the reset flag and then
Hello Albert,
On Wed, 25 Feb 2015 21:57:36 +0100, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
Hello Simon,
On Wed, 25 Feb 2015 07:00:23 -0700, Simon Glass s...@chromium.org
wrote:
Hi Albert,
On 25 February 2015 at 06:27, Simon Glass s...@chromium.org wrote:
Hi Albert,
On
The Jesurun Q5 has a black plastic casing with the approximate dimensions of
100mm x 100mm x 24mm with rounded edges. In terms of hardware it features an
Allwinner A10 SoC with 1GB RAM and 8GB of NAND flash. The storage capacity can
be extended up to 32GB with a MicroSD card. The external
Hans,
I've resubmitted the patch with the Sign-off line included. Thanks a lot
for your help!
Regards,
Gábor
On Thu, 26 Feb 2015 09:56:58 +0100
Hans de Goede hdego...@redhat.com wrote:
Hi Gábor,
On 26-02-15 00:16, Gábor Nyers wrote:
The Jesurun Q5 has a black plastic casing with the
Hi Marek,
On Wednesday, February 25, 2015 at 10:15:24 AM, Lukasz Majewski wrote:
Hi Marek,
Hi!
On Tuesday, February 24, 2015 at 05:05:29 PM, Lukasz Majewski
wrote:
Hi Lukasz,
[...]
I'll stick with your recommendation, though I'd like to --
somehow -- work in
Hi,
I finally hacked my way through U-boot and I managed to add raspberry's
boot code inside U-boot so that it can start as usual when using kernel_old
= 1. I don't think
we want this as a final solution but it made me understand a few things
about U-boot architecture (in short: I added a new
Hi Gábor,
On 26-02-15 00:16, Gábor Nyers wrote:
The Jesurun Q5 has a black plastic casing with the approximate
dimensions of 100mm x 100mm x 24mm with rounded edges. In terms of
hardware it features an Allwinner A10 SoC with 1GB RAM and 8GB of NAND
flash. The storage capacity can be extended up
On 2015-02-26 10:08, Thierry Reding wrote:
On Wed, Feb 18, 2015 at 09:14:03AM +0100, Jan Kiszka wrote:
[...]
+ENTRY(psci_cpu_off)
+bl psci_cpu_off_common
+
+mrc p15, 0, r1, c0, c0, 5 @ MPIDR
+and r1, r1, #7 @ number of CPUs in cluster
+
+
After discussion during the last u-boot mini summit with USB maintainer -
Marek Vasut - it has been decided, that gadget development should be
coordinated by DFU custodian.
Such patch formalizes current development status.
Signed-off-by: Lukasz Majewski l.majew...@samsung.com
---
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