Re: [PATCH 1/2] arm: socfpga: arria10: add option to reprogram the FPGA every reboot

On 2/22/24 09:20, Michał Barnaś wrote: Add Kconfig that enables FPGA reprogramming with warm boot on Arria 10. This option allows to change the bitstream on the filesystem and apply changes with warm reboot without the need for a power cycle. Signed-off-by: Michał Barnaś ---

Re: [PATCH 0/2] arm: socfpga: arria10: allow to reprogram FPGA with warm reboot

On 2/22/24 09:20, Michał Barnaś wrote: By default, the board requires power cycle (cold boot) to program the FPGA with bitstream. This change adds Kconfig that allows to enable reprogramming the FPGA with every boot. This makes the update process of the bitstream on the filesystem to be

[PATCH] board: altera: c5/a10/a5/stratix10: remove Chin Liang as maintainer

Chin Liang is no longer actively maintaining this project. Signed-off-by: Dinh Nguyen --- board/altera/arria10-socdk/MAINTAINERS | 1 - board/altera/arria5-socdk/MAINTAINERS| 1 - board/altera/cyclone5-socdk/MAINTAINERS | 1 - board/altera/stratix10-socdk/MAINTAINERS | 1 - 4 files

Re: [PATCH] configs: socfpga: Add CONFIG_NET_RANDOM_ETHADDR=y to SOCFPGA defconfig

@@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM_RESET=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y Acked-by: Dinh Nguyen

Re: Revert "ARM: socfpga: Remove socfpga_sdram_apply_static_cfg()

CC Hean Loong: On 8/6/20 7:36 AM, Wolfgang Grandegger wrote: > Am 06.08.20 um 13:04 schrieb Marek Vasut: >> On 8/6/20 12:53 PM, Wolfgang Grandegger wrote: >>> This reverts commit c5f4b805755912a3d2fe20f014b6b6ab0473bd73. >>> >>> Conflicts: >>> arch/arm/mach-socfpga/misc_gen5.c >>> >>>

Re: [PATCH] arm: dts: socfpga: l2c-310 full line of zeros error @kernel boot

On 6/15/20 12:56 AM, Nico Becker wrote: > Am 12.06.2020 um 22:27 schrieb Dinh Nguyen: >> >> On 6/12/20 6:41 AM, Marek Vasut wrote: >>> On 6/12/20 1:04 PM, Nico Becker wrote: >>>> Am 12.06.2020 um 07:51 schrieb Nico Becker: >>>&g

Re: [PATCH] arm: dts: socfpga: l2c-310 full line of zeros error @kernel boot

On 6/10/20 8:23 AM, Marek Vasut wrote: > On 6/10/20 3:21 PM, Nico Becker wrote: >> Am 10.06.2020 um 15:19 schrieb Marek Vasut: >>> On 6/10/20 3:14 PM, Nico Becker wrote: if i remove the arm,shared-override option in the dts file, the kernel boot without an error. With the option

Re: [U-Boot] [PATCH v2 0/4] arm: socfpga: Convert drivers from struct to defines

ork.ozlabs.org/cover/1149731/ > I think you also need to Simon Goldschmidt to this series. Beside the minor incorrect address missing a zero in patch 1, I've tested this series on the Sockit. Tested-by: Dinh Nguyen Dinh ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v2 1/4] arm: dts: socfpga: Add u-boot, dm-pre-reloc for sysmgr and clkmgr nodes

On 9/10/19 3:38 AM, Ley Foon Tan wrote: > Add u-boot,dm-pre-reloc for sysmgr and clkmgr nodes to use it in SPL. > In preparation to get base address from DT. > > Signed-off-by: Ley Foon Tan > --- > arch/arm/dts/socfpga-common-u-boot.dtsi | 8 > arch/arm/dts/socfpga.dtsi

Re: [U-Boot] [PATCH 01/15] arm: socfpga: agilex: Add base address for Intel Agilex SoC

On 6/24/19 8:16 PM, Ley Foon Tan wrote: > On Tue, Jun 25, 2019 at 4:00 AM Simon Goldschmidt > wrote: >> >> Am 30.05.2019 um 11:03 schrieb Ley Foon Tan: >>> Add base address for Intel Agilex SoC. >>> >>> Reuse base_addr_s10.h for Agilex, only one base address is >>> different from S10. >>> >>>

Re: [U-Boot] [PATCH 04/14] arm: socfpga: agilex: Add reset manager support

On 5/10/19 12:54 AM, Ley Foon Tan wrote: > Add reset manager support for Agilex. > > Signed-off-by: Ley Foon Tan > --- > .../mach-socfpga/include/mach/reset_manager.h | 5 ++- > .../include/mach/reset_manager_agilex.h | 38 +++ AFAIK, there's really nothing different in

Re: [U-Boot] [PATCH 01/14] arm: socfpga: agilex: Add base address for Intel Agilex SoC

On 5/10/19 12:54 AM, Ley Foon Tan wrote: > Add base address for Intel Agilex SoC. > > Signed-off-by: Ley Foon Tan > --- > .../include/mach/base_addr_agilex.h | 38 +++ > 1 file changed, 38 insertions(+) > create mode 100644

Re: [U-Boot] [PATCHv5 0/6] dm: cache: add dm cache driver

On 4/24/19 7:58 AM, Tom Rini wrote: > On Wed, Apr 24, 2019 at 07:32:14AM -0500, Dinh Nguyen wrote: >> >> >> On 4/23/19 5:02 PM, Tom Rini wrote: >>> On Tue, Apr 23, 2019 at 04:55:00PM -0500, Dinh Nguyen wrote: >>>> Hi, >>>> >>>> Th

Re: [U-Boot] [PATCHv5 0/6] dm: cache: add dm cache driver

On 4/23/19 5:02 PM, Tom Rini wrote: > On Tue, Apr 23, 2019 at 04:55:00PM -0500, Dinh Nguyen wrote: >> Hi, >> >> This is V4 of the series to add a UCLASS_CACHE dm driver to handling >> the configuration of cache settings. Place this new driver under >> /driver

[U-Boot] [PATCHv5 4/6] dm: cache: add the pl310 cache controller driver

ency). I believe these are the settings that affect performance the most. Comprehensive settings can be done by the OS. Reviewed-by: Simon Glass Signed-off-by: Dinh Nguyen --- v4: no change v3: Add Reviewed-by and fix nits v2: split out patch and address comments from Simon Glass --- drivers/cache

[U-Boot] [PATCHv5 6/6] configs: socfpga: add imply pl310 cache controller

Select the PL310 UCLASS_CACHE driver for SoCFPGA. Reviewed-by: Marek Vasut Reviewed-by: Simon Glass Signed-off-by: Dinh Nguyen --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f58f8fb235..f5132d8174 100644 --- a/arch/arm

[U-Boot] [PATCHv5 3/6] dm: cache: Create a uclass for cache

The cache UCLASS will be used for configure settings that can be found in a CPU's L2 cache controller. Add a uclass and a test for cache. Reviewed-by: Simon Glass Signed-off-by: Dinh Nguyen --- v5: fix compile error for sandbox_cache.c v4: re-order includes and add Reviewed-by: v3: Add

[U-Boot] [PATCHv5 5/6] ARM: socfpga: use the pl310 driver to configure the cache

Find the UCLASS_CACHE driver to configure the cache controller's settings. Reviewed-by: Marek Vasut Reviewed-by: Simon Glass Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/misc.c | 16 +++- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-socfpga

[U-Boot] [PATCHv5 2/6] ARM: pl310: Add macro's for handling tag and data latency mask

Add the PL310 macros for latency control setup, read and write bits. Reviewed-by: Marek Vasut Reviewed-by: Simon Glass Signed-off-by: Dinh Nguyen --- arch/arm/include/asm/pl310.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h

[U-Boot] [PATCHv5 1/6] Documentation: dts: Add pl310 cache controller dts documentation

known as PL210/PL220/PL310 and variants) and not generic as the file name implies. It's not valid for integrated L2 controllers as found in e.g. Cortex-A15/A7/A57/A53." Reviewed-by: Simon Glass Signed-off-by: Dinh Nguyen --- .../devicetree/bindings/arm/l2c2x0.txt| 114 ++

[U-Boot] [PATCHv5 0/6] dm: cache: add dm cache driver

be done in the OS. Diffs from v4: - Fix compile error found in sandbox_cache.c Dinh Nguyen (6): Documentation: dts: Add pl310 cache controller dts documentation ARM: pl310: Add macro's for handling tag and data latency mask dm: cache: Create a uclass for cache dm: cache: add the pl310

Re: [U-Boot] [U-Boot, PATCHv4, 3/6] dm: cache: Create a uclass for cache

On 4/22/19 12:48 PM, Tom Rini wrote: > On Mon, Apr 01, 2019 at 05:32:17PM -0500, Dinh Nguyen wrote: > >> The cache UCLASS will be used for configure settings that can be found >> in a CPU's L2 cache controller. >> >> Add a uclass and a test for cache. >> &g

[U-Boot] [PATCHv4 5/6] ARM: socfpga: use the pl310 driver to configure the cache

Find the UCLASS_CACHE driver to configure the cache controller's settings. Reviewed-by: Marek Vasut Reviewed-by: Simon Glass Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/misc.c | 16 +++- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-socfpga

[U-Boot] [PATCHv4 4/6] dm: cache: add the pl310 cache controller driver

ency). I believe these are the settings that affect performance the most. Comprehensive settings can be done by the OS. Reviewed-by: Simon Glass Signed-off-by: Dinh Nguyen --- v4: no change v3: Add Reviewed-by and fix nits v2: split out patch and address comments from Simon Glass --- drivers/cache

[U-Boot] [PATCHv4 3/6] dm: cache: Create a uclass for cache

The cache UCLASS will be used for configure settings that can be found in a CPU's L2 cache controller. Add a uclass and a test for cache. Reviewed-by: Simon Glass Signed-off-by: Dinh Nguyen --- v4: re-order includes and add Reviewed-by: v3: Add cache_get_info() to check for non-zero value

[U-Boot] [PATCHv4 6/6] configs: socfpga: add imply pl310 cache controller

Select the PL310 UCLASS_CACHE driver for SoCFPGA. Reviewed-by: Marek Vasut Reviewed-by: Simon Glass Signed-off-by: Dinh Nguyen --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f42eccef80..f4c6262bb0 100644 --- a/arch/arm

[U-Boot] [PATCHv4 2/6] ARM: pl310: Add macro's for handling tag and data latency mask

Add the PL310 macros for latency control setup, read and write bits. Reviewed-by: Marek Vasut Reviewed-by: Simon Glass Signed-off-by: Dinh Nguyen --- arch/arm/include/asm/pl310.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h

[U-Boot] [PATCHv4 1/6] Documentation: dts: Add pl310 cache controller dts documentation

known as PL210/PL220/PL310 and variants) and not generic as the file name implies. It's not valid for integrated L2 controllers as found in e.g. Cortex-A15/A7/A57/A53." Reviewed-by: Simon Glass Signed-off-by: Dinh Nguyen --- .../devicetree/bindings/arm/l2c2x0.txt| 114 ++

[U-Boot] [PATCHv4 0/6] dm: cache: add dm cache driver

be done in the OS. Diffs from v3: - Re-order includes in a correct order - Add final Reviewed-by: in "dm: cache: Create a uclass for cache" Dinh Nguyen (6): Documentation: dts: Add pl310 cache controller dts documentation ARM: pl310: Add macro's for handling tag and data latency

[U-Boot] [PATCHv3 4/6] dm: cache: add the pl310 cache controller driver

ency). I believe these are the settings that affect performance the most. Comprehensive settings can be done by the OS. Reviewed-by: Simon Glass Signed-off-by: Dinh Nguyen --- v3: Add Reviewed-by and fix nits v2: split out patch and address comments from Simon Glass --- drivers/cache/Kconfig

[U-Boot] [PATCHv3 5/6] ARM: socfpga: use the pl310 driver to configure the cache

Find the UCLASS_CACHE driver to configure the cache controller's settings. Reviewed-by: Marek Vasut Reviewed-by: Simon Glass Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/misc.c | 16 +++- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-socfpga

[U-Boot] [PATCHv3 3/6] dm: cache: Create a uclass for cache

The cache UCLASS will be used for configure settings that can be found in a CPU's L2 cache controller. Add a uclass and a test for cache. Signed-off-by: Dinh Nguyen --- v3: Add cache_get_info() to check for non-zero value Add comments to cache_info struct v2: separate out uclass patch from

[U-Boot] [PATCHv3 6/6] configs: socfpga: add imply pl310 cache controller

Select the PL310 UCLASS_CACHE driver for SoCFPGA. Reviewed-by: Marek Vasut Reviewed-by: Simon Glass Signed-off-by: Dinh Nguyen --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f42eccef80..f4c6262bb0 100644 --- a/arch/arm

[U-Boot] [PATCHv3 2/6] ARM: pl310: Add macro's for handling tag and data latency mask

Add the PL310 macros for latency control setup, read and write bits. Reviewed-by: Marek Vasut Reviewed-by: Simon Glass Signed-off-by: Dinh Nguyen --- arch/arm/include/asm/pl310.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h

[U-Boot] [PATCHv3 1/6] Documentation: dts: Add pl310 cache controller dts documentation

known as PL210/PL220/PL310 and variants) and not generic as the file name implies. It's not valid for integrated L2 controllers as found in e.g. Cortex-A15/A7/A57/A53." Reviewed-by: Simon Glass Signed-off-by: Dinh Nguyen --- .../devicetree/bindings/arm/l2c2x0.txt| 114 ++

[U-Boot] [PATCHv3 0/6] dm: cache: add dm cache driver

be done in the OS. Diffs from v2: - Add cache_get_info() to check for non-zero value - Add comments to cache_info struct - Fix up nits from Simon Glass Dinh Nguyen (6): Documentation: dts: Add pl310 cache controller dts documentation ARM: pl310: Add macro's for handling tag and data latency

Re: [U-Boot] [PATCH 1/2] ARM: socfpga: Pull PL310 clearing into common code

On 3/22/19 9:30 AM, Marek Vasut wrote: > Pull the PL310 clearing code into common code, so it can be reused > by Arria10. > > Signed-off-by: Marek Vasut > Cc: Dalon Westergreen > Cc: Dinh Nguyen > --- > arch/arm/mach-socfpga/include/mach/misc.h | 1 + > a

Re: [U-Boot] [PATCH] ARM: dts: socfpga: Add missing altr, sysmgr-syscon for EMAC

On 3/13/19 6:54 AM, Ley Foon Tan wrote: > On Wed, 2019-03-13 at 10:33 -0500, Dinh Nguyen wrote: >> >> On 3/13/19 9:32 AM, Dinh Nguyen wrote: >>> >>> >>> >>> On 3/13/19 12:59 AM, Ley Foon Tan wrote: >>>> >>>> On Wed, 2

Re: [U-Boot] [PATCH] ARM: dts: socfpga: Add missing altr, sysmgr-syscon for EMAC

On 3/13/19 9:32 AM, Dinh Nguyen wrote: > > > On 3/13/19 12:59 AM, Ley Foon Tan wrote: >> On Wed, 2019-03-13 at 04:30 +0100, Marek Vasut wrote: >>> On 3/13/19 4:03 AM, Ley Foon Tan wrote: >>>> >>>> Syscon register is required in dts to select

Re: [U-Boot] [PATCH] ARM: dts: socfpga: Add missing altr, sysmgr-syscon for EMAC

On 3/13/19 12:59 AM, Ley Foon Tan wrote: > On Wed, 2019-03-13 at 04:30 +0100, Marek Vasut wrote: >> On 3/13/19 4:03 AM, Ley Foon Tan wrote: >>> >>> Syscon register is required in dts to select correct >>> PHY interface. >>> >>> Fix error below: >>> >>> Net:   Failed to get syscon: -2 >>> >>>

[U-Boot] [PATCHv2 3/6] dm: cache: Create a uclass for cache

The cache UCLASS will be used for configure settings that can be found in a CPU's L2 cache controller. Add a uclass and a test for cache. Signed-off-by: Dinh Nguyen --- v2: separate out uclass patch from driver and add test --- drivers/Kconfig | 2 ++ drivers/Makefile

[U-Boot] [PATCHv2 5/6] ARM: socfpga: use the pl310 driver to configure the cache

Find the UCLASS_CACHE driver to configure the cache controller's settings. Reviewed-by: Marek Vasut Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/misc.c | 16 +++- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach

[U-Boot] [PATCHv2 4/6] dm: cache: add the pl310 cache controller driver

ency). I believe these are the settings that affect performance the most. Comprehensive settings can be done by the OS. Signed-off-by: Dinh Nguyen --- v2: split out patch and address comments from Simon Glass --- drivers/cache/Kconfig | 9 + drivers/cache/Makefile | 1 + drivers/cache/ca

[U-Boot] [PATCHv2 6/6] configs: socfpga: add imply pl310 cache controller

Select the PL310 UCLASS_CACHE driver for SoCFPGA. Reviewed-by: Marek Vasut Signed-off-by: Dinh Nguyen --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f42eccef80..f4c6262bb0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig

[U-Boot] [PATCHv2 1/6] Documentation: dts: Add pl310 cache controller dts documentation

known as PL210/PL220/PL310 and variants) and not generic as the file name implies. It's not valid for integrated L2 controllers as found in e.g. Cortex-A15/A7/A57/A53." Signed-off-by: Dinh Nguyen --- .../devicetree/bindings/arm/l2c2x0.txt| 114 ++ 1 file changed, 114 i

[U-Boot] [PATCHv2 2/6] ARM: pl310: Add macro's for handling tag and data latency mask

Add the PL310 macros for latency control setup, read and write bits. Reviewed-by: Marek Vasut Signed-off-by: Dinh Nguyen --- arch/arm/include/asm/pl310.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h index b83978b1cc

[U-Boot] [PATCHv2 0/6] dm: cache: add dm cache driver

. Dinh Nguyen (6): Documentation: dts: Add pl310 cache controller dts documentation ARM: pl310: Add macro's for handling tag and data latency mask dm: cache: Create a uclass for cache dm: cache: add the pl310 cache controller driver ARM: socfpga: use the pl310 driver to configure the cache

[U-Boot] [PATCHv1 3/4] configs: socfpga: add imply pl310 cache controller

Select the PL310 UCLASS_CACHE driver for SoCFPGA. Signed-off-by: Dinh Nguyen --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f42eccef80..f4c6262bb0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -845,6 +845,7 @@ config

[U-Boot] [PATCHv1 4/4] ARM: socfpga: use the pl310 driver to configure the cache

Find the UCLASS_CACHE driver to configure the cache controller's settings. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/misc.c | 16 +++- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index

[U-Boot] [PATCHv1 0/4] dm: cache: add dm cache driver

Dinh Nguyen (4): ARM: pl310: Add macro's for handling tag and data latency mask dm: cache: Create a uclass for cache controller configs: socfpga: add imply pl310 cache controller ARM: socfpga: use the pl310 driver to configure the cache arch/arm/Kconfig | 1 + arch/arm/include

[U-Boot] [PATCHv1 2/4] dm: cache: Create a uclass for cache controller

the most. Comprehensive settings can be done by the OS. Signed-off-by: Dinh Nguyen --- drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/cache/Kconfig| 22 ++ drivers/cache/Makefile | 3 ++ drivers/cache/cache-l2x0.

[U-Boot] [PATCHv1 1/4] ARM: pl310: Add macro's for handling tag and data latency mask

Add the PL310 macros for latency control setup, read and write bits. Signed-off-by: Dinh Nguyen --- arch/arm/include/asm/pl310.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h index b83978b1cc..f69e9e45f8 100644 --- a/arch/arm

Re: [U-Boot] [PATCH v11 9/9] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL

On 3/7/19 2:24 AM, Chee, Tien Fong wrote: > On Tue, 2019-03-05 at 22:52 -0600, Dinh Nguyen wrote: >> >> On 3/5/19 10:23 AM, tien.fong.c...@intel.com wrote: >>> >>> From: Tien Fong Chee >>> >>> After some series of patches to maximise r

Re: [U-Boot] [PATCH v11 8/9] ARM: socfpga: Synchronize the configuration for A10 SoCDK

On 3/5/19 10:23 AM, tien.fong.c...@intel.com wrote: > From: Tien Fong Chee > > Update the default configuration file to enable the necessary functionality > the get the kit working. > > Signed-off-by: Tien Fong Chee > > --- > > changes for v8 > - Moved the FIT related configs to the patch

Re: [U-Boot] [PATCH v11 9/9] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL

On 3/5/19 10:23 AM, tien.fong.c...@intel.com wrote: > From: Tien Fong Chee > > After some series of patches to maximise reusable of memory pool, here come > to result of reasonable size required for whole SDMMC boot working on A10 > SoCDK. Size required come from default max cluster(0x1) +

Re: [U-Boot] [PATCH v11 4/9] ARM: socfpga: Move the watchdog reset to the looping location

It looks like this patch was not in the previous 9 versions of this series? Please try to not add new functionality to a series that is already gone through so many reviews. It make reviewing the series really confusing! On 3/5/19 10:23 AM, tien.fong.c...@intel.com wrote: > From: Tien Fong Chee

Re: [U-Boot] [PATCH v11 3/9] ARM: socfpga: Cleaning up the messages

On 3/5/19 10:23 AM, tien.fong.c...@intel.com wrote: > From: Tien Fong Chee > > Ensure the comment and debug messages are always consistent with the rest. The rest of what? This patch seems unnecessary to me. Dinh > > Signed-off-by: Tien Fong Chee > --- > drivers/fpga/socfpga_arria10.c |

Re: [U-Boot] [PATCH v11 6/9] ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK

On 3/5/19 10:23 AM, tien.fong.c...@intel.com wrote: > From: Tien Fong Chee > > Update the default configuration file to enable the necessary functionality > to get the SoCFPGA loadfs driver support. This would enable the > implementation of programming bitstream into FPGA from MMC. > >

Re: [U-Boot] [RFC PATCHv1 2/3] defconfig: socfpga_sockit_defconfig: enable L2X0_CACHE driver

On 3/5/19 1:20 PM, Marek Vasut wrote: > On 3/5/19 8:03 PM, Dinh Nguyen wrote: >> Enable CONFIG_MISC and CONFIG_L2X0_CACHE config options. >> >> Signed-off-by: Dinh Nguyen >> --- >> configs/socfpga_sockit_defconfig | 2 ++ >> 1 file changed, 2 i

Re: [U-Boot] [RFC PATCHv1 3/3] ARM: socfpga: let the pl310 driver configure the cache settings

On 3/5/19 1:20 PM, Marek Vasut wrote: > On 3/5/19 8:03 PM, Dinh Nguyen wrote: >> Load the PL310 L2 cache driver and allow it to setup the cache settings >> >> Signed-off-by: Dinh Nguyen >> --- >> arch/arm/mach-socfpga/misc.c | 15 ++- >&g

Re: [U-Boot] [RFC PATCHv1 1/3] misc: pl310: add a misc driver for the pl310 cache controller

On 3/5/19 1:19 PM, Marek Vasut wrote: > On 3/5/19 8:03 PM, Dinh Nguyen wrote: >> The driver will read the cache properties from the device tree file and >> set it up. >> >> >> +config L2X0_CACHE >> +bool "L2x0 Cache support" >

Re: [U-Boot] [PATCH v11 1/9] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10

Curious, you sent out 3 versions(2x v10, and v11) within ~2 hours. What versions should we be reviewing? On 3/5/19 10:23 AM, tien.fong.c...@intel.com wrote: > From: Tien Fong Chee > > This patch adds description on properties about file name used for both > peripheral bitstream and core

[U-Boot] [RFC PATCHv1 3/3] ARM: socfpga: let the pl310 driver configure the cache settings

Load the PL310 L2 cache driver and allow it to setup the cache settings Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/misc.c | 15 ++- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index fcf211d62b

[U-Boot] [RFC PATCHv1 2/3] defconfig: socfpga_sockit_defconfig: enable L2X0_CACHE driver

Enable CONFIG_MISC and CONFIG_L2X0_CACHE config options. Signed-off-by: Dinh Nguyen --- configs/socfpga_sockit_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index 4c17d1a9e4..0009b0ebc3 100644 --- a/configs

[U-Boot] [RFC PATCHv1 1/3] misc: pl310: add a misc driver for the pl310 cache controller

The driver will read the cache properties from the device tree file and set it up. Signed-off-by: Dinh Nguyen --- arch/arm/include/asm/pl310.h | 3 ++ drivers/misc/Kconfig | 7 +++ drivers/misc/Makefile| 1 + drivers/misc/cache-l2x0.c| 84

[U-Boot] [RFC PATCHv1 0/3] misc: pl310: add a dm cache driver

and set the corresponding bits in cache controller. I think we can do something similar without make this driver and placing the file in /arch/arm/cpu/armv7, but wanted to get feedback. To-dos: - Add error checking - Add more cache properties Thanks, Dinh Nguyen (3): misc: pl310: add a misc

[U-Boot] [PATCHv2] ARM: socfpga: fix data and tag latency values for pl310 cache controller

1>, the register value should be 0x010. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/misc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index fcf211d62b..ec8339e045 100644 --- a/arch/arm/mach-so

[U-Boot] [PATCH] ARM: socfpga: configure pl310 from dts

Read the cache properties of the L2 cache controller from the device tree and configure it. Signed-off-by: Dinh Nguyen --- arch/arm/include/asm/pl310.h | 4 arch/arm/mach-socfpga/misc.c | 45 +--- 2 files changed, 41 insertions(+), 8 deletions(-) diff

Re: [U-Boot] [PATCH] ARM: socfpga: Configure PL310 latencies

On 3/1/19 10:09 AM, Marek Vasut wrote: > On 3/1/19 4:19 PM, Dinh Nguyen wrote: >> >> >> On 3/1/19 3:40 AM, Marek Vasut wrote: >>> On 3/1/19 12:59 AM, Dinh Nguyen wrote: >>>> Hi Marek, >>>> >>>> On 2/19/19 4:01 AM, Simon Goldschmi

Re: [U-Boot] [PATCH] ARM: socfpga: Configure PL310 latencies

On 3/1/19 3:40 AM, Marek Vasut wrote: > On 3/1/19 12:59 AM, Dinh Nguyen wrote: >> Hi Marek, >> >> On 2/19/19 4:01 AM, Simon Goldschmidt wrote: >>> On Tue, Feb 19, 2019 at 1:44 AM Marek Vasut wrote: >>>> >>>> Configure the PL310 tag an

Re: [U-Boot] [PATCH] ARM: socfpga: Configure PL310 latencies

off-by: Marek Vasut >> Cc: Dalon Westergreen >> Cc: Dinh Nguyen >> --- >> arch/arm/mach-socfpga/misc.c | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c >> index 78fbe28724..1ea4e

Re: [U-Boot] [PATCH] ARM: cache: Fix incorrect bitwise operation

-zero, which is incorrect. Fix the > conditional. > > Signed-off-by: Marek Vasut > Cc: Dalon Westergreen > Cc: Dinh Nguyen > Cc: Tom Rini > Fixes: 93bc21930a1b ("armv7: add PL310 support to u-boot") > --- > arch/arm/lib/cache-pl310.c | 2 +- > 1 file changed,

Re: [U-Boot] [PATCH] ARM: socfpga: Configure PL310 latencies

On 2/18/19 6:44 PM, Marek Vasut wrote: > Configure the PL310 tag and data latency registers, which slightly > improves performance and aligns the behavior with Linux. > > Signed-off-by: Marek Vasut > Cc: Dalon Westergreen > Cc: Dinh Nguyen > --- > arch/arm/mach-soc

Re: [U-Boot] [PATCH] arm: socfpga: move gen5 SDR driver to DM

Hi Marek, On 2/9/19 4:01 AM, Marek Vasut wrote: > On 2/7/19 10:23 PM, Simon Goldschmidt wrote: >> To clean up reset handling for socfpga gen5, let's move the code snippet >> taking the DDR controller out of reset from SPL to the DDR driver. >> >> While at it, port the ddr driver to UCLASS_RAM and

Re: [U-Boot] [PATCH v1 1/4] arm: socfpga: imply SPL config instead of select

On 1/14/19 10:05 AM, Simon Goldschmidt wrote: > Hi Dinh, > > Am 14.01.2019 um 16:58 schrieb Dinh Nguyen: >> Hi Simon, >> >> On 1/14/19 9:50 AM, Simon Goldschmidt wrote: >>> Am 11.01.2019 um 23:02 schrieb Marek Vasut: >>>> On 1/11/19 9:39 PM, Simon

Re: [U-Boot] [PATCH v1 1/4] arm: socfpga: imply SPL config instead of select

Hi Simon, On 1/14/19 9:50 AM, Simon Goldschmidt wrote: > Am 11.01.2019 um 23:02 schrieb Marek Vasut: >> On 1/11/19 9:39 PM, Simon Goldschmidt wrote: >>> Am 07.01.2019 um 23:53 schrieb Marek Vasut: On 1/7/19 10:14 PM, Simon Goldschmidt wrote: > In order to build a smaller SPL, let's imply

Re: [U-Boot] [PATCH] net: phy: add TSE PCS support to dwmac-socfpga

On 09/25/2018 10:00 AM, Dinh Nguyen wrote: > > > On 09/25/2018 01:24 AM, Ooi, Joyce wrote: >> This adds support for TSE PCS that uses SGMII adapter when the >> phy-mode in device tree is set to sgmii. > > Can you add a bit more description to your commit message?

Re: [U-Boot] [PATCH] net: phy: add TSE PCS support to dwmac-socfpga

On 09/25/2018 01:24 AM, Ooi, Joyce wrote: > This adds support for TSE PCS that uses SGMII adapter when the > phy-mode in device tree is set to sgmii. Can you add a bit more description to your commit message? TSE(Triple Speed Ethernet), but what is PCS? > > Signed-off-by: Ooi, Joyce > --- >

Re: [U-Boot] [PATCH 5/5] arm: dts: socfpga: stratix10: update pdma

On 07/10/2018 08:11 AM, Chee, Tien Fong wrote: > On Mon, 2018-07-09 at 22:28 +0200, Marek Vasut wrote: >> On 07/09/2018 08:03 PM, Dinh Nguyen wrote: >>> >>> >>> >>> On 05/31/2018 03:08 AM, tien.fong.c...@intel.com wrote: >>>> &g

Re: [U-Boot] [PATCH 5/5] arm: dts: socfpga: stratix10: update pdma

On 05/31/2018 03:08 AM, tien.fong.c...@intel.com wrote: > From: Tien Fong Chee > > Update pdma properties for Stratix 10 > > Signed-off-by: Tien Fong Chee > --- > arch/arm/dts/socfpga_stratix10.dtsi | 20 > 1 file changed, 20 insertions(+) > > diff --git

Re: [U-Boot] [PATCH] ARM: dts: socfpga: Adjust NAND register layout on Arria10

On 05/29/2018 11:36 AM, Marek Vasut wrote: > Adjust the NAND register size on Arria10 to reflect reality. > > Signed-off-by: Marek Vasut > Cc: Chin Liang See > Cc: Dinh Nguyen > --- > arch/arm/dts/socfpga_arria10.dtsi | 4 ++-- > 1 file changed, 2 insertions(+),

Re: [U-Boot] [U-Boot, v3, 1/3] mmc: dwmmc: socfpga: Add reset ctrl to driver

-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 On 05/25/2018 06:16 AM, Tom Rini wrote: > On Fri, May 25, 2018 at 10:45:53AM +0800, Ley Foon Tan wrote: >> On Thu, May 24, 2018 at 8:39 PM, Tom Rini >> wrote: >>> On Tue, May 08, 2018 at 11:19:24AM +0800, Ley Foon Tan wrote: >>> Add code to

Re: [U-Boot] [PATCH v2 0/3] drivers: Add reset ctrl to drivers

On Fri, May 4, 2018 at 5:49 AM, Ley Foon Tan wrote: > Add reset ctrl to dwmmc socfpga, designware Ethernet and ns16550 serial > drivers. > > A reset property is an optional feature, so only print out a warning and > do not fail if a reset property is not present. > > If a

Re: [U-Boot] [RFC] spl: dw_mmc_socfpga: udevice structure is NULL in SPL

On 04/25/2018 09:26 PM, Ley Foon Tan wrote: > On Thu, Apr 26, 2018 at 10:24 AM, Dinh Nguyen <dingu...@kernel.org> wrote: >> Hi, >> >> I am trying to add support for the sdmmc driver to use the reset manager >> driver in SPL. But I'm noticing that t

[U-Boot] [RFC] spl: dw_mmc_socfpga: udevice structure is NULL in SPL

Hi, I am trying to add support for the sdmmc driver to use the reset manager driver in SPL. But I'm noticing that the udevice struct dev that passed into socfpga_dwmmc_probe() is NULL, thus, I can't use the reset_get_by_() functions to get the reset information because it needs the dev structure

Re: [U-Boot] [PATCHv1 14/14] reset: remove request and free functions

On 04/16/2018 01:51 PM, Stephen Warren wrote: > On 04/16/2018 12:43 PM, Simon Glass wrote: >> +Stephen for comment >> >> Hi Dinh, >> >> On 14 April 2018 at 12:51, Dinh Nguyen <dingu...@kernel.org> wrote: >>> The request and free reset function

Re: [U-Boot] [PATCHv1 14/14] reset: remove request and free functions

On 04/16/2018 01:43 PM, Simon Glass wrote: > +Stephen for comment > > Hi Dinh, > > On 14 April 2018 at 12:51, Dinh Nguyen <dingu...@kernel.org> wrote: >> The request and free reset functions are not really used for any useful >> purpose but for deb

[U-Boot] [PATCHv1 13/14] reset: test: remove sandbox_reset_test_free function

Remove sandbox_reset_test_free() because it calls reset_free, which is being removed. Signed-off-by: Dinh Nguyen <dingu...@kernel.org> --- arch/sandbox/include/asm/reset.h | 1 - drivers/reset/sandbox-reset-test.c | 7 --- test/dm/reset.c| 2 -- 3 files chang

[U-Boot] [PATCHv1 10/14] net: dwc_eth_qos: remove reset_free from driver

The call to free the reset control line is a deadend call that doesn't lead to any reset control functionality. Also the reset_free() function will be remove in a subsequent patch, so remove it here. Signed-off-by: Dinh Nguyen <dingu...@kernel.org> --- drivers/net/dwc_eth_qos.c | 4

[U-Boot] [PATCHv1 09/14] reset: sandbox: remove request and free functions

The request and free reset functions are not really used for any useful purpose but for debugging. We can safely remove them. Signed-off-by: Dinh Nguyen <dingu...@kernel.org> --- drivers/reset/sandbox-reset.c | 25 ++--- 1 file changed, 6 insertions(+), 19 deletions(-)

[U-Boot] [PATCHv1 08/14] reset: socfpga: remove request and free functions

The request and free reset functions are not really used for any useful purpose but for debugging. We can safely remove them. Signed-off-by: Dinh Nguyen <dingu...@kernel.org> --- drivers/reset/reset-socfpga.c | 18 -- 1 file changed, 18 deletions(-) diff --git a/drivers

[U-Boot] [PATCHv1 03/14] reset: uniphier: remove request and free functions

The request and free reset functions are not really used for any useful purpose but for debugging. We can safely remove them. Signed-off-by: Dinh Nguyen <dingu...@kernel.org> --- drivers/reset/reset-uniphier.c | 12 1 file changed, 12 deletions(-) diff --git a/drivers/reset

[U-Boot] [PATCHv1 12/14] usb: ehci/ohci: remove reset_free function

The call to free the reset control line is a deadend call that doesn't lead to any reset control functionality. Also the reset_free() function will be remove in a subsequent patch, so remove it here. Signed-off-by: Dinh Nguyen <dingu...@kernel.org> --- drivers/usb/host/ehci-generic

[U-Boot] [PATCHv1 14/14] reset: remove request and free functions

The request and free reset functions are not really used for any useful purpose but for debugging. We can safely remove them. Signed-off-by: Dinh Nguyen <dingu...@kernel.org> --- drivers/reset/reset-uclass.c | 28 include/reset-uclass.h

[U-Boot] [PATCHv1 05/14] reset: meson: remove request and free functions

The request and free reset functions are not really used for any useful purpose but for debugging. We can safely remove them. Signed-off-by: Dinh Nguyen <dingu...@kernel.org> --- drivers/reset/reset-meson.c | 18 +++--- 1 file changed, 3 insertions(+), 15 deletions(-) diff

[U-Boot] [PATCHv1 06/14] reset: bcm6345: remove request and free functions

The request and free reset functions are not really used for any useful purpose but for debugging. We can safely remove them. Signed-off-by: Dinh Nguyen <dingu...@kernel.org> --- drivers/reset/reset-bcm6345.c | 21 ++--- 1 file changed, 6 insertions(+), 15 deletions(-)

[U-Boot] [PATCHv1 11/14] phy: bcm63xx: remove reset_free function

The call to free the reset control line is a deadend call that doesn't lead to any reset control functionality. Also the reset_free() function will be remove in a subsequent patch, so remove it here. Signed-off-by: Dinh Nguyen <dingu...@kernel.org> --- drivers/phy/bcm6318-usbh-phy

[U-Boot] [PATCHv1 07/14] reset: ast2500: remove request function

The request reset function is not really used for any useful purpose except for debugging. We can safely remove it. Signed-off-by: Dinh Nguyen <dingu...@kernel.org> --- drivers/reset/ast2500-reset.c | 9 - 1 file changed, 9 deletions(-) diff --git a/drivers/reset/ast2500-res

[U-Boot] [PATCHv1 04/14] reset: rockchip: remove request and free functions

The request and free reset functions are not really used for any useful purpose but for debugging. We can safely remove them. Signed-off-by: Dinh Nguyen <dingu...@kernel.org> --- drivers/reset/reset-rockchip.c | 26 +++--- 1 file changed, 3 insertions(+), 23 del

[U-Boot] [PATCHv1 02/14] reset: sti: remove request and free functions

The request and free reset functions are not really used for any useful purpose but for debugging. We can safely remove them. Signed-off-by: Dinh Nguyen <dingu...@kernel.org> --- drivers/reset/sti-reset.c | 12 drivers/reset/stm32-reset.c | 12 2 files chang

  1   2   3   4   5   >