On 11/17/2017 11:04 AM, Marek Vasut wrote:
> On 11/17/2017 08:02 PM, Marek Vasut wrote:
>> On 11/17/2017 05:43 PM, York Sun wrote:
>>> On 09/12/2017 10:09 AM, Marek Vasut wrote:
>>>> The status register is optional in the AMD command sets, but it's
>>>>
On Nov 17, 2017, at 11:04, Marek Vasut
<marek.va...@gmail.com<mailto:marek.va...@gmail.com>> wrote:
On 11/17/2017 08:02 PM, Marek Vasut wrote:
On 11/17/2017 05:43 PM, York Sun wrote:
On 09/12/2017 10:09 AM, Marek Vasut wrote:
The status register is optional in the AMD command se
On 11/09/2017 02:39 AM, Prabhakar Kushwaha wrote:
> mac help does not reflect correct descriptions and parameter.
>
> So update mac help command.
>
> Signed-off-by: Prabhakar Kushwaha
> ---
Minor change to commit message.
Applied to fsl-qoriq master. Thanks.
York
On 11/09/2017 01:26 AM, Prabhakar Kushwaha wrote:
> Value provided in MC_MEM_SIZE_ENV_VAR is in hex.
>
> So provide 16 as base in simple_strtoul.
>
> Signed-off-by: Prabhakar Kushwaha
> ---
Minor change in commit message.
Applied to fsl-qoriq master. Thanks.
York
On 11/09/2017 02:16 AM, Shengzhou Liu wrote:
> Signed-off-by: Shengzhou Liu
> ---
This set is applied to fsl-qoriq master. Thanks.
York
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On 11/05/2017 11:48 PM, Ashish Kumar wrote:
> Signed-off-by: Ashish Kumar
> Signed-off-by: Prabhakar Kushwaha
> Signed-off-by: Raghav Dogra
> ---
> v6:
> Sorting defconfig with help make savedefconfig
>
Applied to
On 11/05/2017 11:49 PM, Ashish Kumar wrote:
> Distro boot support gives flexibility to run distro RFS like Ubuntu's
> being deployed from SD card or SATA drive. If it fails
> to detect external storage, fall back to qspi/sd boot.
>
> Enable this by default in RDB's defconfig by selecting
>
On 11/05/2017 11:48 PM, Ashish Kumar wrote:
> Signed-off-by: Prabhakar Kushwaha
> Signed-off-by: Ashish Kumar
> Signed-off-by: Raghav Dogra
> ---
> v6:
> Incorporation of review comments in README wrt to line wrap.
>
On 11/01/2017 09:20 PM, Ashish Kumar wrote:
> Signed-off-by: Ashish Kumar
> Signed-off-by: Amrita Kumari
> ---
> v2: Rebase to top
> v3: Consolidate defines in common file
> v4: Protect define using CONFIG_SCSI
Squashed with patch #1.
Applied to
On 10/30/2017 02:58 PM, Scott Wood wrote:
> On Mon, 2017-10-30 at 18:50 +0000, York Sun wrote:
>> On 10/20/2017 03:43 AM, Kurt Kanzenbach wrote:
>>> Currently the chipselect used to identify the corresponding NAND chip is
>>> stored
>>> at the controller a
On 10/29/2017 11:24 PM, Ashish Kumar wrote:
> Signed-off-by: Ashish Kumar
> ---
Applied to fsl-qoriq master. Thanks.
York
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On 10/26/2017 03:33 AM, Ashish Kumar wrote:
> Correcting error handing for qbman_swp_acquire. The return value is zero is
> an error condition since number of buffer copied is zero meaning
> there are no free buffers for allocation.
>
> Signed-off-by: Ashish Kumar
>
On 09/12/2017 10:09 AM, Marek Vasut wrote:
> The status register is optional in the AMD command sets, but it's
> presence can be checked by reading out CFI table entry 0xc bit 0.
> If the register is present, prefer using it's bit 7 to determine
> if the flash is busy over reading the flash ; this
Tom,
Passed compiling on travis,
https://travis-ci.org/yorksun/u-boot/builds/302640283, the following
changes since commit c253573f3e269fd9a24ee6684d87dd91106018a5:
Prepare v2017.11 (2017-11-13 20:08:06 -0500)
are available in the git repository at:
git://git.denx.de/u-boot-fsl-qoriq.git
On 11/13/2017 11:06 PM, Rajesh Bhagat wrote:
> Adds SERDES voltage and reset SERDES lanes API and makes
> enable/disable DDR controller support 0.9V API common.
>
> Signed-off-by: Ashish Kumar
> Signed-off-by: Rajesh Bhagat
> ---
> Changes in v6:
On 11/12/2017 09:30 PM, Rajesh Bhagat wrote:
> Adds SERDES voltage and reset SERDES lanes API and makes
> enable/disable DDR controller support 0.9V API common.
>
> Signed-off-by: Ashish Kumar
> Signed-off-by: Rajesh Bhagat
> ---
> Changes in v5:
On 11/12/2017 09:29 PM, Rajesh Bhagat wrote:
> Adds LTC3882 voltage regulator chip support in common VID driver.
> And adds VID support for LS1088A QDS and RDB platforms.
>
> Rajesh Bhagat (7):
> armv8: lsch3: Add serdes and DDR voltage setup
> board: common:vid: Add LS1088A VID Supported
On 11/08/2017 06:48 PM, Prabhakar Kushwaha wrote:
> Instruction prefetch feature is by default enabled during core
> release.
>
> This patch add support of disabling instruction prefetch by setting
> core mask in PPA. Here each core mask bit represents a core and
> prefetch is disabled at the
On 11/08/2017 09:16 PM, Ashish Kumar wrote:
> -Original Message-
> From: York Sun
> Sent: Thursday, November 09, 2017 2:07 AM
> To: Ashish Kumar <ashish.ku...@nxp.com>; u-boot@lists.denx.de
> Cc: joe.hershber...@ni.com; Prabhakar Kushwaha <prabhakar.kushw...@nxp.co
On 11/08/2017 01:30 PM, Joakim Tjernlund wrote:
> On Wed, 2017-11-08 at 21:05 +0000, York Sun wrote:
>> CAUTION: This email originated from outside of the organization. Do not
>> click links or open attachments unless you recognize the sender and know the
>> content is sa
-boot@lists.denx.de; Z.q. Hou
> <zhiqiang@nxp.com>; York Sun <york@nxp.com>; Xiaowei Bao
> <xiaowei@nxp.com>; hamish.mar...@alliedtelesis.co.nz; M.h. Lian
> <minghuan.l...@nxp.com>
> Subject: Re: [U-Boot] [PATCH 3/3] Powerpc: pcie: Make pcie link state
On 11/06/2017 01:09 AM, Ashish Kumar wrote:
> In case of PHY-less mode, there is no interaction with PHY
> so auto-neg etc is not required and link will have fixed
> attributes
>
> Signed-off-by: Ashish Kumar
> Signed-off-by: Prabhakar Kushwaha
On 11/07/2017 02:37 AM, Rajesh Bhagat wrote:
> Adds SERDES voltage and reset SERDES lanes API and makes
> enable/disable DDR controller support 0.9V API common.
>
> Signed-off-by: Ashish Kumar
> Signed-off-by: Rajesh Bhagat
> ---
> Changes in v4:
On 11/05/2017 11:48 PM, Ashish Kumar wrote:
> Signed-off-by: Prabhakar Kushwaha
> Signed-off-by: Ashish Kumar
> Signed-off-by: Raghav Dogra
> ---
> v6:
> Incorporation of review comments in README wrt to line wrap.
>
On 11/01/2017 09:20 PM, Ashish Kumar wrote:
> Signed-off-by: Ashish Kumar
> ---
>
> v3: Change SCSI command to imply SCSI
> v4: No change
>
> arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git
On 11/06/2017 10:37 PM, Ashish Kumar wrote:
> Hello York,
>
> Please see inline.
Please avoid using this "inline" style and follow the list style when
you reply to any email.
>
> -Original Message-
> From: York Sun
> Sent: Tuesday, November 07,
On 11/05/2017 11:49 PM, Ashish Kumar wrote:
> Distro boot support gives flexibility to run distro RFS like Ubuntu's
> being deployed from SD card or SATA drive. If it fails
> to detect external storage, fall back to qspi/sd boot.
>
> Enable this by default in RDB's defconfig by selecting
>
On 11/01/2017 04:19 AM, Shengzhou Liu wrote:
>
> York,
> please drop this version, I will update it and send next new version to add
> distro secureboot together.
>
Shengzhou,
Do not mark the patch as "superseded" if you haven't sent a new version.
You can mark it as "Not Applicable"
On 11/01/2017 09:20 PM, Ashish Kumar wrote:
> Signed-off-by: Ashish Kumar
> Signed-off-by: Amrita Kumari
> ---
> v2: Rebase to top
> v3: Consolidate defines in common file
> v4: Protect define using CONFIG_SCSI
>
Andy,
Does this set represent the
On 11/01/2017 09:21 PM, Ashish Kumar wrote:
> Signed-off-by: Prabhakar Kushwaha
> Signed-off-by: Ashish Kumar
> Signed-off-by: Raghav Dogra
> ---
>
> v5:
> Rewording and incorporation of review comments in README
> Move
On 11/01/2017 10:48 PM, Ashish Kumar wrote:
> Disto boot support give flexibility to run distro RFS like ubuntu's
s/Disto/Distro
s/give/gives
S/ubuntu/Ubuntu
> being deployed from SD card or USB stick. If it fails
> to detect external storage, fall back to qspi/sd boot.
>
> Signed-off-by:
On 11/01/2017 10:48 PM, Ashish Kumar wrote:
> Signed-off-by: Ashish Kumar
> ---
> configs/ls1088ardb_qspi_defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/configs/ls1088ardb_qspi_defconfig
> b/configs/ls1088ardb_qspi_defconfig
> index db15d31..6ec949c
On 10/31/2017 02:55 AM, Ashish Kumar wrote:
> Signed-off-by: Ashish Kumar
> Signed-off-by: Amrita Kumari
> ---
> v2: Rebase to top
> v3: Consolidate defines in common file
>
> include/configs/ls1088a_common.h | 11 +++
> 1 file changed, 11
On 09/07/2017 10:54 PM, Sumit Garg wrote:
> Enable validation of boot.scr script prior to its execution dependent
> on "secureboot" flag in environment. Enable fall back option to
> qspi boot in case of secure boot.
>
> Signed-off-by: Sumit Garg
> Tested-by: Vinitha Pillai
the way ETH connector LEDs blink.
>
> Signed-off-by: Lukasz Majewski <lu...@denx.de>
>
> ---
>
> Changes in v3:
> - Enable extended registers access only for 88E151x family of PHYs
>
> Changes in v2:
> - Provide the readext and writeext callbacks t
On 10/30/2017 12:06 PM, York Sun wrote:
> On 10/29/2017 11:40 PM, Ashish Kumar wrote:
>> Signed-off-by: Amrita Kumari <amrita.kum...@nxp.com>
>> Signed-off-by: Ashish Kumar <ashish.ku...@nxp.com>
>> ---
>
> Change log?
>
>> include/configs/ls1088
On 10/29/2017 11:40 PM, Ashish Kumar wrote:
> Signed-off-by: Amrita Kumari
> Signed-off-by: Ashish Kumar
> ---
Change log?
> include/configs/ls1088ardb.h | 13 +
> 1 file changed, 13 insertions(+)
>
> diff --git
On 10/29/2017 10:23 PM, Ashish Kumar wrote:
> Hello York,
>
> The definition of qbman_swp_acquire(), is not owned by u-boot, it is part of
> qbman drivers which is owned by Roy.
> u-boot gets this definition from flib code and same is used in u-boot as it
> is.
>
> So, moving this error
On 10/26/2017 02:46 AM, andy.t...@nxp.com wrote:
> From: Yuantian Tang
>
> Enable sata feature on ls1088a platforms
>
> Signed-off-by: Tang Yuantian
> ---
> include/configs/ls1088aqds.h | 12
> include/configs/ls1088ardb.h | 13 +
On 10/20/2017 03:43 AM, Kurt Kanzenbach wrote:
> Currently the chipselect used to identify the corresponding NAND chip is
> stored
> at the controller and only set during fsl_ifc_chip_init(). This way, only the
> last NAND chip is working, as the previous value of cs_nand gets overwritten.
>
>
On 10/23/2017 01:53 PM, York Sun wrote:
> On 09/14/2017 02:26 PM, York Sun wrote:
>> On 08/30/2017 03:43 AM, Shengzhou Liu wrote:
>>> Signed-off-by: Shengzhou Liu <shengzhou@nxp.com>
>>> ---
>>> include/configs/ls1043a_common.h | 11 ++-
On 10/09/2017 02:09 AM, Calvin Johnson wrote:
> This patch adds PFE driver into U-Boot.
>
> Following are the main driver files:-
> pfe.c: provides low level helper functions to initialize PFE internal
> processor engines and other hardware blocks.
> pfe_driver.c: provides probe functions,
On 09/01/2017 01:25 AM, Sumit Garg wrote:
> Enable support for loadables in SEC firmware FIT image. Currently support
> is added for single loadable image.
>
> Brief description of implementation:
> - Add two more address pointers (loadable_h, loadable_l) as arguments to
> sec_firmware_init()
On 09/01/2017 01:24 AM, Sumit Garg wrote:
> Change DDR allocated for secure memory from 2 MB to 66 MB. This additional
> 64 MB secure memory is required for trusted OS running in Trusted Execution
> Environment using ARMv8 TrustZone.
>
> Signed-off-by: Sumit Garg
> ---
On 10/22/2017 07:28 PM, Ran Wang wrote:
> Use Kconfig to select QE-HDLC and USB pin-mux.
>
> Signed-off-by: Ran Wang
> Reviewed-by: Bin Meng
> ---
> Change in v4:
> Typo correction.
>
> Change in v3:
> New patch file.
>
This set is
On 10/12/2017 02:51 AM, Ashish Kumar wrote:
> Since TX delay is now enabled only in PHY_INTERFACE_MODE_RGMII_ID
> PHY_INTERFACE_MODE_RGMII_TXID.
>
> These change where introduced in phy driver in commit titled
> "net: phy: realtek: fix enabling of the TX-delay for RTL8211F"
>
> Signed-off-by:
On 10/11/2017 11:47 PM, andy.t...@nxp.com wrote:
> From: Yuantian Tang
>
> On ls1012a soc, core clock source frequency is 100Mhz.
> Generic timer frequency is derived from core clock source divided
> by 4, which is 25Mhz. So assign timer frequency to 25Mhz here.
>
>
On 10/11/2017 06:07 AM, Ashish Kumar wrote:
> Signed-off-by: Ashish Kumar
> ---
> v2:
> Reword commit msg
>
Applied to fsl-qoriq master. Thanks.
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On 10/10/2017 08:21 PM, Prabhakar Kushwaha wrote:
> Memory allocated via malloc is not guaranteed to be zeroized.
>
> So explicitly use calloc instead of malloc.
>
> Signed-off-by: Prabhakar Kushwaha
> ---
> Changes for v2: Replaced malloc/memset with calloc
>
On 10/17/2017 08:19 AM, York Sun wrote:
> Commit 06ad970b53a3 ("powerpc: mpc85xx: Implemente workaround for CPU
> erratum A-007907") clears L1CSR2 for the boot core, but other cores
> don't run through the workaround. Add similar code for secondary
> cores to clear DCS
On 10/30/2017 10:55 AM, Jagan Teki wrote:
> On Mon, Oct 30, 2017 at 11:19 PM, York Sun <york@nxp.com> wrote:
>> On 10/30/2017 10:17 AM, Jagan Teki wrote:
>>> Hi,
>>>
>>> Did anyone have tested falcon recently? it was working for me during
>>>
ons '')
[0.00] bootconsole [uart8250] enabled
Starting logging: OK
Initializing random number generator... done.
Starting network: OK
Welcome to Buildroot
buildroot login:
I have a local commit to adjust the image size. My git log is
commit a1a577912fe17f9ff75e07661d9eb61f15e45
On 10/30/2017 03:34 AM, Lukasz Majewski wrote:
> Hi York,
>
>> On 10/27/2017 08:23 AM, Lukasz Majewski wrote:
>>> On Fri, 27 Oct 2017 15:06:37 +
>>> York Sun <york@nxp.com> wrote:
>>>
>>>> On 10/27/2017 02:12 AM, Lukasz Ma
On 10/30/2017 03:31 AM, Ashish Kumar wrote:
> Signed-off-by: Prabhakar Kushwaha
> Signed-off-by: Ashish Kumar
> Signed-off-by: Raghav Dogra
> ---
>
> v4:
> Add Documentation for SD boot
> Rebase to top
>
>
: ls1088ardb: Enable USB command RDB qspi-boot
armv8: ls1088aqds: Enable USB command on QDS for qspi-boot
Sumit Garg (2):
armv8: layerscape: Allocate 66 MB DDR for secure memory
armv8: sec_firmware: Add support for loadables in FIT
York Sun (1):
powerpc: mpc85xx: Implement CPU
On 10/27/2017 08:23 AM, Lukasz Majewski wrote:
> On Fri, 27 Oct 2017 15:06:37 +
> York Sun <york@nxp.com> wrote:
>
>> On 10/27/2017 02:12 AM, Lukasz Majewski wrote:
>>> This commit allows extended Marvell registers to be read with:
>>>
>>>
On 10/27/2017 02:12 AM, Lukasz Majewski wrote:
> This commit allows extended Marvell registers to be read with:
>
> foo > mdio rx FEC 3.10
> Reading from bus FEC
> PHY at address 0:
> 3.16 - 0x1063
> foo > mdio wx FEC 3.10 0x1011
>
> The above code changes the way ETH connector LEDs blink.
>
>
On 10/26/2017 08:16 AM, Lukasz Majewski wrote:
> On Thu, 26 Oct 2017 17:15:19 +0200
> Lukasz Majewski <lu...@denx.de> wrote:
>
>> On Thu, 26 Oct 2017 15:05:18 +
>> York Sun <york@nxp.com> wrote:
>>
>>> On 09/29/2017 07:48 AM, Lukasz Majewski
ls1043a_common.h | 1 -
> include/configs/nsa310s.h| 1 -
> include/configs/pengwyn.h| 3 ---
> include/configs/salvator-x.h | 1 -
> include/configs/ulcb.h | 1 -
> include/configs/xilinx_zynqmp.h | 1 -
> 12 files
On 10/26/2017 03:33 AM, Ashish Kumar wrote:
> Correcting error handing for qbman_swp_acquire. The return value is zero is
> an error condition since number of buffer copied is zero meaning
> there are no free buffers for allocation.
>
> Signed-off-by: Ashish Kumar
>
L2 cache */
> #define CONFIG_BTB /* toggle branch predition */
>
> -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
>
> #define CONFIG_ENABLE_36BIT_PHYS
>
>
Reviewed-by: York Sun <york@nxp.com>
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On 09/29/2017 07:48 AM, Lukasz Majewski wrote:
> This commit allows extended Marvell registers to be read with:
>
> foo > mdio rx FEC 3.10
> Reading from bus FEC
> PHY at address 0:
> 3.16 - 0x1063
> foo > mdio wx FEC 3.10 0x1011
>
> The above code changes the way ETH connector LEDs blink.
>
>
On 10/24/2017 09:00 PM, Sumit Garg wrote:
>> -Original Message-
>> From: York Sun
>> Sent: Tuesday, October 24, 2017 8:00 PM
>> To: Sumit Garg <sumit.g...@nxp.com>; u-boot@lists.denx.de
>> Cc: Ruchika Gupta <ruchika.gu...@nxp.com>; Prabhakar Kus
On 10/23/2017 09:21 PM, Sumit Garg wrote:
>>
>> Sumit,
>>
>> If I understand you correctly, you are parsing the secure firmware FIT image
>> to
>> find the loadable node and store the 64-bit load address in the scratch
>> registers. How do you determine which scratch registers to use?
>>
>> York
On 10/15/2017 10:03 PM, Udit Agarwal wrote:
> Validates PPA, MC, DPC, Bootscript, DPL and Kernel images in ESBC phase
> using esbc_validate command. Add images validation in default environment
> under mcinitcmd prior to MC initialization.
>
> Add header address for PPA to be validated during
On 09/01/2017 01:25 AM, Sumit Garg wrote:
> Enable support for loadables in SEC firmware FIT image. Currently support
> is added for single loadable image.
>
> Brief description of implementation:
> - Add two more address pointers (loadable_h, loadable_l) as arguments to
> sec_firmware_init()
On 09/01/2017 01:24 AM, Sumit Garg wrote:
> Change DDR allocated for secure memory from 2 MB to 66 MB. This additional
> 64 MB secure memory is required for trusted OS running in Trusted Execution
> Environment using ARMv8 TrustZone.
>
> Signed-off-by: Sumit Garg
> ---
>
On 09/14/2017 02:26 PM, York Sun wrote:
> On 08/30/2017 03:43 AM, Shengzhou Liu wrote:
>> Signed-off-by: Shengzhou Liu <shengzhou@nxp.com>
>> ---
>> include/configs/ls1043a_common.h | 11 ++-
>> 1 file changed, 10 insertions(+), 1 deletion(-)
&
On 10/09/2017 02:09 AM, Calvin Johnson wrote:
> Hi,
>
> This patch series introduces U-Boot support for NXP's LS1012A Packet
> Forwarding
> Engine (pfe_eth). LS1012A uses hardware packet forwarding engine to provide
> high performance Ethernet interfaces. The device includes two Ethernet ports.
Commit 06ad970b53a3 ("powerpc: mpc85xx: Implemente workaround for CPU
erratum A-007907") clears L1CSR2 for the boot core, but other cores
don't run through the workaround. Add similar code for secondary
cores to clear DCSTASHID field in L1CSR2 register.
Signed-off-by: York Sun <yor
On 10/15/2017 10:04 PM, Udit Agarwal wrote:
> Adds config CONFIG_FSL_LS_PPA and CONFIG_FSL_CAAM in
> LS2080AQDS and LS2080ARDB secure boot defconfig.
>
> Removes CONFIG_FIT, as not required when CONFIG_FSL_LS_PPA
> is enabled.
Your reason is wrong. With CONFIG_FSL_LS_PPA enabled, CONFIG_FIT is
On 09/28/2017 08:42 AM, York Sun wrote:
> Commit 15eb1d43bf47 ("spl: reorder the assignment of board info to
> global data") intended to move assignment of board info earlier,
> into board_init_r(). However, function preload_console_init() is
> called either from sp
On 10/04/2017 11:57 PM, Bogdan Purcareata wrote:
> The MC boot sequence is contained in mc_env_boot. Update LS1088A boards
> to use this function, and hook it to reset_phy so that it's called late
> enough, after the ports have been initialized, for proper DPC / DPL
> fixup.
>
> Signed-off-by:
On 10/03/2017 03:16 AM, Sumit Garg wrote:
> This change is required due to trusted OS (OP-TEE) not being position
> independent code, it requires compile time fixed base address.
>
> To take care of this it is assumed that all layerscape armv8 platforms
> has minimum 2G ddr in first region. So we
On 09/28/2017 09:24 AM, Fabio Estevam wrote:
> CONFIG_CMD_BOOTZ symbol does not work in board config file
> anymore, so fix this by moving it to Kconfig.
>
> Signed-off-by: Fabio Estevam
> ---
Applied to fsl-qoriq master. Thanks.
York
On 09/22/2017 12:39 AM, Ran Wang wrote:
> Rx Compliance tests may fail intermittently at high
> jitter frequencies using default register values.
>
> Program register USB_PHY_RX_OVRD_IN_HI in certain sequence
> to make the Rx compliance test pass.
>
> Signed-off-by: Ran Wang
On 09/18/2017 02:16 AM, Gong Qianyu wrote:
> Fix a bug of 'commit 8104deb2d6b7 ("armv8: layerscape: Adjust memory
> mapping for Flash/SD card on LS1046A")' as NAND block size is
> 256KB on LS1046AQDS.
>
> Signed-off-by: Gong Qianyu
> ---
Applied to fsl-qoriq master. Thanks.
Qianyu (1):
armv8: ls1046aqds: Fix NAND offset for Fman ucode and env
Ran Wang (1):
armv8: Apply workaround for USB erratum A-009007 to LS1088A
Sumit Garg (1):
armv8: fsl-layerscape: Allocate Secure memory from first ddr region
York Sun (7):
spl: fix assignment of board
On 10/08/2017 11:48 PM, andy.t...@nxp.com wrote:
> From: Yuantian Tang
>
> Generic Timer frequency should be 25Mhz. Current setting is
> CONFIG_SYS_CLK_FREQ/4 which is about 31Mhz, which is not correct.
> So correct it.
>
> Signed-off-by: Tang Yuantian
>
On 09/24/2017 08:44 PM, Bao Xiaowei wrote:
> For some special reset times for longer pcie devices, in this case, the
> pcie device may on polling compliance state, the RC considers the pcie
> device is link up, but the pcie device is not link up, only the L0 state
> is link up state. So add the
On 10/06/2017 03:50 AM, Bhaskar Upadhaya wrote:
>
>
> -Original Message-
> From: York Sun
> Sent: Wednesday, September 06, 2017 9:51 PM
> To: Bhaskar Upadhaya <bhaskar.upadh...@nxp.com>; u-boot@lists.denx.de
> Subject: Re: [PATCH 1/1] armv8: ls1012a: Memory
On 10/06/2017 04:06 AM, Prabhakar Kushwaha wrote:
> Memory allocated via malloc is not guaranteed to be zeroized.
>
> So explicitly memset the memory allocated via malloc.
>
> Signed-off-by: Prabhakar Kushwaha
> ---
Have you tried calloc()?
York
On 10/05/2017 01:47 AM, Rajesh Bhagat wrote:
> Include common config_distro_defaults.h and config_distro_bootcmd.h
> for u-boot enviroments to support automatical distro boot which
> scan boot.scr from external storage devices(e.g. SD and USB)
> and execute autoboot script.
>
> Signed-off-by:
On 10/05/2017 01:47 AM, Rajesh Bhagat wrote:
> Include common config_distro_defaults.h and config_distro_bootcmd.h
> for u-boot enviroments to support automatical distro boot which
> scan boot.scr from external storage devices(e.g. SD and USB)
> and execute autoboot script.
>
> Signed-off-by:
On 10/03/2017 03:51 AM, Sumit Garg wrote:
>> -Original Message-
>> From: York Sun
>> Sent: Friday, September 15, 2017 2:08 AM
>> To: Sumit Garg <sumit.g...@nxp.com>; u-boot@lists.denx.de
>> Cc: Ruchika Gupta <ruchika.gu...@nxp.com>; Prabhak
On 08/31/2017 04:14 AM, Ashish Kumar wrote:
> Add SD boot support for LS1088ARDB
>
> Signed-off-by: Prabhakar Kushwaha
> Signed-off-by: Ashish Kumar
> Signed-off-by: Raghav Dogra
> ---
> v3:
> Depends upon
>
On 10/04/2017 02:10 AM, Bogdan Purcareata wrote:
> This patch follows the work of previous commits:
> 5707dfb02e drivers: net: fsl-mc: Fixup MAC addresses in DPC
> 33a8991a87 drivers: net: fsl-mc: Link MC boot to PHY_RESET_R
> 1161dbcc0a drivers: net: fsl-mc: Include MAC addr fixup to DPL
These
On 09/07/2017 02:54 AM, Rajesh Bhagat wrote:
> Include common config_distro_defaults.h and config_distro_bootcmd.h
> for u-boot enviroments to support automatical distro boot which
> scan boot.scr from external storage devices(e.g. SD and USB)
> and execute autoboot script.
>
> Signed-off-by:
On 09/07/2017 10:10 PM, Rajesh Bhagat wrote:
> Include common config_distro_defaults.h and config_distro_bootcmd.h
> for u-boot enviroments to support automatical distro boot which
> scan boot.scr from external storage devices(e.g. SD and USB)
> and execute autoboot script.
>
> Signed-off-by:
On 09/24/2017 08:44 PM, Bao Xiaowei wrote:
> For some special reset times for longer pcie devices, in this case, the
> pcie device may on polling compliance state, the RC considers the pcie
> device is link up, but the pcie device is not link up, only the L0 state
> is link up state. So add the
On 09/28/2017 08:42 AM, York Sun wrote:
> Commit 15eb1d43bf47 ("spl: reorder the assignment of board info to
> global data") intended to move assignment of board info earlier,
> into board_init_r(). However, function preload_console_init() is
> called either from sp
On 09/29/2017 09:06 AM, Łukasz Majewski wrote:
> Hi York,
>
>> On 09/29/2017 12:44 AM, Łukasz Majewski wrote:
>>> Hi York,
>>>
This board has soldered DDR chips. To reduce the SPL image size,
use static DDR setting instead of dynamic DDR driver.
>>>
>>> I'm just wondering - since your
On 09/29/2017 01:02 AM, Łukasz Majewski wrote:
> Hi York,
>
>> Add jump_to_image_linux() for arm64. Add "noreturn" flag to
>> armv8_switch_to_el2(). Add hooks to fsl-layerscape to enable falcon
>> boot.
>>
>> Signed-off-by: York Sun <
On 09/29/2017 12:44 AM, Łukasz Majewski wrote:
> Hi York,
>
>> This board has soldered DDR chips. To reduce the SPL image size,
>> use static DDR setting instead of dynamic DDR driver.
>
> I'm just wondering - since your board supports FIT in SPL, maybe it
> would be good to have a binary blob
e boot in this patch after rebasing to latest mater.
Recent change in SPL makes the image size bigger.
Relace getenv_f() with env_get_f() after rebasing to latet master.
York Sun (7):
spl: fix assignment of board info to global data
cmd: spl: fix compiling error when CONFIG_CMD_SPL_WRIT
CONFIG_SPL_BOARD_INIT is used for SPL boot. Enable it in defconfig
for LS1043ARDB SPL targets.
Signed-off-by: York Sun <york@nxp.com>
---
Changes in v3: None
Changes in v2: None
configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 1 +
configs/ls1043ardb_nand_defconfig
Add jump_to_image_linux() for arm64. Add "noreturn" flag to
armv8_switch_to_el2(). Add hooks to fsl-layerscape to enable falcon
boot.
Signed-off-by: York Sun <york@nxp.com>
Reviewed-by: Simon Glass <s...@chromium.org>
---
Changes in v3:
Fix typo in subject and other
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_OF_LIBFDT=y
Because environment variables are not avaiable during SPL stage for
SD boot, set "boot_os=y" as default.
Signed-off-by: York Sun <york@nxp.com>
Reviewed-by: Simon Glass <s...@chromium.org>
---
Changes in v3:
gd->ram_size is reduced in this function to reserve secure memory.
Avoid running this function again to further reduce memory size.
This fixes issue for SPL boot with PPA image loaded in which case
secure memory is incorrectly allocated due to repeated calling.
Signed-off-by: York Sun &l
This board has soldered DDR chips. To reduce the SPL image size,
use static DDR setting instead of dynamic DDR driver.
Signed-off-by: York Sun <york@nxp.com>
---
Changes in v3:
Minor cosmetic fix.
Changes in v2:
Drop checking secure boot in this patch after rebasing to latest mater.
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