Re: [PATCH] efi_loader: add some description about UEFI secure boot
On 2/7/20 6:14 AM, AKASHI Takahiro wrote: A small text in docs/uefi/uefi.rst was added to explain how we can configure and utilise UEFI secure boot feature on U-Boot. Signed-off-by: AKASHI Takahiro --- doc/uefi/uefi.rst | 77 +++ 1 file changed, 77 insertions(+) diff --git a/doc/uefi/uefi.rst b/doc/uefi/uefi.rst index a8fd886d6b5e..98cd770aefe5 100644 --- a/doc/uefi/uefi.rst +++ b/doc/uefi/uefi.rst @@ -97,6 +97,83 @@ Below you find the output of an example session starting GRUB:: See doc/uImage.FIT/howto.txt for an introduction to FIT images. +Configuring UEFI secure boot + + +UEFI specification[1] defines a secure way of executing UEFI images +by verifying a signature (or message digest) of image with certificates. +This feature on U-Boot is enabled with:: + +CONFIG_UEFI_SECURE_BOOT=y + +To make the boot sequence safe, you need to establish a chain of trust; +In UEFI secure boot, you can make it with the UEFI variables, "PK" +(Platform Key), "KEK" (Key Exchange Keys), "db" (white list database) +and "dbx" (black list database). + +There are many online documents that describe what UEFI secure boot is +and how it works. Please consult some of them for details. + +Here is a simple example that you can follow for your initial attempt +(Please note that the actual steps would absolutely depend on your system +and environment.): + +1. Install utility commands on your host +* openssl +* efitools +* sbsigntool + +2. Create signing keys and key database files on your host +for PK:: + +$ openssl req -x509 -sha256 -newkey rsa:2048 -subj /CN=TEST_PK/ \ +-keyout PK.key -out PK.crt -nodes -days 365 +$ cert-to-efi-sig-list -g ----123456789abc \ +PK.crt PK.esl; +$ sign-efi-sig-list -c PK.crt -k PK.key PK PK.esl PK.auth + +for KEK:: + +$ openssl req -x509 -sha256 -newkey rsa:2048 -subj /CN=TEST_KEK/ \ +-keyout KEK.key -out KEK.crt -nodes -days 365 +$ cert-to-efi-sig-list -g ----123456789abc \ +KEK.crt KEK.esl +$ sign-efi-sig-list -c PK.crt -k PK.key KEK KEK.esl KEK.auth + +for db:: + +$ openssl req -x509 -sha256 -newkey rsa:2048 -subj /CN=TEST_db/ \ +-keyout db.key -out db.crt -nodes -days 365 +$ cert-to-efi-sig-list -g ----123456789abc \ +db.crt db.esl +$ sign-efi-sig-list -c KEK.crt -k KEK.key db db.esl db.auth Hello Takahiro, do you have a link to the public key of the Microsoft CA that shim is signed with? Isn't this what many users would add here? Best regards Heinrich + +Copy \*.auth to media, say mmc, that is accessible from U-Boot. + +3. Sign an image with one key in "db" on your host:: + +$ sbsign --key db.key --cert db.crt helloworld.efi + +4. Install keys on your board:: + +==> fatload mmc 0:1 PK.auth +==> setenv -e -nv -bs -rt -at -i ,$filesize PK +==> fatload mmc 0:1 KEK.auth +==> setenv -e -nv -bs -rt -at -i ,$filesize KEK +==> fatload mmc 0:1 db.auth +==> setenv -e -nv -bs -rt -at -i ,$filesize db + +5. Set up boot parameters on your board:: + +==> efidebug boot add 1 HELLO mmc 0:1 /helloworld.efi.signed "" + +Then your board runs that image from Boot manager (See below). +You can also try this sequence by running Pytest, test_efi_secboot, +on sandbox:: + +$ cd +$ pytest.py test/py/tests/test_efi_secboot/test_signed.py --bd sandbox + Executing the boot manager ~~
[PATCH] dm: make uclass_find_first_device() return error when no defice is found
uclass_find_first_device() succeeds even if it cannot find any device. So, the caller must check the return code and also *devp is not NULL. Returning -ENODEV will be sensible in this case. Signed-off-by: Masahiro Yamada --- If this patch is acceptable, I want to fold this into my pull request because it need it for my another patch: http://patchwork.ozlabs.org/patch/1238000/ drivers/core/uclass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c index 58b19a421091..3580974f3b85 100644 --- a/drivers/core/uclass.c +++ b/drivers/core/uclass.c @@ -227,7 +227,7 @@ int uclass_find_first_device(enum uclass_id id, struct udevice **devp) if (ret) return ret; if (list_empty(>dev_head)) - return 0; + return -ENODEV; *devp = list_first_entry(>dev_head, struct udevice, uclass_node); -- 2.17.1
Re: [PATCH v5 07/16] efi_loader: image_loader: support image authentication
On Tue, Feb 25, 2020 at 07:40:01AM +0100, Heinrich Schuchardt wrote: > On 2/25/20 6:25 AM, AKASHI Takahiro wrote: > > On Mon, Feb 24, 2020 at 07:29:17PM +0100, Heinrich Schuchardt wrote: > > > On 1/28/20 9:25 AM, AKASHI Takahiro wrote: > > > > With this commit, image validation can be enforced, as UEFI > > > > specification > > > > section 32.5 describes, if CONFIG_EFI_SECURE_BOOT is enabled. > > > > > > > > Currently we support > > > > * authentication based on db and dbx, > > > > so dbx-validated image will always be rejected. > > > > * following signature types: > > > > EFI_CERT_SHA256_GUID (SHA256 digest for unsigned images) > > > > EFI_CERT_X509_GUID (x509 certificate for signed images) > > > > Timestamp-based certificate revocation is not supported here. > > > > > > > > Internally, authentication data is stored in one of certificates tables > > > > of PE image (See efi_image_parse()) and will be verified by > > > > efi_image_authenticate() before loading a given image. > > > > > > > > It seems that UEFI specification defines the verification process > > > > in a bit ambiguous way. I tried to implement it as closely to as > > > > EDK2 does. > > > > > > > > Signed-off-by: AKASHI Takahiro > > > > > > According to git bisect this patch breaks the test > > > test/py/tests/test_efi_fit.py. > > > > This error only occurs on "compressed" FIT images. While I'm not sure > > whether it is directly related to efi support in bootm or not, I've > > fixed it any way. > > Hello Takahiro, > > where can I find the fix? Only in my local repository. Since I'm running Travis CI now, I will post a new version once the test is completed AND if you have no more comments on my v5. Thanks, -Takahiro Akashi > Best regards > > Heinrich > > > > > Thanks, > > -Takahiro Akashi > > > > > > > Best regards > > > > > > Heinrich >
Re: [PATCH v5 04/16] efi_loader: variable: support variable authentication
On 1/28/20 9:25 AM, AKASHI Takahiro wrote:
With this commit, EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS
is supported for authenticated variables and the system secure state
will transfer between setup mode and user mode as UEFI specification
section 32.3 describes.
Internally, authentication data is stored as part of authenticated
variable's value. It is nothing but a pkcs7 message (but we need some
wrapper, see efi_variable_parse_signature()) and will be validated by
efi_variable_authenticate(), hence efi_signature_verify_with_db().
Associated time value will be encoded in "{...,time=...}" along with
other UEFI variable's attributes.
Signed-off-by: AKASHI Takahiro
---
include/efi_loader.h | 3 +
lib/efi_loader/efi_variable.c | 665 --
2 files changed, 564 insertions(+), 104 deletions(-)
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 34f7b8eec8cd..f461c6195834 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -184,6 +184,7 @@ extern const efi_guid_t efi_guid_image_security_database;
extern const efi_guid_t efi_guid_sha256;
extern const efi_guid_t efi_guid_cert_x509;
extern const efi_guid_t efi_guid_cert_x509_sha256;
+extern const efi_guid_t efi_guid_cert_type_pkcs7;
/* GUID of RNG protocol */
extern const efi_guid_t efi_guid_rng_protocol;
@@ -738,6 +739,8 @@ efi_status_t efi_image_region_add(struct efi_image_regions
*regs,
void efi_sigstore_free(struct efi_signature_store *sigstore);
struct efi_signature_store *efi_sigstore_parse_sigdb(u16 *name);
+
+bool efi_secure_boot_enabled(void);
#endif /* CONFIG_EFI_SECURE_BOOT */
#else /* CONFIG_IS_ENABLED(EFI_LOADER) */
diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c
index c316bdfec0e4..2ae8222b1a94 100644
--- a/lib/efi_loader/efi_variable.c
+++ b/lib/efi_loader/efi_variable.c
@@ -10,8 +10,14 @@
#include
#include
#include
+#include
#include
+#include
#include
+#include "../lib/crypto/pkcs7_parser.h"
+
+const efi_guid_t efi_guid_cert_type_pkcs7 = EFI_CERT_TYPE_PKCS7_GUID;
+static bool efi_secure_boot;
#define READ_ONLY BIT(31)
@@ -108,7 +114,7 @@ static const char *prefix(const char *str, const char
*prefix)
* @attrp:pointer to UEFI attributes
* Return:pointer to remainder of U-Boot variable value
*/
-static const char *parse_attr(const char *str, u32 *attrp)
+static const char *parse_attr(const char *str, u32 *attrp, u64 *timep)
./lib/efi_loader/efi_variable.c:128: warning: Function parameter or
member 'timep' not described in 'parse_attr'
All 'make htmldocs' warnings will be treated as errors after upcoming
Travis CI changes.
Best regards
Heinrich
{
u32 attr = 0;
char sep = '{';
@@ -131,6 +137,12 @@ static const char *parse_attr(const char *str, u32 *attrp)
attr |= EFI_VARIABLE_BOOTSERVICE_ACCESS;
} else if ((s = prefix(str, "run"))) {
attr |= EFI_VARIABLE_RUNTIME_ACCESS;
+ } else if ((s = prefix(str, "time="))) {
+ attr |=
EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS;
+ hex2bin((u8 *)timep, s, sizeof(*timep));
+ s += sizeof(*timep) * 2;
+ } else if (*str == '}') {
+ break;
} else {
printf("invalid attribute: %s\n", str);
break;
@@ -148,48 +160,291 @@ static const char *parse_attr(const char *str, u32
*attrp)
}
/**
- * efi_get_variable() - retrieve value of a UEFI variable
+ * efi_secure_boot_enabled - return if secure boot is enabled or not
*
- * This function implements the GetVariable runtime service.
+ * Return: true if enabled, false if disabled
+ */
+bool efi_secure_boot_enabled(void)
+{
+ return efi_secure_boot;
+}
+
+#ifdef CONFIG_EFI_SECURE_BOOT
+static u8 pkcs7_hdr[] = {
+ /* SEQUENCE */
+ 0x30, 0x82, 0x05, 0xc7,
+ /* OID: pkcs7-signedData */
+ 0x06, 0x09, 0x2a, 0x86, 0x48, 0x86, 0xf7, 0x0d, 0x01, 0x07, 0x02,
+ /* Context Structured? */
+ 0xa0, 0x82, 0x05, 0xb8,
+};
+
+/**
+ * efi_variable_parse_signature - parse a signature in variable
+ * @buf: Pointer to variable's value
+ * @buflen:Length of @buf
*
- * See the Unified Extensible Firmware Interface (UEFI) specification for
- * details.
+ * Parse a signature embedded in variable's value and instantiate
+ * a pkcs7_message structure. Since pkcs7_parse_message() accepts only
+ * pkcs7's signedData, some header needed be prepended for correctly
+ * parsing authentication data, particularly for variable's.
*
- * @variable_name: name of the variable
- * @vendor:vendor GUID
- * @attributes:attributes of the variable
- * @data_size: size of the buffer to which the variable value is copied
- * @data: buffer to which the variable value is
Re: [PATCH v5 07/16] efi_loader: image_loader: support image authentication
On 1/28/20 9:25 AM, AKASHI Takahiro wrote:
With this commit, image validation can be enforced, as UEFI specification
section 32.5 describes, if CONFIG_EFI_SECURE_BOOT is enabled.
Currently we support
* authentication based on db and dbx,
so dbx-validated image will always be rejected.
* following signature types:
EFI_CERT_SHA256_GUID (SHA256 digest for unsigned images)
EFI_CERT_X509_GUID (x509 certificate for signed images)
Timestamp-based certificate revocation is not supported here.
Internally, authentication data is stored in one of certificates tables
of PE image (See efi_image_parse()) and will be verified by
efi_image_authenticate() before loading a given image.
It seems that UEFI specification defines the verification process
in a bit ambiguous way. I tried to implement it as closely to as
EDK2 does.
Signed-off-by: AKASHI Takahiro
---
include/efi_loader.h | 13 +-
lib/efi_loader/efi_boottime.c | 10 +-
lib/efi_loader/efi_image_loader.c | 460 +-
3 files changed, 467 insertions(+), 16 deletions(-)
diff --git a/include/efi_loader.h b/include/efi_loader.h
index f461c6195834..0e15470d9c17 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
static inline int guidcmp(const void *g1, const void *g2)
{
@@ -263,6 +264,11 @@ struct efi_object {
enum efi_object_type type;
};
+enum efi_image_auth_status {
+ EFI_IMAGE_AUTH_FAILED = 0,
+ EFI_IMAGE_AUTH_PASSED,
+};
+
/**
* struct efi_loaded_image_obj - handle of a loaded image
*
@@ -282,6 +288,7 @@ struct efi_loaded_image_obj {
EFIAPI efi_status_t (*entry)(efi_handle_t image_handle,
struct efi_system_table *st);
u16 image_type;
+ enum efi_image_auth_status auth_status;
};
/**
@@ -414,7 +421,8 @@ efi_status_t efi_set_watchdog(unsigned long timeout);
/* Called from places to check whether a timer expired */
void efi_timer_check(void);
/* PE loader implementation */
-efi_status_t efi_load_pe(struct efi_loaded_image_obj *handle, void *efi,
+efi_status_t efi_load_pe(struct efi_loaded_image_obj *handle,
+void *efi, size_t efi_size,
struct efi_loaded_image *loaded_image_info);
/* Called once to store the pristine gd pointer */
void efi_save_gd(void);
@@ -741,6 +749,9 @@ void efi_sigstore_free(struct efi_signature_store
*sigstore);
struct efi_signature_store *efi_sigstore_parse_sigdb(u16 *name);
bool efi_secure_boot_enabled(void);
+
+bool efi_image_parse(void *efi, size_t len, struct efi_image_regions **regp,
+WIN_CERTIFICATE **auth, size_t *auth_len);
#endif /* CONFIG_EFI_SECURE_BOOT */
#else /* CONFIG_IS_ENABLED(EFI_LOADER) */
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index 1f598b357a5c..cc8cc4cb5408 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -1882,12 +1882,12 @@ efi_status_t EFIAPI efi_load_image(bool boot_policy,
efi_dp_split_file_path(file_path, , );
ret = efi_setup_loaded_image(dp, fp, image_obj, );
if (ret == EFI_SUCCESS)
- ret = efi_load_pe(*image_obj, dest_buffer, info);
+ ret = efi_load_pe(*image_obj, dest_buffer, source_size, info);
if (!source_buffer)
/* Release buffer to which file was loaded */
efi_free_pages((uintptr_t)dest_buffer,
efi_size_in_pages(source_size));
- if (ret == EFI_SUCCESS) {
+ if (ret == EFI_SUCCESS || ret == EFI_SECURITY_VIOLATION) {
info->system_table =
info->parent_handle = parent_image;
} else {
@@ -2885,10 +2885,16 @@ efi_status_t EFIAPI efi_start_image(efi_handle_t
image_handle,
EFI_ENTRY("%p, %p, %p", image_handle, exit_data_size, exit_data);
+ if (!efi_search_obj(image_handle))
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
+
/* Check parameters */
if (image_obj->header.type != EFI_OBJECT_TYPE_LOADED_IMAGE)
return EFI_EXIT(EFI_INVALID_PARAMETER);
+ if (image_obj->auth_status != EFI_IMAGE_AUTH_PASSED)
+ return EFI_EXIT(EFI_SECURITY_VIOLATION);
+
ret = EFI_CALL(efi_open_protocol(image_handle, _guid_loaded_image,
, NULL, NULL,
EFI_OPEN_PROTOCOL_GET_PROTOCOL));
diff --git a/lib/efi_loader/efi_image_loader.c
b/lib/efi_loader/efi_image_loader.c
index d5de6df16d84..f6b44cdd 100644
--- a/lib/efi_loader/efi_image_loader.c
+++ b/lib/efi_loader/efi_image_loader.c
@@ -10,7 +10,10 @@
#include
#include
#include
+#include
#include
+#include
+#include "../lib/crypto/pkcs7_parser.h"
const efi_guid_t efi_global_variable_guid = EFI_GLOBAL_VARIABLE_GUID;
const efi_guid_t
Re: [PATCH v5 07/16] efi_loader: image_loader: support image authentication
On 2/25/20 6:25 AM, AKASHI Takahiro wrote: On Mon, Feb 24, 2020 at 07:29:17PM +0100, Heinrich Schuchardt wrote: On 1/28/20 9:25 AM, AKASHI Takahiro wrote: With this commit, image validation can be enforced, as UEFI specification section 32.5 describes, if CONFIG_EFI_SECURE_BOOT is enabled. Currently we support * authentication based on db and dbx, so dbx-validated image will always be rejected. * following signature types: EFI_CERT_SHA256_GUID (SHA256 digest for unsigned images) EFI_CERT_X509_GUID (x509 certificate for signed images) Timestamp-based certificate revocation is not supported here. Internally, authentication data is stored in one of certificates tables of PE image (See efi_image_parse()) and will be verified by efi_image_authenticate() before loading a given image. It seems that UEFI specification defines the verification process in a bit ambiguous way. I tried to implement it as closely to as EDK2 does. Signed-off-by: AKASHI Takahiro According to git bisect this patch breaks the test test/py/tests/test_efi_fit.py. This error only occurs on "compressed" FIT images. While I'm not sure whether it is directly related to efi support in bootm or not, I've fixed it any way. Hello Takahiro, where can I find the fix? Best regards Heinrich Thanks, -Takahiro Akashi Best regards Heinrich
Re: [PATCH v5 07/16] efi_loader: image_loader: support image authentication
On Mon, Feb 24, 2020 at 07:29:17PM +0100, Heinrich Schuchardt wrote: > On 1/28/20 9:25 AM, AKASHI Takahiro wrote: > > With this commit, image validation can be enforced, as UEFI specification > > section 32.5 describes, if CONFIG_EFI_SECURE_BOOT is enabled. > > > > Currently we support > > * authentication based on db and dbx, > >so dbx-validated image will always be rejected. > > * following signature types: > > EFI_CERT_SHA256_GUID (SHA256 digest for unsigned images) > > EFI_CERT_X509_GUID (x509 certificate for signed images) > > Timestamp-based certificate revocation is not supported here. > > > > Internally, authentication data is stored in one of certificates tables > > of PE image (See efi_image_parse()) and will be verified by > > efi_image_authenticate() before loading a given image. > > > > It seems that UEFI specification defines the verification process > > in a bit ambiguous way. I tried to implement it as closely to as > > EDK2 does. > > > > Signed-off-by: AKASHI Takahiro > > According to git bisect this patch breaks the test > test/py/tests/test_efi_fit.py. This error only occurs on "compressed" FIT images. While I'm not sure whether it is directly related to efi support in bootm or not, I've fixed it any way. Thanks, -Takahiro Akashi > Best regards > > Heinrich
Re: [PATCH v5 00/16] efi_loader: add secure boot support
On Sun, Feb 23, 2020 at 12:53:16PM +0100, Heinrich Schuchardt wrote: > On 1/28/20 9:25 AM, AKASHI Takahiro wrote: > > # Documentation for UEFI secure boot on U-Boot will be submitted in > > # a separate patch in near future. > > > > One of major missing features in current UEFI implementation is "secure > > boot." > > The ultimate goal of my attempt is to implement image authentication based > > on signature and provide UEFI secure boot support which would be fully > > compliant with UEFI specification, section 32[1]. > > (The code was originally developed by Patrick Wildt.) > > > > Please note, however, this patch doesn't work on its own; there are > > a couple of functional dependencies[2] and [3], that I have submitted > > before. For complete workable patch set, see my repository[4], > > which also contains experimental timestamp-based revocation suuport. > > > > My "non-volatile" support[5], which is under discussion, is not mandatory > > and so not included here, but this inevitably implies that, for example, > > signature database variables, like db and dbx, won't be persistent unless > > you explicitly run "env save" command. > > Anyhow, Linaro is also working on implementing real "secure storage" > > solution based on TF-A and OP-TEE. > > In the patch series I am missing a patch providing the documentation > explaining how to set up secure boot with U-Boot. doc/uefi/uefi.rst > would be a good place for it. See: https://lists.denx.de/pipermail/u-boot/2020-February/399446.html I posted this patch as a separate one because I believe that we can discuss separately from the code. -Takahiro Akashi > I guess the description should include: > > - which certificates have to be created and how to generate these > - which variables have to be initialized with which values > - how the images can be signed > > Best regards > > Heinrich > > > > > > > Supported features: > > * image authentication based on db and dbx > > * supported signature types are > > EFI_CERT_SHA256_GUID (SHA256 digest for unsigned images) > > EFI_CERT_X509_GUID (x509 certificate for signed images) > > * SecureBoot/SignatureSupport variables > > * SetupMode and user mode > > * variable authentication based on PK and KEK > > EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS > > * basic pytest test cases > > > > Unsupported features: (marked as TODO in most cases in the source code, > > and won't be included in this series) > > * hash algorithms other than SHA256 > > * dbt: timestamp(RFC6131)-based certificate revocation > > * dbr: OS recovery > > * xxxDefault: default values for signature stores > > * transition to AuditMode and DeployedMode > > * recording rejected images in EFI_IMAGE_EXECUTION_INFO_TABLE > > * verification "policy", in particular, check against signature's owner > > * private authenticated variables > > * variable authentication with EFI_VARIABLE_ENHANCED_AUTHENTICATED_ACCESS > > * real secure storage support, including hardware-specific PK (Platform Key) > >installation > > > > TODO's other than "Unsupported features": (won't be included in this series) > > * fail recovery, in particular, in modifying authenticated variables > > * support read-only attributes of well-defined global variables > >in particular, "SignatureSupport" > > * Extensive test suite (or more test cases) to confirm compatibility > >with EDK2 > > => I requested EDK SCT community to add tests[6]. > > > > Test: > > * My pytest, included in this patch set, passed. > > * efi_selftest passed. (At least no regression.) > > * Travis CI tests have passed. > > > > Known issues: > > * efitools is used in pytest, and its version must be v1.5.2 or later. > >(Solution: You can define EFITOOLS_PATH in defs.py for your own > > efitools.) > > > > > > Hints about how to use: > > (Please see other documents, or my pytest scripts, for details.) > > * You can create your own certificates with openssl. > > * You can sign your application with sbsign (on Ubuntu). > > * You can create raw data for signature database with efitools, and > >install/manage authenticated variables with "env -set -e" command > >or efitools' "UpdateVars.efi" application. > > > > > > [1] https://uefi.org/sites/default/files/resources/UEFI_Spec_2_8_final.pdf > > [2] https://lists.denx.de/pipermail/u-boot/2019-November/390127.html > > (import x509/pkcs7 parsers from linux) > > [3] https://lists.denx.de/pipermail/u-boot/2020-January/398057.html > > (extend rsa_verify() for UEFI secure boot) > > [4] http://git.linaro.org/people/takahiro.akashi/u-boot.git/ efi/secboot > > [5] https://lists.denx.de/pipermail/u-boot/2019-September/382835.html > > (non-volatile variables support) > > [6] https://bugzilla.tianocore.org/show_bug.cgi?id=2230 > > > > > > Changes in v5 (Jan 28, 2020) > > * rebased to pre-v2020.04-rc1 (fixed some merge conflicts) > > * remove already-merged commits (v4's patch#1) > > * fix
Re: [PATCH v5 16/16] travis: add packages for UEFI secure boot test
On Sun, Feb 23, 2020 at 12:46:22PM +0100, Heinrich Schuchardt wrote: > On 1/28/20 9:25 AM, AKASHI Takahiro wrote: > > Pytest for UEFI secure boot will use several host commands. > > In particular, Test setup relies on efitools, whose version must be v1.5.2 > > or later. So fetch a new version of deb package directly. > > Please note it has a dependency on mtools, which must also be installed > > along wih efitools. > > > > In addition, the path, '/sbin', is added to PATH for use of sgdisk and > > mkfs. > > > > Signed-off-by: AKASHI Takahiro > > You are adding some packages here. Don't you need the same packages in > the Docker image used by Gitlab CI and Azure CI? You're right, but I expect that Tom will take care of this as far as he remembers that he has said so. Thanks, -Takahiro Akashi > Cf. https://gitlab.denx.de/u-boot/gitlab-ci-runner > > Best regards > > Heinrich > > > --- > > .travis.yml | 11 ++- > > 1 file changed, 10 insertions(+), 1 deletion(-) > > > > diff --git a/.travis.yml b/.travis.yml > > index 3991eb7716fb..f0fed6d4b790 100644 > > --- a/.travis.yml > > +++ b/.travis.yml > > @@ -38,6 +38,14 @@ addons: > > - libisl15 > > - clang-7 > > - srecord > > +- coreutils > > +- util-linux > > +- dosfstools > > +- gdisk > > +- mount > > +- mtools > > +- openssl > > +- sbsigntool > > > > install: > ># Clone uboot-test-hooks > > @@ -58,10 +66,11 @@ install: > >- mkdir ~/grub2-arm64 > >- ( cd ~/grub2-arm64; wget -O - > > http://download.opensuse.org/ports/aarch64/distribution/leap/42.2/repo/oss/suse/aarch64/grub2-arm64-efi-2.02~beta2-87.1.aarch64.rpm > > | rpm2cpio | cpio -di ) > >- wget > > http://mirrors.kernel.org/ubuntu/pool/main/m/mpfr4/libmpfr4_3.1.4-1_amd64.deb > > && sudo dpkg -i libmpfr4_3.1.4-1_amd64.deb && rm libmpfr4_3.1.4-1_amd64.deb > > + - wget > > http://mirrors.kernel.org/ubuntu/pool/universe/e/efitools/efitools_1.8.1-0ubuntu2_amd64.deb > > && sudo dpkg -i efitools_1.8.1-0ubuntu2_amd64.deb && rm > > efitools_1.8.1-0ubuntu2_amd64.deb > > > > env: > > global: > > -- > > PATH=/tmp/qemu-install/bin:/tmp/uboot-test-hooks/bin:/usr/bin:/bin:/usr/local/bin > > +- > > PATH=/tmp/qemu-install/bin:/tmp/uboot-test-hooks/bin:/sbin:/usr/bin:/bin:/usr/local/bin > > - PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci > > - BUILD_DIR=build > > - HOSTCC="cc" > > >
[PATCH 2/2] video: meson: Use reserving memory function without kernel linear mapping
Memory reserved for the simple framebuffer should not be used
and part of memory linear mapping. See
https://patchwork.kernel.org/patch/10486131/ for more detailed
background information and discussion.
Signed-off-by: Michael Trimarchi
---
Changes RFC -> v1:
- Fix compilation issue on RFC
- change node name from display_reserved to display-reserved
---
drivers/video/meson/meson_vpu.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/video/meson/meson_vpu.c b/drivers/video/meson/meson_vpu.c
index 4eb66398d0..5bfad05d75 100644
--- a/drivers/video/meson/meson_vpu.c
+++ b/drivers/video/meson/meson_vpu.c
@@ -173,9 +173,9 @@ static void meson_vpu_setup_simplefb(void *fdt)
* at the end of the RAM and we strip this portion from the kernel
* allowed region
*/
- mem_start = gd->bd->bi_dram[0].start;
- mem_size = gd->bd->bi_dram[0].size - meson_fb.fb_size;
- ret = fdt_fixup_memory_banks(fdt, _start, _size, 1);
+ mem_start = meson_fb.base;
+ mem_size = meson_fb.fb_size;
+ ret = fdt_fixup_reserved_memory(fdt, "display-reserved", _start,
_size);
if (ret) {
eprintf("Cannot setup simplefb: Error reserving memory\n");
return;
--
2.17.1
[PATCH 1/2] common: fdt: Add a function for reserving memory without kernel linear mapping
The intent is to reserve memory _and_ prevent it from being included
in the kernel's linear map. For thos reason it is also necessary to include the
'no-map' property for this reserved-mem node.
>From Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt:
no-map (optional) - empty property
- Indicates the operating system must not create a virtual mapping
of the region as part of its standard mapping of system memory,
nor permit speculative access to it under any circumstances other
than under the control of the device driver using the region.
Signed-off-by: Michael Trimarchi
---
Changes: RFC->v1
- Add a better commit message
---
common/fdt_support.c | 40
include/fdt_support.h | 11 +++
2 files changed, 51 insertions(+)
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 02cf5c6241..a3662f4358 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -410,6 +410,46 @@ static int fdt_pack_reg(const void *fdt, void *buf, u64
*address, u64 *size,
return p - (char *)buf;
}
+int fdt_fixup_reserved_memory(void *blob, const char *area, u64 start[], u64
size[])
+{
+ int offs, len;
+ const char *subpath;
+ const char *path = "/reserved-memory";
+ fdt32_t address_cells = cpu_to_fdt32(fdt_address_cells(blob, 0));
+ fdt32_t size_cells = cpu_to_fdt32(fdt_size_cells(blob, 0));
+ u8 temp[16]; /* Up to 64-bit address + 64-bit size */
+
+ offs = fdt_path_offset(blob, path);
+ if (offs < 0) {
+ debug("Node %s not found\n", path);
+ path = "/";
+ subpath = "reserved-memory";
+ offs = fdt_path_offset(blob, path);
+ offs = fdt_add_subnode(blob, offs, subpath);
+ if (offs < 0) {
+ printf("Could not create %s%s node.\n", path, subpath);
+ return -1;
+ }
+ path = "/reserved-memory";
+ offs = fdt_path_offset(blob, path);
+
+ fdt_setprop(blob, offs, "#address-cells", _cells,
sizeof(address_cells));
+ fdt_setprop(blob, offs, "#size-cells", _cells,
sizeof(size_cells));
+ fdt_setprop(blob, offs, "ranges", NULL, 0);
+ }
+
+ offs = fdt_add_subnode(blob, offs, area ? : "private");
+ if (offs < 0) {
+ printf("Could not create %s%s node.\n", path, subpath);
+ return -1;
+ }
+
+ fdt_setprop(blob, offs, "no-map", NULL, 0);
+ len = fdt_pack_reg(blob, temp, start, size, 1);
+ fdt_setprop(blob, offs, "reg", temp, len);
+ return 0;
+}
+
#if CONFIG_NR_DRAM_BANKS > 4
#define MEMORY_BANKS_MAX CONFIG_NR_DRAM_BANKS
#else
diff --git a/include/fdt_support.h b/include/fdt_support.h
index ba14acd7f6..7c8a280f53 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -93,6 +93,17 @@ void do_fixup_by_compat_u32(void *fdt, const char *compat,
*/
int fdt_fixup_memory(void *blob, u64 start, u64 size);
+/**
+ * Setup the memory reserved node in the DT. Creates one if none was existing
before.
+ *
+ * @param blob FDT blob to update
+ * @param area Reserved area name
+ * @param startBegin of DRAM mapping in physical memory
+ * @param size Size of the single memory bank
+ * @return 0 if ok, or -1 or -FDT_ERR_... on error
+ */
+int fdt_fixup_reserved_memory(void *blob, const char *area, u64 start[], u64
size[]);
+
/**
* Fill the DT memory node with multiple memory banks.
* Creates the node if none was existing before.
--
2.17.1
[PATCH 0/2] Update reserved memory for simple framebuffer
Reserved memory for simple frame buffer should be created in a different
way:
+ aliases {
+ display0 =
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ display_reserved: framebuffer@86fa2000 {
+ reg = <0x86fa2000 0x8>;
+ no-map;
+ };
+
+ };
We add a function to change the loaded dts and inject those information.
I have added another patch for meson. Right now I'm testing on tinker-s
board.
Michael Trimarchi (2):
common: fdt: Add a function for reserving memory without kernel linear
mapping
video: meson: Use reserving memory function without kernel linear
mapping
common/fdt_support.c| 40 +
drivers/video/meson/meson_vpu.c | 6 ++---
include/fdt_support.h | 11 +
3 files changed, 54 insertions(+), 3 deletions(-)
--
2.17.1
Re: [PATCH v5 04/16] efi_loader: variable: support variable authentication
On Sun, Feb 23, 2020 at 12:20:16PM +0100, Heinrich Schuchardt wrote:
> On 1/28/20 9:25 AM, AKASHI Takahiro wrote:
> > With this commit, EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS
> > is supported for authenticated variables and the system secure state
> > will transfer between setup mode and user mode as UEFI specification
> > section 32.3 describes.
> >
> > Internally, authentication data is stored as part of authenticated
> > variable's value. It is nothing but a pkcs7 message (but we need some
> > wrapper, see efi_variable_parse_signature()) and will be validated by
> > efi_variable_authenticate(), hence efi_signature_verify_with_db().
> >
> > Associated time value will be encoded in "{...,time=...}" along with
> > other UEFI variable's attributes.
> >
> > Signed-off-by: AKASHI Takahiro
> > ---
> > include/efi_loader.h | 3 +
> > lib/efi_loader/efi_variable.c | 665 --
> > 2 files changed, 564 insertions(+), 104 deletions(-)
> >
> > diff --git a/include/efi_loader.h b/include/efi_loader.h
> > index 34f7b8eec8cd..f461c6195834 100644
> > --- a/include/efi_loader.h
> > +++ b/include/efi_loader.h
> > @@ -184,6 +184,7 @@ extern const efi_guid_t
> > efi_guid_image_security_database;
> > extern const efi_guid_t efi_guid_sha256;
> > extern const efi_guid_t efi_guid_cert_x509;
> > extern const efi_guid_t efi_guid_cert_x509_sha256;
> > +extern const efi_guid_t efi_guid_cert_type_pkcs7;
> >
> > /* GUID of RNG protocol */
> > extern const efi_guid_t efi_guid_rng_protocol;
> > @@ -738,6 +739,8 @@ efi_status_t efi_image_region_add(struct
> > efi_image_regions *regs,
> >
> > void efi_sigstore_free(struct efi_signature_store *sigstore);
> > struct efi_signature_store *efi_sigstore_parse_sigdb(u16 *name);
> > +
> > +bool efi_secure_boot_enabled(void);
> > #endif /* CONFIG_EFI_SECURE_BOOT */
> >
> > #else /* CONFIG_IS_ENABLED(EFI_LOADER) */
> > diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c
> > index c316bdfec0e4..2ae8222b1a94 100644
> > --- a/lib/efi_loader/efi_variable.c
> > +++ b/lib/efi_loader/efi_variable.c
> > @@ -10,8 +10,14 @@
> > #include
> > #include
> > #include
> > +#include
> > #include
> > +#include
> > #include
> > +#include "../lib/crypto/pkcs7_parser.h"
> > +
> > +const efi_guid_t efi_guid_cert_type_pkcs7 = EFI_CERT_TYPE_PKCS7_GUID;
> > +static bool efi_secure_boot;
> >
> > #define READ_ONLY BIT(31)
> >
> > @@ -108,7 +114,7 @@ static const char *prefix(const char *str, const char
> > *prefix)
> >* @attrp:pointer to UEFI attributes
> >* Return:pointer to remainder of U-Boot variable value
> >*/
> > -static const char *parse_attr(const char *str, u32 *attrp)
> > +static const char *parse_attr(const char *str, u32 *attrp, u64 *timep)
> > {
> > u32 attr = 0;
> > char sep = '{';
> > @@ -131,6 +137,12 @@ static const char *parse_attr(const char *str, u32
> > *attrp)
> > attr |= EFI_VARIABLE_BOOTSERVICE_ACCESS;
> > } else if ((s = prefix(str, "run"))) {
> > attr |= EFI_VARIABLE_RUNTIME_ACCESS;
> > + } else if ((s = prefix(str, "time="))) {
> > + attr |=
> > EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS;
> > + hex2bin((u8 *)timep, s, sizeof(*timep));
> > + s += sizeof(*timep) * 2;
> > + } else if (*str == '}') {
> > + break;
> > } else {
> > printf("invalid attribute: %s\n", str);
> > break;
> > @@ -148,48 +160,291 @@ static const char *parse_attr(const char *str, u32
> > *attrp)
> > }
> >
> > /**
> > - * efi_get_variable() - retrieve value of a UEFI variable
> > + * efi_secure_boot_enabled - return if secure boot is enabled or not
> >*
> > - * This function implements the GetVariable runtime service.
> > + * Return: true if enabled, false if disabled
> > + */
> > +bool efi_secure_boot_enabled(void)
> > +{
> > + return efi_secure_boot;
> > +}
> > +
> > +#ifdef CONFIG_EFI_SECURE_BOOT
> > +static u8 pkcs7_hdr[] = {
> > + /* SEQUENCE */
> > + 0x30, 0x82, 0x05, 0xc7,
> > + /* OID: pkcs7-signedData */
> > + 0x06, 0x09, 0x2a, 0x86, 0x48, 0x86, 0xf7, 0x0d, 0x01, 0x07, 0x02,
> > + /* Context Structured? */
> > + 0xa0, 0x82, 0x05, 0xb8,
> > +};
> > +
> > +/**
> > + * efi_variable_parse_signature - parse a signature in variable
> > + * @buf: Pointer to variable's value
> > + * @buflen:Length of @buf
> >*
> > - * See the Unified Extensible Firmware Interface (UEFI) specification for
> > - * details.
> > + * Parse a signature embedded in variable's value and instantiate
> > + * a pkcs7_message structure. Since pkcs7_parse_message() accepts only
> > + * pkcs7's signedData, some header needed be prepended for correctly
> > + * parsing authentication data, particularly for variable's.
> >*
> > - * @variable_name: name
Re: [PATCH v5 01/16] efi_loader: add CONFIG_EFI_SECURE_BOOT config option
On Sun, Feb 23, 2020 at 11:56:09AM +0100, Heinrich Schuchardt wrote: > On 1/28/20 9:25 AM, AKASHI Takahiro wrote: > > Under this configuration, UEFI secure boot support will be added > > in later patches. > > > > Signed-off-by: AKASHI Takahiro > > This patch should be after all the patches that are necessary for secure > boot, i.e. after patch 09/16. I can take care of that. I disagree. Doing so will constrain bisect ability to some extent because any code under EFI_SECURE_BOOT will never have a chance to be compiled until this patch is applied. Then bisect result could be inaccurate. Thanks, -Takahiro Akashi > Best regards > > Heinrich > > > --- > > lib/efi_loader/Kconfig | 18 ++ > > 1 file changed, 18 insertions(+) > > > > diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig > > index a7afa3f29e88..4b09a07f1b0a 100644 > > --- a/lib/efi_loader/Kconfig > > +++ b/lib/efi_loader/Kconfig > > @@ -130,4 +130,22 @@ config EFI_RNG_PROTOCOL > > "Support for EFI_RNG_PROTOCOL implementation. Uses the rng > >device on the platform" > > > > +config EFI_SECURE_BOOT > > + bool "Enable EFI secure boot support" > > + depends on EFI_LOADER > > + select SHA256 > > + select RSA > > + select RSA_VERIFY_WITH_PKEY > > + select IMAGE_SIGN_INFO > > + select ASYMMETRIC_KEY_TYPE > > + select ASYMMETRIC_PUBLIC_KEY_SUBTYPE > > + select X509_CERTIFICATE_PARSER > > + select PKCS7_MESSAGE_PARSER > > + default n > > + help > > + Select this option to enable EFI secure boot support. > > + Once SecureBoot mode is enforced, any EFI binary can run only if > > + it is signed with a trusted key. To do that, you need to install, > > + at least, PK, KEK and db. > > + > > endif > > >
Re: [PATCH v7 0/7] rsa: extend rsa_verify() for UEFI secure boot
On Fri, Feb 21, 2020 at 12:18:41PM -0500, Tom Rini wrote: > On Fri, Feb 21, 2020 at 03:12:54PM +0900, AKASHI Takahiro wrote: > > > # This patch set is a prerequisite for UEFI secure boot. > > > > The current rsa_verify() requires five parameters for a RSA public key > > for efficiency while RSA, in theory, requires only two. In addition, > > those parameters are expected to come from FIT image. > > > > So this function won't fit very well when we want to use it for the purpose > > of implementing UEFI secure boot, in particular, image authentication > > as well as variable authentication, where the essential two parameters > > are set to be retrieved from one of X509 certificates in signature > > database. > > > > So, in this patch, additional three parameters will be calculated > > on the fly when rsa_verify() is called without fdt which should contain > > parameters above. > > > > This calculation heavily relies on "big-number (or multi-precision) > > library." Therefore some routines from BearSSL[1] under MIT license are > > imported in this implementation. See Patch#4. > > # Please let me know if this is not appropriate. > > > > Prerequisite: > > * public key parser in my "import x509/pkcs7 parser" patch[2] > > This has been applied a long while back. Yes, I forgot to remove this line. > And for the record, without http://patchwork.ozlabs.org/patch/1239098/ > applied sandbox fails to build. I had said I would take care of that > specific issue, so I'm just noting it here. I'm kicking off a larger > test now. Thank you! -Takahiro Akashi > -- > Tom
Re: [PATCH v2] env: ti: boot: Fix Android boot on AM57x EVM
On 21/02/20 8:05 PM, Sam Protsenko wrote: > When applying DTBO on top of DTB (with "fdt apply" command) on AM57x EVM > board, there is not enough memory reserved in RAM for DTB blob. Hence, > DTBO can't be merged in DTB. It leads to inability to boot Android with > next error message: > > failed on fdt_overlay_apply(): FDT_ERR_NOSPACE > > To overcome that issue let's provide 512 KiB of space to keep DTB and > all merged DTBO blobs. To do so, "length" parameter should be specified > for "fdt addr" command: > > => fdt addr $fdtaddr 0x8 > > 512 KiB is the maximum size we can use for this, because next address > after $fdtaddr is 512 KiB ahead of it: > > fdtaddr=0x8800 > rdaddr=0x8808 > > Also add size variables to 'adtimg' command invocations, to avoid > cluttering the console with DTBO blob sizes. > > Signed-off-by: Sam Protsenko Applied to u-boot-ti next. Thanks and regards, Lokesh
Re: [RFC PATCH 0/1] Add boot hartid to a Device tree
On Mon, Feb 24, 2020 at 3:35 PM Ard Biesheuvel wrote: > > On Tue, 25 Feb 2020 at 00:22, Heinrich Schuchardt wrote: > > > > On 2/24/20 11:19 PM, Atish Patra wrote: > > > The RISC-V booting protocol requires the hart id to be present in "a0" > > > register. This is not a problem for bootm/booti commands as they directly > > > jump to Linux kernel. However, bootefi jumps to a EFI boot stub code in > > > Linux kernel which acts a loader and jumps to real Linux after terminating > > > the boot services. This boot stub code has to be aware of the boot hart id > > > so that it can set it in "a0" before jumping to Linux kernel. Currently, > > > UEFI protocol doesn't have any mechanism to pass the boot hart id to an > > > EFI executable. We should keep it this way as this is a RISC-V specific > > > requirement rather than a UEFI requirement. Out of the all possible > > > options, > > > device tree seemed to be the best choice to do this job. > > > The detailed discussion can be found in the following thread. > > > > > > https://patchwork.ozlabs.org/patch/1233664/ > > > > The above mentioned patch is obsoleted by the new suggestion. > > Thanks for pointing that out to avoid confusion. > > > > > > This patch updates the device tree in arch_fixup_fdt() which is common for > > > all booting commands. As a result, the DT modification doesn't require any > > > efi related arch specific functions and all DT related modifications are > > > contained at one place. However, the hart id node will be available for > > > Linux even if the kernel is booted using bootm command. > > > > > > If that is not acceptable, we can always move the code to an efi specific > > > function. > > > > Does a related Linux patch already exist? Yes. But in my local tree ;). It will be included in RISC-V EFI stub support series which I am planning to post in a couple of days. > > How about EDK2? > > > > RISC-V is not supported at all yet in EDK2. > The EDK2 patches are out there and reviewed. I guess it will be available in mainline EDK2 pretty soon. Abner agreed that similar patch can be added to EDK2 as well in the previous thread. > > I guess boot loaders like GRUB would not have to care about the extra > > property? > > > > Yes, that is basically the point. -- Regards, Atish
Re: [RFC PATCH 1/1] riscv: Add boot hartid to Device tree
On Mon, 24 Feb 2020 at 23:20, Atish Patra wrote:
>
> Linux booting protocol mandates that register "a0" contains the hartid.
> However, U-boot can not pass the hartid via a0 during EFI boot without
> breaking the UEFI specification.
>
It is not about breaking or violating the UEFI specification. It is
about the firmware using a conduit that is already being used to
describe the hardware to the OS to pass an extra piece of information
that the OS needs.
> Add a DT node under chosen node to indicate the boot hartid. EFI stub
> in Linux kernel will parse this node and pass it to the real kernel
> in "a0" before jumping to it.
>
> Signed-off-by: Atish Patra
> ---
> arch/riscv/lib/bootm.c | 13 +
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c
> index fad16901c5f2..b84cc2db2016 100644
> --- a/arch/riscv/lib/bootm.c
> +++ b/arch/riscv/lib/bootm.c
> @@ -28,6 +28,19 @@ __weak void board_quiesce_devices(void)
>
> int arch_fixup_fdt(void *blob)
> {
> + u32 size;
> + int chosen_offset, err;
> +
> + size = fdt_totalsize(blob);
> + err = fdt_open_into(blob, blob, size + 32);
> + if (err < 0) {
> + printf("Device Tree can't be expanded to accmodate new node");
'accommodate'
> + return -1;
> + }
> + chosen_offset = fdt_path_offset(blob, "/chosen");
> + fdt_setprop_u64(blob, chosen_offset, "efi-boot-hartid",
I assume that boot hartid does not change value when you boot via
UEFI, so this should simply be /chosen/boot-hartid
> + gd->arch.boot_hart);
> +
> return 0;
> }
>
> --
> 2.24.0
>
Re: [RFC PATCH 0/1] Add boot hartid to a Device tree
On Tue, 25 Feb 2020 at 00:22, Heinrich Schuchardt wrote: > > On 2/24/20 11:19 PM, Atish Patra wrote: > > The RISC-V booting protocol requires the hart id to be present in "a0" > > register. This is not a problem for bootm/booti commands as they directly > > jump to Linux kernel. However, bootefi jumps to a EFI boot stub code in > > Linux kernel which acts a loader and jumps to real Linux after terminating > > the boot services. This boot stub code has to be aware of the boot hart id > > so that it can set it in "a0" before jumping to Linux kernel. Currently, > > UEFI protocol doesn't have any mechanism to pass the boot hart id to an > > EFI executable. We should keep it this way as this is a RISC-V specific > > requirement rather than a UEFI requirement. Out of the all possible options, > > device tree seemed to be the best choice to do this job. > > The detailed discussion can be found in the following thread. > > > > https://patchwork.ozlabs.org/patch/1233664/ > > The above mentioned patch is obsoleted by the new suggestion. > > > > > This patch updates the device tree in arch_fixup_fdt() which is common for > > all booting commands. As a result, the DT modification doesn't require any > > efi related arch specific functions and all DT related modifications are > > contained at one place. However, the hart id node will be available for > > Linux even if the kernel is booted using bootm command. > > > > If that is not acceptable, we can always move the code to an efi specific > > function. > > Does a related Linux patch already exist? > How about EDK2? > RISC-V is not supported at all yet in EDK2. > I guess boot loaders like GRUB would not have to care about the extra > property? > Yes, that is basically the point.
Re: [RFC PATCH 0/1] Add boot hartid to a Device tree
On 2/24/20 11:19 PM, Atish Patra wrote: The RISC-V booting protocol requires the hart id to be present in "a0" register. This is not a problem for bootm/booti commands as they directly jump to Linux kernel. However, bootefi jumps to a EFI boot stub code in Linux kernel which acts a loader and jumps to real Linux after terminating the boot services. This boot stub code has to be aware of the boot hart id so that it can set it in "a0" before jumping to Linux kernel. Currently, UEFI protocol doesn't have any mechanism to pass the boot hart id to an EFI executable. We should keep it this way as this is a RISC-V specific requirement rather than a UEFI requirement. Out of the all possible options, device tree seemed to be the best choice to do this job. The detailed discussion can be found in the following thread. https://patchwork.ozlabs.org/patch/1233664/ The above mentioned patch is obsoleted by the new suggestion. This patch updates the device tree in arch_fixup_fdt() which is common for all booting commands. As a result, the DT modification doesn't require any efi related arch specific functions and all DT related modifications are contained at one place. However, the hart id node will be available for Linux even if the kernel is booted using bootm command. If that is not acceptable, we can always move the code to an efi specific function. Does a related Linux patch already exist? How about EDK2? I guess boot loaders like GRUB would not have to care about the extra property? Best regards Heinrich Atish Patra (1): riscv: Add boot hartid to Device tree arch/riscv/lib/bootm.c | 13 + 1 file changed, 13 insertions(+) -- 2.24.0
[PATCH 1/1] drivers/rng: add Amlogic hardware RNG driver
Add support for the hardware random number generator of Amlogic SOCs.
Signed-off-by: Heinrich Schuchardt
---
drivers/rng/Kconfig | 8 +++
drivers/rng/Makefile| 1 +
drivers/rng/meson-rng.c | 120
3 files changed, 129 insertions(+)
create mode 100644 drivers/rng/meson-rng.c
diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
index c1aa43b823..edb6152bb9 100644
--- a/drivers/rng/Kconfig
+++ b/drivers/rng/Kconfig
@@ -8,6 +8,14 @@ config DM_RNG
if DM_RNG
+config RNG_MESON
+ bool "Amlogic Meson Random Number Generator support"
+ depends on ARCH_MESON
+ default y
+ help
+ Enable support for hardware random number generator
+ of Amlogic Meson SoCs.
+
config RNG_SANDBOX
bool "Sandbox random number generator"
depends on SANDBOX
diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile
index 3517005541..6a8a66779b 100644
--- a/drivers/rng/Makefile
+++ b/drivers/rng/Makefile
@@ -4,5 +4,6 @@
#
obj-$(CONFIG_DM_RNG) += rng-uclass.o
+obj-$(CONFIG_RNG_MESON) += meson-rng.o
obj-$(CONFIG_RNG_SANDBOX) += sandbox_rng.o
obj-$(CONFIG_RNG_STM32MP1) += stm32mp1_rng.o
diff --git a/drivers/rng/meson-rng.c b/drivers/rng/meson-rng.c
new file mode 100644
index 00..4b81a62353
--- /dev/null
+++ b/drivers/rng/meson-rng.c
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2020, Heinrich Schuchardt
+ *
+ * Driver for Amlogic hardware random number generator
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+struct meson_rng_platdata {
+ fdt_addr_t base;
+ struct clk clk;
+};
+
+/**
+ * meson_rng_read() - fill buffer with random bytes
+ *
+ * @buffer:buffer to receive data
+ * @size: size of buffer
+ *
+ * Return: 0
+ */
+static int meson_rng_read(struct udevice *dev, void *data, size_t len)
+{
+ struct meson_rng_platdata *pdata = dev_get_platdata(dev);
+ char *buffer = (char *)data;
+
+ while (len) {
+ u32 rand = readl(pdata->base);
+ size_t step;
+
+ if (len >= 4)
+ step = 4;
+ else
+ step = len;
+ memcpy(buffer, , step);
+ buffer += step;
+ len -= step;
+ }
+ return 0;
+}
+
+/**
+ * meson_rng_probe() - probe rng device
+ *
+ * @dev: device
+ * Return: 0 if ok
+ */
+static int meson_rng_probe(struct udevice *dev)
+{
+ struct meson_rng_platdata *pdata = dev_get_platdata(dev);
+ int err;
+
+ err = clk_enable(>clk);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+/**
+ * meson_rng_remove() - deinitialize rng device
+ *
+ * @dev: device
+ * Return: 0 if ok
+ */
+static int meson_rng_remove(struct udevice *dev)
+{
+ struct meson_rng_platdata *pdata = dev_get_platdata(dev);
+
+ return clk_disable(>clk);
+}
+
+/**
+ * meson_rng_ofdata_to_platdata() - transfer device tree data to plaform data
+ *
+ * @dev: device
+ * Return: 0 if ok
+ */
+static int meson_rng_ofdata_to_platdata(struct udevice *dev)
+{
+ struct meson_rng_platdata *pdata = dev_get_platdata(dev);
+ int err;
+
+ pdata->base = dev_read_addr(dev);
+ if (!pdata->base)
+ return -ENODEV;
+
+ err = clk_get_by_name(dev, "core", >clk);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+static const struct dm_rng_ops meson_rng_ops = {
+ .read = meson_rng_read,
+};
+
+static const struct udevice_id meson_rng_match[] = {
+ {
+ .compatible = "amlogic,meson-rng",
+ },
+ {},
+};
+
+U_BOOT_DRIVER(meson_rng) = {
+ .name = "meson-rng",
+ .id = UCLASS_RNG,
+ .of_match = meson_rng_match,
+ .ops = _rng_ops,
+ .probe = meson_rng_probe,
+ .remove = meson_rng_remove,
+ .platdata_auto_alloc_size = sizeof(struct meson_rng_platdata),
+ .ofdata_to_platdata = meson_rng_ofdata_to_platdata,
+};
--
2.20.1
[RFC PATCH 1/1] riscv: Add boot hartid to Device tree
Linux booting protocol mandates that register "a0" contains the hartid.
However, U-boot can not pass the hartid via a0 during EFI boot without
breaking the UEFI specification.
Add a DT node under chosen node to indicate the boot hartid. EFI stub
in Linux kernel will parse this node and pass it to the real kernel
in "a0" before jumping to it.
Signed-off-by: Atish Patra
---
arch/riscv/lib/bootm.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c
index fad16901c5f2..b84cc2db2016 100644
--- a/arch/riscv/lib/bootm.c
+++ b/arch/riscv/lib/bootm.c
@@ -28,6 +28,19 @@ __weak void board_quiesce_devices(void)
int arch_fixup_fdt(void *blob)
{
+ u32 size;
+ int chosen_offset, err;
+
+ size = fdt_totalsize(blob);
+ err = fdt_open_into(blob, blob, size + 32);
+ if (err < 0) {
+ printf("Device Tree can't be expanded to accmodate new node");
+ return -1;
+ }
+ chosen_offset = fdt_path_offset(blob, "/chosen");
+ fdt_setprop_u64(blob, chosen_offset, "efi-boot-hartid",
+ gd->arch.boot_hart);
+
return 0;
}
--
2.24.0
[RFC PATCH 0/1] Add boot hartid to a Device tree
The RISC-V booting protocol requires the hart id to be present in "a0" register. This is not a problem for bootm/booti commands as they directly jump to Linux kernel. However, bootefi jumps to a EFI boot stub code in Linux kernel which acts a loader and jumps to real Linux after terminating the boot services. This boot stub code has to be aware of the boot hart id so that it can set it in "a0" before jumping to Linux kernel. Currently, UEFI protocol doesn't have any mechanism to pass the boot hart id to an EFI executable. We should keep it this way as this is a RISC-V specific requirement rather than a UEFI requirement. Out of the all possible options, device tree seemed to be the best choice to do this job. The detailed discussion can be found in the following thread. https://patchwork.ozlabs.org/patch/1233664/ This patch updates the device tree in arch_fixup_fdt() which is common for all booting commands. As a result, the DT modification doesn't require any efi related arch specific functions and all DT related modifications are contained at one place. However, the hart id node will be available for Linux even if the kernel is booted using bootm command. If that is not acceptable, we can always move the code to an efi specific function. Atish Patra (1): riscv: Add boot hartid to Device tree arch/riscv/lib/bootm.c | 13 + 1 file changed, 13 insertions(+) -- 2.24.0
Re: [PATCH v2] env: ti: boot: Fix Android boot on AM57x EVM
On Fri, Feb 21, 2020 at 04:35:21PM +0200, Sam Protsenko wrote: > When applying DTBO on top of DTB (with "fdt apply" command) on AM57x EVM > board, there is not enough memory reserved in RAM for DTB blob. Hence, > DTBO can't be merged in DTB. It leads to inability to boot Android with > next error message: > > failed on fdt_overlay_apply(): FDT_ERR_NOSPACE > > To overcome that issue let's provide 512 KiB of space to keep DTB and > all merged DTBO blobs. To do so, "length" parameter should be specified > for "fdt addr" command: > > => fdt addr $fdtaddr 0x8 > > 512 KiB is the maximum size we can use for this, because next address > after $fdtaddr is 512 KiB ahead of it: > > fdtaddr=0x8800 > rdaddr=0x8808 > > Also add size variables to 'adtimg' command invocations, to avoid > cluttering the console with DTBO blob sizes. > > Signed-off-by: Sam Protsenko > --- > Changes in v2: > - Reserve 512 KiB for DTB area, not 1 MiB Reviewed-by: Eugeniu Rosca -- Best Regards Eugeniu Rosca
[PATCH] net: phy: marvell: Unify 88E151x series phy_driver
The PHY models of the Marvell 88E151x series are not reliably
distinguishable by their uid / PHY identifiers.
The 88E1510, 88E1512, 88E1514 and 88E1518 all have the same OUI and
model number and bits 3:0 in the PHY Identifier 2 (Page 0, Reg 3) are
described as HW revision number, but both 88E1510 and 88E1518 PHYs were
observed with the same HW rev number (1).
Before commit 83cfbeb0df9f ("net: phy: Fix mask so that we can identify
Marvell 88E1518"), the 88E151x were detected because the HW revision
bits were masked from the uid. After that change, 88E1510/12/18 were all
detected as 88E1518 and the 88E1510 specific code was no longer run.
I modified the mask to again ignore all four HW revision bits, removed
the 88E1510 specific code (board-specific LED/INTn setup), which was not
called since late 2016 anyway and renamed the config function and
phy_driver struct to the better fitting 88e151x.
The uid and mask bits 3:0 are now again the same as in the Linux kernel.
Signed-off-by: Clemens Gruber
---
drivers/net/phy/marvell.c | 65 ++-
1 file changed, 10 insertions(+), 55 deletions(-)
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index efbbd31ff7..93cf44ad4c 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -303,9 +303,9 @@ static int m88es_config(struct phy_device *phydev)
}
/**
- * m88e1518_phy_writebits - write bits to a register
+ * m88e151x_phy_writebits - write bits to a register
*/
-void m88e1518_phy_writebits(struct phy_device *phydev,
+void m88e151x_phy_writebits(struct phy_device *phydev,
u8 reg_num, u16 offset, u16 len, u16 data)
{
u16 reg, mask;
@@ -323,7 +323,7 @@ void m88e1518_phy_writebits(struct phy_device *phydev,
phy_write(phydev, MDIO_DEVAD_NONE, reg_num, reg);
}
-static int m88e1518_config(struct phy_device *phydev)
+static int m88e151x_config(struct phy_device *phydev)
{
u16 reg;
@@ -350,11 +350,11 @@ static int m88e1518_config(struct phy_device *phydev)
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 18);
/* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
- m88e1518_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL,
+ m88e151x_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL,
0, 3, MIIM_88E151x_MODE_SGMII);
/* PHY reset is necessary after changing MODE[2:0] */
- m88e1518_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL,
+ m88e151x_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL,
MIIM_88E151x_RESET_OFFS, 1, 1);
/* Reset page selection */
@@ -401,33 +401,6 @@ static int m88e1518_config(struct phy_device *phydev)
return 0;
}
-/* Marvell 88E1510 */
-static int m88e1510_config(struct phy_device *phydev)
-{
- /* Select page 3 */
- phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE,
- MIIM_88E1118_PHY_LED_PAGE);
-
- /* Enable INTn output on LED[2] */
- m88e1518_phy_writebits(phydev, MIIM_88E151x_LED_TIMER_CTRL,
- MIIM_88E151x_INT_EN_OFFS, 1, 1);
-
- /* Configure LEDs */
- /* LED[0]:0011 (ACT) */
- m88e1518_phy_writebits(phydev, MIIM_88E151x_LED_FUNC_CTRL,
- MIIM_88E151x_LED0_OFFS, MIIM_88E151x_LED_FLD_SZ,
- MIIM_88E151x_LED0_ACT);
- /* LED[1]:0110 (LINK 100/1000 Mbps) */
- m88e1518_phy_writebits(phydev, MIIM_88E151x_LED_FUNC_CTRL,
- MIIM_88E151x_LED1_OFFS, MIIM_88E151x_LED_FLD_SZ,
- MIIM_88E151x_LED1_100_1000_LINK);
-
- /* Reset page selection */
- phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0);
-
- return m88e1518_config(phydev);
-}
-
/* Marvell 88E1118 */
static int m88e1118_config(struct phy_device *phydev)
{
@@ -685,29 +658,12 @@ static struct phy_driver M88E1149S_driver = {
.shutdown = _shutdown,
};
-static struct phy_driver M88E1510_driver = {
- .name = "Marvell 88E1510",
- .uid = 0x1410dd0,
- .mask = 0xfff,
- .features = PHY_GBIT_FEATURES,
- .config = _config,
- .startup = _startup,
- .shutdown = _shutdown,
- .readext = _phy_extread,
- .writeext = _phy_extwrite,
-};
-
-/*
- * This supports:
- * 88E1518, uid 0x1410dd1
- * 88E1512, uid 0x1410dd4
- */
-static struct phy_driver M88E1518_driver = {
- .name = "Marvell 88E1518",
+static struct phy_driver M88E151x_driver = {
+ .name = "Marvell 88E151x",
.uid = 0x1410dd0,
- .mask = 0xffa,
+ .mask = 0xff0,
.features = PHY_GBIT_FEATURES,
- .config = _config,
+ .config = _config,
.startup = _startup,
.shutdown = _shutdown,
.readext = _phy_extread,
@@ -744,8 +700,7 @@ int
Re: [PATCH 2/7] mx31pdk: Move CONFIG_SPL_LDSCRIPT to defconfig
On Mon, 24 Feb 2020 at 19:05, Tom Rini wrote: > As there is only one mx31pdk config file and with upcoming updates to > the Kconfig parsing logic, rather than have an entry in > board/freescale/mx31pdk/Kconfig, move this single setting to the > defconfig file. > > Cc: Magnus Lilja > Signed-off-by: Tom Rini > --- > Reviewed-by: Magnus Lilja /Magnus > board/freescale/mx31pdk/Kconfig | 3 --- > configs/mx31pdk_defconfig | 1 + > 2 files changed, 1 insertion(+), 3 deletions(-) > > diff --git a/board/freescale/mx31pdk/Kconfig > b/board/freescale/mx31pdk/Kconfig > index b9fc2d517786..055545c93063 100644 > --- a/board/freescale/mx31pdk/Kconfig > +++ b/board/freescale/mx31pdk/Kconfig > @@ -1,8 +1,5 @@ > if TARGET_MX31PDK > > -config SPL_LDSCRIPT > - default "arch/$(ARCH)/cpu/u-boot-spl.lds" > - > config SYS_BOARD > default "mx31pdk" > > diff --git a/configs/mx31pdk_defconfig b/configs/mx31pdk_defconfig > index 9ab4a09ea9cb..163f756b4afc 100644 > --- a/configs/mx31pdk_defconfig > +++ b/configs/mx31pdk_defconfig > @@ -2,6 +2,7 @@ CONFIG_ARM=y > # CONFIG_SPL_USE_ARCH_MEMCPY is not set > # CONFIG_SPL_USE_ARCH_MEMSET is not set > CONFIG_ARCH_MX31=y > +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/u-boot-spl.lds" > CONFIG_SYS_TEXT_BASE=0x87e0 > CONFIG_SPL_LIBGENERIC_SUPPORT=y > CONFIG_TARGET_MX31PDK=y > -- > 2.17.1 > >
Re: [PATCH 0/3] mediatek: pwm: add pwm driver for MediaTek SoCs
tested pwm on bananapi r64 (with LED on gpio pins 9 as GND + 11 as pwm) with commands BPI-R64> pwm 0 config 10 5 BPI-R64> pwm 0 enable also no boot-problem after last Patch (removed my temporary workaround) Tested-by: Frank Wunderlich only a small typo in last patches subject (missing d in unused): arm: mediatek: remove unuse binman config regards Frank
Re: [PATCH v5 07/16] efi_loader: image_loader: support image authentication
On 1/28/20 9:25 AM, AKASHI Takahiro wrote: With this commit, image validation can be enforced, as UEFI specification section 32.5 describes, if CONFIG_EFI_SECURE_BOOT is enabled. Currently we support * authentication based on db and dbx, so dbx-validated image will always be rejected. * following signature types: EFI_CERT_SHA256_GUID (SHA256 digest for unsigned images) EFI_CERT_X509_GUID (x509 certificate for signed images) Timestamp-based certificate revocation is not supported here. Internally, authentication data is stored in one of certificates tables of PE image (See efi_image_parse()) and will be verified by efi_image_authenticate() before loading a given image. It seems that UEFI specification defines the verification process in a bit ambiguous way. I tried to implement it as closely to as EDK2 does. Signed-off-by: AKASHI Takahiro According to git bisect this patch breaks the test test/py/tests/test_efi_fit.py. Best regards Heinrich
[PATCH 7/7] kconfig / kbuild: re-sync with Linux 4.18
Align Kconfig and Kbuild logic to Linux 4.18 release with minimal impact
on files outside of this scope.
Our previous Kconfig sync was done by commit e91610da7c8a ("kconfig:
re-sync with Linux 4.17-rc4").
A very small number of changes upstream since our sync with v4.17-rc4
that exist in the v4.18 release have already been applied here and have
been omitted from the list in this commit (and are readily available in
our own git history).
The imported Linux commits are:
b3aa58d2e85d fixdep: suppress consecutive / from file paths in dependency list
files
74656b682902 kbuild: disable new dtc graph and unit-address warnings
74d931716151 genksyms: remove symbol prefix support
e6ecfb45072c kbuild: do not display CHK for filechk
0b669a5076fd kconfig: refactor Qt package checks for building qconf
b464ef583dc7 kconfig: refactor GTK+ package checks for building gconf
1c5af5cf9308 kconfig: refactor ncurses package checks for building mconf and
nconf
694c49a7c01c kconfig: drop localization support
96f60dfa5819 trace: Use -mcount-record for dynamic ftrace
bb222ceeb327 kconfig: remove string expansion in file_lookup()
96d8e48da55a kconfig: remove string expansion for mainmenu after yyparse()
5b31a9746756 kconfig: remove sym_expand_string_value()
137c0118a900 kconfig: make default prompt of mainmenu less specific
e298f3b49def kconfig: add built-in function support
2fd5b09c201e kconfig: add 'shell' built-in function
9de071536c87 kconfig: begin PARAM state only when seeing a command keyword
9ced3bddec08 kconfig: support user-defined function and recursively expanded
variable
1175c02506ff kconfig: support simply expanded variable
ed2a22f277c6 kconfig: support append assignment operator
82bc8bd82e5c kconfig: expand lefthand side of assignment statement
1d6272e6fe43 kconfig: add 'info', 'warning-if', and 'error-if' built-in
functions
a702a6176e2f kconfig: add 'filename' and 'lineno' built-in variables
915f64901eb3 kconfig: error out if a recursive variable references itself
2bece88f89fa kconfig: test: add Kconfig macro language tests
21c54b774744 kconfig: show compiler version text in the top comment
59f7b5847b0c kbuild: $(CHECK) doesnt need NOSTDINC_FLAGS twice
145167650b96 kbuild: add endianness flag to CHEKCFLAGS
1f2f01b122d7 kbuild: add machine size to CHECKFLAGS
d6a0c8a1326b kconfig: Add testconfig into make help output
bb6d83dde191 kbuild: Move last word of nconfig help to the previous line
8593080c0fcf kconfig: fix localmodconfig
ed7d40bc67b8 tracing: Fix SKIP_STACK_VALIDATION=1 build due to bad merge with
-mrecord-mcount
b2d00d7c61c8 kconfig: fix line numbers for if-entries in menu tree
ecd53ac2f2c6 kconfig: handle P_SYMBOL in print_symbol()
73d1c580f92b kconfig: loop boundary condition fix
48f6e3cf5bc6 kbuild: do not drop -I without parameter
bd412d81b7ea kbuild: .PHONY is not a variable, but PHONY is
6916162c7308 kbuild: remove duplicated comments about PHONY
Cc: Masahiro Yamada
Signed-off-by: Tom Rini
---
Kconfig | 6 +-
Makefile | 11 +-
scripts/Kbuild.include| 3 +-
scripts/Makefile.build| 10 +-
scripts/Makefile.clean| 3 -
scripts/Makefile.lib | 3 +
scripts/basic/fixdep.c| 6 +-
scripts/kconfig/.gitignore| 4 -
scripts/kconfig/Makefile | 194 ++
scripts/kconfig/POTFILES.in | 12 -
scripts/kconfig/check.sh | 14 -
scripts/kconfig/conf.c| 51 +-
scripts/kconfig/confdata.c| 37 +-
scripts/kconfig/expr.h| 3 +
scripts/kconfig/gconf-cfg.sh | 23 +
scripts/kconfig/gconf.c | 46 +-
scripts/kconfig/kconf_id.c| 1 -
scripts/kconfig/kxgettext.c | 235 ---
scripts/kconfig/lkc.h | 19 +-
scripts/kconfig/lkc_proto.h | 15 +-
scripts/kconfig/lxdialog/check-lxdialog.sh| 93 ---
scripts/kconfig/lxdialog/checklist.c | 4 +-
scripts/kconfig/lxdialog/dialog.h | 8 +-
scripts/kconfig/lxdialog/inputbox.c | 4 +-
scripts/kconfig/lxdialog/menubox.c| 10 +-
scripts/kconfig/lxdialog/textbox.c| 2 +-
scripts/kconfig/lxdialog/yesno.c | 4 +-
scripts/kconfig/mconf-cfg.sh | 44 ++
scripts/kconfig/mconf.c | 141 +++--
scripts/kconfig/menu.c| 23 +-
scripts/kconfig/nconf-cfg.sh | 44 ++
scripts/kconfig/nconf.c | 148 +++--
scripts/kconfig/nconf.h | 1 -
scripts/kconfig/preprocess.c | 572 ++
scripts/kconfig/qconf-cfg.sh | 25 +
scripts/kconfig/qconf.cc | 104
[PATCH 6/7] scripts/dtc: Update to upstream version v1.4.6-21-g84e414b0b5bc
From: Rob Herring
This adds the following commits from upstream:
84e414b0b5bc tests: Add a test case for the omit-if-no-ref keyword
4038fd90056e dtc: add ability to make nodes conditional on them being referenced
e1f139ea4900 checks: drop warning for missing PCI bridge bus-range
f4eba68d89ee checks: Print duplicate node name instead of parent name
46df1fb1b211 .travis.yml: Run valgrind checks via Travis
14a3002a1aee tests: Update valgrind suppressions for sw_tree1
02c5fe9debc0 tests: Remove valgrind error from tests/get_path
df536831d02c checks: add graph binding checks
2347c96edcbe checks: add a check for duplicate unit-addresses of child nodes
8f1b35f88395 Correct overlay syntactic sugar for generating target-path
fragments
afbddcd418fb Suppress warnings on overlay fragments
119e27300359 Improve tests for dtc overlay generation
[From Linux Kernel commit 50aafd60898a8b3edf2f60e014a8288da3b2e5e3]
Signed-off-by: Rob Herring
[For applying to U-Boot]
Signed-off-by: Tom Rini
---
scripts/dtc/checks.c | 186 +-
scripts/dtc/dtc-parser.y | 22 ++---
scripts/dtc/livetree.c| 12 ++-
scripts/dtc/version_gen.h | 2 +-
4 files changed, 206 insertions(+), 16 deletions(-)
diff --git a/scripts/dtc/checks.c b/scripts/dtc/checks.c
index 40879677c8c3..c35aa6f88639 100644
--- a/scripts/dtc/checks.c
+++ b/scripts/dtc/checks.c
@@ -255,7 +255,7 @@ static void check_duplicate_node_names(struct check *c,
struct dt_info *dti,
child2;
child2 = child2->next_sibling)
if (streq(child->name, child2->name))
- FAIL(c, dti, node, "Duplicate node name");
+ FAIL(c, dti, child2, "Duplicate node name");
}
ERROR(duplicate_node_names, check_duplicate_node_names, NULL);
@@ -317,6 +317,11 @@ static void check_unit_address_vs_reg(struct check *c,
struct dt_info *dti,
const char *unitname = get_unitname(node);
struct property *prop = get_property(node, "reg");
+ if (get_subnode(node, "__overlay__")) {
+ /* HACK: Overlay fragments are a special case */
+ return;
+ }
+
if (!prop) {
prop = get_property(node, "ranges");
if (prop && !prop->val.len)
@@ -1030,6 +1035,36 @@ static void check_avoid_unnecessary_addr_size(struct
check *c, struct dt_info *d
}
WARNING(avoid_unnecessary_addr_size, check_avoid_unnecessary_addr_size, NULL,
_default_addr_size);
+static void check_unique_unit_address(struct check *c, struct dt_info *dti,
+ struct node *node)
+{
+ struct node *childa;
+
+ if (node->addr_cells < 0 || node->size_cells < 0)
+ return;
+
+ if (!node->children)
+ return;
+
+ for_each_child(node, childa) {
+ struct node *childb;
+ const char *addr_a = get_unitname(childa);
+
+ if (!strlen(addr_a))
+ continue;
+
+ for_each_child(node, childb) {
+ const char *addr_b = get_unitname(childb);
+ if (childa == childb)
+ break;
+
+ if (streq(addr_a, addr_b))
+ FAIL(c, dti, childb, "duplicate unit-address
(also used in node %s)", childa->fullpath);
+ }
+ }
+}
+WARNING(unique_unit_address, check_unique_unit_address, NULL,
_default_addr_size);
+
static void check_obsolete_chosen_interrupt_controller(struct check *c,
struct dt_info *dti,
struct node *node)
@@ -1370,6 +1405,152 @@ static void check_interrupts_property(struct check *c,
}
WARNING(interrupts_property, check_interrupts_property, _references);
+static const struct bus_type graph_port_bus = {
+ .name = "graph-port",
+};
+
+static const struct bus_type graph_ports_bus = {
+ .name = "graph-ports",
+};
+
+static void check_graph_nodes(struct check *c, struct dt_info *dti,
+ struct node *node)
+{
+ struct node *child;
+
+ for_each_child(node, child) {
+ if (!(strprefixeq(child->name, child->basenamelen, "endpoint")
||
+ get_property(child, "remote-endpoint")))
+ continue;
+
+ node->bus = _port_bus;
+
+ /* The parent of 'port' nodes can be either 'ports' or a device
*/
+ if (!node->parent->bus &&
+ (streq(node->parent->name, "ports") || get_property(node,
"reg")))
+ node->parent->bus = _ports_bus;
+
+ break;
+ }
+
+}
+WARNING(graph_nodes, check_graph_nodes, NULL);
+
+static void check_graph_child_address(struct check *c, struct dt_info *dti,
+ struct
[PATCH 5/7] Azure / GitLab / Travis: Add Kconfig unit tests to a job
The Kconfig language provides a unit test that can be run. As these
require pytest to be installed and run very quickly, bundle them in to
an existing CI job.
Signed-off-by: Tom Rini
---
.azure-pipelines.yml | 5 +++--
.gitlab-ci.yml | 7 ---
.travis.yml | 3 ++-
3 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index c22095830c0c..89aa5e46e298 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -110,7 +110,7 @@ jobs:
make tools-only_config envtools -j$(nproc)
- job: utils
-displayName: 'Run binman, buildman, dtoc and patman testsuites'
+displayName: 'Run binman, buildman, dtoc, Kconfig and patman testsuites'
pool:
vmImage: $(ubuntu_vm)
steps:
@@ -125,7 +125,7 @@ jobs:
export USER=azure
virtualenv -p /usr/bin/python3 /tmp/venv
. /tmp/venv/bin/activate
- pip install pyelftools
+ pip install pyelftools pytest
export UBOOT_TRAVIS_BUILD_DIR=/tmp/.bm-work/sandbox_spl
export PYTHONPATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt
export PATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}
@@ -134,6 +134,7 @@ jobs:
./tools/buildman/buildman -t
./tools/dtoc/dtoc -t
./tools/patman/patman --test
+ make testconfig
EOF
cat build.sh
# We cannot use "container" like other jobs above, as buildman
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index d486e72042fb..87231a039b48 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -150,7 +150,7 @@ Build envtools:
script:
- make tools-only_config envtools -j$(nproc)
-Run binman, buildman, dtoc and patman testsuites:
+Run binman, buildman, dtoc, Kconfig and patman testsuites:
tags: [ 'all' ]
stage: testsuites
script:
@@ -159,7 +159,7 @@ Run binman, buildman, dtoc and patman testsuites:
export USER=gitlab;
virtualenv -p /usr/bin/python3 /tmp/venv;
. /tmp/venv/bin/activate;
- pip install pyelftools;
+ pip install pyelftools pytest;
export UBOOT_TRAVIS_BUILD_DIR=/tmp/.bm-work/sandbox_spl;
export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt";
export PATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}";
@@ -167,7 +167,8 @@ Run binman, buildman, dtoc and patman testsuites:
./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test;
./tools/buildman/buildman -t;
./tools/dtoc/dtoc -t;
- ./tools/patman/patman --test
+ ./tools/patman/patman --test;
+ make testconfig
# Test sandbox with test.py
sandbox test.py:
diff --git a/.travis.yml b/.travis.yml
index e6db9d6a721a..53e4c2c12671 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -150,7 +150,8 @@ script:
./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test &&
./tools/patman/patman --test &&
./tools/buildman/buildman -t &&
- ./tools/dtoc/dtoc -t;
+ ./tools/dtoc/dtoc -t &&
+ make testconfig;
fi;
fi
--
2.17.1
[PATCH 3/7] Kconfig: Escape variables to make in default strings
We have some variables that need to include a variable to pass to make to evaluate later, typically ARCH and BOARDDIR, to find a file to use. The way we're doing this today isn't correct but works. With an update to Kconfig we will need to escape these properly, so do so. Cc: Masahiro Yamada Signed-off-by: Tom Rini --- arch/arm/mach-davinci/Kconfig | 2 +- arch/arm/mach-orion5x/Kconfig | 2 +- common/spl/Kconfig| 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 8a81c078811d..83f749c0440a 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -135,6 +135,6 @@ source "board/davinci/da8xxevm/Kconfig" source "board/lego/ev3/Kconfig" config SPL_LDSCRIPT - default "board/$(BOARDDIR)/u-boot-spl-da850evm.lds" + default "board/\$(BOARDDIR)/u-boot-spl-da850evm.lds" endif diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index 2984a3edda21..c4bc524eb81e 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -16,6 +16,6 @@ config SYS_SOC source "board/LaCie/edminiv2/Kconfig" config SPL_LDSCRIPT - default "$(CPUDIR)/orion5x/u-boot-spl.lds" if ORION5X + default "\$(CPUDIR)/orion5x/u-boot-spl.lds" if ORION5X endif diff --git a/common/spl/Kconfig b/common/spl/Kconfig index b03a476b9f69..9d52b75cb434 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -139,7 +139,7 @@ config SPL_HANDOFF config SPL_LDSCRIPT string "Linker script for the SPL stage" - default "arch/$(ARCH)/cpu/u-boot-spl.lds" + default "arch/\$(ARCH)/cpu/u-boot-spl.lds" help The SPL stage will usually require a different linker-script (as it runs from a different memory region) than the regular @@ -1306,7 +1306,7 @@ config TPL_LDSCRIPT string "Linker script for the TPL stage" depends on TPL default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64 - default "arch/$(ARCH)/cpu/u-boot-spl.lds" + default "arch/\$(ARCH)/cpu/u-boot-spl.lds" help The TPL stage will usually require a different linker-script (as it runs from a different memory region) than the regular -- 2.17.1
[PATCH 4/7] Kconfig: Remove redundant variable sets
In a few places we have Kconfig entries that set SPL_LDSCRIPT to what is the default value anyways. Drop these. Cc: Michal Simek Cc: Rick Chen Cc: Philippe Reynes Cc: Eric Jarrige Signed-off-by: Tom Rini --- arch/microblaze/Kconfig | 3 --- arch/riscv/Kconfig | 3 --- board/armadeus/apf27/Kconfig | 3 --- 3 files changed, 9 deletions(-) diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 5ce8261451d3..2bd260e5d76e 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -30,7 +30,4 @@ config STACK_SIZE source "board/xilinx/microblaze-generic/Kconfig" -config SPL_LDSCRIPT - default "arch/microblaze/cpu/u-boot-spl.lds" - endmenu diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 3338b788f84a..f49618d24d26 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -229,7 +229,4 @@ config STACK_SIZE_SHIFT int default 14 -config SPL_LDSCRIPT - default "arch/riscv/cpu/u-boot-spl.lds" - endmenu diff --git a/board/armadeus/apf27/Kconfig b/board/armadeus/apf27/Kconfig index a342d2e05ec5..65544a844834 100644 --- a/board/armadeus/apf27/Kconfig +++ b/board/armadeus/apf27/Kconfig @@ -1,8 +1,5 @@ if TARGET_APF27 -config SPL_LDSCRIPT - default "arch/$(ARCH)/cpu/u-boot-spl.lds" - config SYS_BOARD default "apf27" -- 2.17.1
[PATCH 2/7] mx31pdk: Move CONFIG_SPL_LDSCRIPT to defconfig
As there is only one mx31pdk config file and with upcoming updates to the Kconfig parsing logic, rather than have an entry in board/freescale/mx31pdk/Kconfig, move this single setting to the defconfig file. Cc: Magnus Lilja Signed-off-by: Tom Rini --- board/freescale/mx31pdk/Kconfig | 3 --- configs/mx31pdk_defconfig | 1 + 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/board/freescale/mx31pdk/Kconfig b/board/freescale/mx31pdk/Kconfig index b9fc2d517786..055545c93063 100644 --- a/board/freescale/mx31pdk/Kconfig +++ b/board/freescale/mx31pdk/Kconfig @@ -1,8 +1,5 @@ if TARGET_MX31PDK -config SPL_LDSCRIPT - default "arch/$(ARCH)/cpu/u-boot-spl.lds" - config SYS_BOARD default "mx31pdk" diff --git a/configs/mx31pdk_defconfig b/configs/mx31pdk_defconfig index 9ab4a09ea9cb..163f756b4afc 100644 --- a/configs/mx31pdk_defconfig +++ b/configs/mx31pdk_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_MX31=y +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/u-boot-spl.lds" CONFIG_SYS_TEXT_BASE=0x87e0 CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_TARGET_MX31PDK=y -- 2.17.1
[PATCH 1/7] misc: Add more -I$(objtree)/$(obj) lines
We have a few more places where we depend at build time on generated files being found within the compiler search path. Add appropriate -I lines in these places. Signed-off-by: Tom Rini --- cmd/Makefile| 2 ++ lib/Makefile| 1 + lib/crypto/Makefile | 4 3 files changed, 7 insertions(+) diff --git a/cmd/Makefile b/cmd/Makefile index f1dd513a4b41..8ae0478047e9 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -228,3 +228,5 @@ $(obj)/license_data_size.h: $(srctree)/Licenses/gpl-2.0.txt FORCE $(call filechk,data_size) CFLAGS_ethsw.o := -Wno-enum-conversion +CFLAGS_config.o += -I$(objtree)/$(obj) +CFLAGS_license.o += -I$(objtree)/$(obj) diff --git a/lib/Makefile b/lib/Makefile index 15259d0473c4..771e4de5a183 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -127,6 +127,7 @@ obj-y += date.o # Build a fast OID lookup registry from include/linux/oid_registry.h # obj-$(CONFIG_OID_REGISTRY) += oid_registry.o +CFLAGS_oid_registry.o += -I$(objtree)/$(obj) $(obj)/oid_registry.o: $(obj)/oid_registry_data.c diff --git a/lib/crypto/Makefile b/lib/crypto/Makefile index 8267fee0a7b8..96a3910872fd 100644 --- a/lib/crypto/Makefile +++ b/lib/crypto/Makefile @@ -47,3 +47,7 @@ pkcs7_message-y := \ $(obj)/pkcs7_parser.o: $(obj)/pkcs7.asn1.h $(obj)/pkcs7.asn1.o: $(obj)/pkcs7.asn1.c $(obj)/pkcs7.asn1.h + +CFLAGS_rsa_helper.o += -I$(objtree)/$(obj) +CFLAGS_pkcs7_parser.o += -I$(objtree)/$(obj) +CFLAGS_x509_cert_parser.o += -I$(objtree)/$(obj) -- 2.17.1
RE: [PATCH v4 01/14] misc: add driver for the SiFive otp controller
Hi,
> From: U-Boot On Behalf Of Pragnesh Patel
> Sent: lundi 24 février 2020 09:33
>
> Added a misc driver to handle OTP memory in SiFive SoCs.
>
> Signed-off-by: Pragnesh Patel
> ---
> drivers/misc/Kconfig | 7 ++
> drivers/misc/Makefile | 1 +
> drivers/misc/sifive-otp.c | 241 ++
> 3 files changed, 249 insertions(+)
> create mode 100644 drivers/misc/sifive-otp.c
>
> diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index
> f18aa8f7ba..fcb45c63d4 100644
> --- a/drivers/misc/Kconfig
> +++ b/drivers/misc/Kconfig
> @@ -68,6 +68,13 @@ config ROCKCHIP_OTP
> addressing and a length or through child-nodes that are generated
> based on the e-fuse map retrieved from the DTS.
>
> +config SIFIVE_OTP
> + bool "SiFive Ememory OTP driver"
> + depends on RISCV && MISC
> + help
> + Enable support for reading and writing the ememory OTP on the
> + SiFive SoCs.
> +
> config VEXPRESS_CONFIG
> bool "Enable support for Arm Versatile Express config bus"
> depends on MISC
> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index
> 2b843de93c..ee888631b6 100644
> --- a/drivers/misc/Makefile
> +++ b/drivers/misc/Makefile
> @@ -58,6 +58,7 @@ obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o
> obj-$(CONFIG_QFW) += qfw.o
> obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o
> obj-$(CONFIG_ROCKCHIP_OTP) += rockchip-otp.o
> +obj-$(CONFIG_SIFIVE_OTP) += sifive-otp.o
> obj-$(CONFIG_SANDBOX) += syscon_sandbox.o misc_sandbox.o
> obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
> obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o diff --git
> a/drivers/misc/sifive-otp.c b/drivers/misc/sifive-otp.c new file mode 100644
> index
> 00..6a39ec42df
> --- /dev/null
> +++ b/drivers/misc/sifive-otp.c
> @@ -0,0 +1,241 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * This is a driver for the eMemory EG004K32TQ028XW01 NeoFuse
> + * One-Time-Programmable (OTP) memory used within the SiFive FU540.
> + * It is documented in the FU540 manual here:
> + * https://www.sifive.com/documentation/chips/freedom-u540-c000-manual/
> + *
> + * Copyright (C) 2018 Philipp Hug
> + * Copyright (C) 2018 Joey Hewitt
> + *
> + * Copyright (C) 2020 SiFive, Inc
> + */
> +
> +/*
> + * The FU540 stores 4096x32 bit (16KiB) values.
> + * Index 0x00-0xff are reserved for SiFive internal use. (first 1KiB)
> + * Right now first 1KB is used to store only serial number.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#define BYTES_PER_FUSE 4
> +
> +#define PA_RESET_VAL 0x00
> +#define PAS_RESET_VAL0x00
> +#define PAIO_RESET_VAL 0x00
> +#define PDIN_RESET_VAL 0x00
> +#define PTM_RESET_VAL0x00
> +
> +#define PCLK_ENABLE_VAL BIT(0)
> +#define PCLK_DISABLE_VAL 0x00
> +
> +#define PWE_WRITE_ENABLE BIT(0)
> +#define PWE_WRITE_DISABLE0x00
> +
> +#define PTM_FUSE_PROGRAM_VAL BIT(1)
> +
> +#define PCE_ENABLE_INPUT BIT(0)
> +#define PCE_DISABLE_INPUT0x00
> +
> +#define PPROG_ENABLE_INPUT BIT(0)
> +#define PPROG_DISABLE_INPUT 0x00
> +
> +#define PTRIM_ENABLE_INPUT BIT(0)
> +#define PTRIM_DISABLE_INPUT 0x00
> +
> +#define PDSTB_DEEP_STANDBY_ENABLEBIT(0)
> +#define PDSTB_DEEP_STANDBY_DISABLE 0x00
> +
> +struct sifive_otp_regs {
> + u32 pa; /* Address input */
> + u32 paio; /* Program address input */
> + u32 pas;/* Program redundancy cell selection input */
> + u32 pce;/* OTP Macro enable input */
> + u32 pclk; /* Clock input */
> + u32 pdin; /* Write data input */
> + u32 pdout; /* Read data output */
> + u32 pdstb; /* Deep standby mode enable input (active low) */
> + u32 pprog; /* Program mode enable input */
> + u32 ptc;/* Test column enable input */
> + u32 ptm;/* Test mode enable input */
> + u32 ptm_rep;/* Repair function test mode enable input */
> + u32 ptr;/* Test row enable input */
> + u32 ptrim; /* Repair function enable input */
> + u32 pwe;/* Write enable input (defines program cycle) */
> +} __packed;
> +
> +struct sifive_otp_platdata {
> + struct sifive_otp_regs __iomem *regs;
> + u32 total_fuses;
> +};
> +
> +/*
> + * offset and size are assumed aligned to the size of the fuses (32bit).
> + */
> +static int sifive_otp_read(struct udevice *dev, int offset,
> +void *buf, int size)
> +{
> + struct sifive_otp_platdata *plat = dev_get_platdata(dev);
> + struct sifive_otp_regs *regs = (struct sifive_otp_regs *)plat->regs;
> +
> + int fuseidx = offset / BYTES_PER_FUSE;
> + int fusecount = size / BYTES_PER_FUSE;
> + u32 fusebuf[fusecount];
> +
> + /* check bounds */
> + if (offset < 0 || size < 0)
> + return -EINVAL;
> + if (fuseidx >=
RE: [PATCH v4 02/14] riscv: sifive: fu540: Use OTP DM driver for serial environment variable
Hi,
Just a warning as I had the same issue with 8729b1ae2cbd ("misc: Update read()
and write() methods to return bytes xfered")
> From: U-Boot On Behalf Of Pragnesh Patel
> Sent: lundi 24 février 2020 09:33
>
> Use the OTP DM driver to set the serial environment variable.
>
> Signed-off-by: Pragnesh Patel
> ---
> arch/riscv/dts/fu540-c000-u-boot.dtsi | 14 +++
> .../dts/hifive-unleashed-a00-u-boot.dtsi | 6 +
> board/sifive/fu540/Kconfig| 2 +
> board/sifive/fu540/fu540.c| 113 +++---
> 4 files changed, 62 insertions(+), 73 deletions(-) create mode 100644
> arch/riscv/dts/fu540-c000-u-boot.dtsi
> create mode 100644 arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
>
> diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi
> b/arch/riscv/dts/fu540-c000-u-
> boot.dtsi
> new file mode 100644
> index 00..31fd113c7d
> --- /dev/null
> +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
> @@ -0,0 +1,14 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * (C) Copyright 2019 SiFive, Inc
> + */
> +
> +/ {
> + soc {
> + otp: otp@1007 {
> + compatible = "sifive,fu540-otp";
> + reg = <0x0 0x1007 0x0 0x0FFF>;
> + fuse-count = <0x1000>;
> + };
> + };
> +};
> diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> b/arch/riscv/dts/hifive-
> unleashed-a00-u-boot.dtsi
> new file mode 100644
> index 00..bec0d19134
> --- /dev/null
> +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> @@ -0,0 +1,6 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019 SiFive, Inc
> + */
> +
> +#include "fu540-c000-u-boot.dtsi"
> diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig index
> 5ca21474de..900197bbb2 100644
> --- a/board/sifive/fu540/Kconfig
> +++ b/board/sifive/fu540/Kconfig
> @@ -48,5 +48,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
> imply SIFIVE_GPIO
> imply CMD_GPIO
> imply SMP
> + imply MISC
> + imply SIFIVE_OTP
>
> endif
> diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c index
> 47a2090251..409471effc 100644
> --- a/board/sifive/fu540/fu540.c
> +++ b/board/sifive/fu540/fu540.c
> @@ -10,94 +10,61 @@
> #include
> #include
> #include
> +#include
>
> -#ifdef CONFIG_MISC_INIT_R
> -
> -#define FU540_OTP_BASE_ADDR 0x1007
> -
> -struct fu540_otp_regs {
> - u32 pa; /* Address input */
> - u32 paio; /* Program address input */
> - u32 pas;/* Program redundancy cell selection input */
> - u32 pce;/* OTP Macro enable input */
> - u32 pclk; /* Clock input */
> - u32 pdin; /* Write data input */
> - u32 pdout; /* Read data output */
> - u32 pdstb; /* Deep standby mode enable input (active low) */
> - u32 pprog; /* Program mode enable input */
> - u32 ptc;/* Test column enable input */
> - u32 ptm;/* Test mode enable input */
> - u32 ptm_rep;/* Repair function test mode enable input */
> - u32 ptr;/* Test row enable input */
> - u32 ptrim; /* Repair function enable input */
> - u32 pwe;/* Write enable input (defines program cycle) */
> -} __packed;
> -
> -#define BYTES_PER_FUSE 4
> -#define NUM_FUSES0x1000
> -
> -static int fu540_otp_read(int offset, void *buf, int size) -{
> - struct fu540_otp_regs *regs = (void __iomem
> *)FU540_OTP_BASE_ADDR;
> - unsigned int i;
> - int fuseidx = offset / BYTES_PER_FUSE;
> - int fusecount = size / BYTES_PER_FUSE;
> - u32 fusebuf[fusecount];
> -
> - /* check bounds */
> - if (offset < 0 || size < 0)
> - return -EINVAL;
> - if (fuseidx >= NUM_FUSES)
> - return -EINVAL;
> - if ((fuseidx + fusecount) > NUM_FUSES)
> - return -EINVAL;
> -
> - /* init OTP */
> - writel(0x01, >pdstb); /* wake up from stand-by */
> - writel(0x01, >ptrim); /* enable repair function */
> - writel(0x01, >pce); /* enable input */
> -
> - /* read all requested fuses */
> - for (i = 0; i < fusecount; i++, fuseidx++) {
> - writel(fuseidx, >pa);
> -
> - /* cycle clock to read */
> - writel(0x01, >pclk);
> - mdelay(1);
> - writel(0x00, >pclk);
> - mdelay(1);
> -
> - /* read the value */
> - fusebuf[i] = readl(>pdout);
> - }
> -
> - /* shut down */
> - writel(0, >pce);
> - writel(0, >ptrim);
> - writel(0, >pdstb);
> -
> - /* copy out */
> - memcpy(buf, fusebuf, size);
> +/*
> + * This define is a value used for error/unknown serial.
> + * If we really care about distinguishing errors and 0 is
> + * valid, we'll need a different one.
> + */
> +#define ERROR_READING_SERIAL_NUMBER 0
>
> - return 0;
> -}
> +#ifdef CONFIG_MISC_INIT_R
>
> -static u32
[PATCHv2 1/4] kbuild: fixdep: Resync this with v4.17
The previous kbuild resync of e91610da7c8a ("kconfig: re-sync with Linux
4.17-rc4") accidentally did not sync the fixdep program. This commit
brings fixdep in line with the rest of that previous resync.
This includes all of the following Linux kernel commits:
fbfa9be9904e kbuild: move include/config/ksym/* to include/ksym/*
5b8ad96d1a44 fixdep: remove some false CONFIG_ matches
14a596a7e6fd fixdep: remove stale references to uml-config.h
ab9ce9feed36 fixdep: use existing helper to check modular CONFIG options
87b95a81357d fixdep: refactor parse_dep_file()
5d1ef76f5a22 fixdep: move global variables to local variables of main()
ccfe78873c22 fixdep: remove unneeded memcpy() in parse_dep_file()
4003fd80cba9 fixdep: factor out common code for reading files
01b5cbe7012f fixdep: use malloc() and read() to load dep_file to buffer
41f92cffba19 fixdep: remove unnecessary inclusion
7c2ec43a2154 fixdep: exit with error code in error branches of do_config_file()
4e433fc4d1a9 fixdep: trivial: typo fix and correction
dee81e988674 fixdep: faster CONFIG_ search
c1a95fda2a40 kbuild: add fine grained build dependencies for exported symbols
d8329e35cc08 fixdep: accept extra dependencies on stdin
4c835b57b8de fixdep: constify strrcmp arguments
Of note is that when applying dee81e988674 above our logic in that area
required some careful consideration to continue to apply.
[Fold in bugfix to allow us to include 638e69cf2230 from upstream]
Signed-off-by: Masahiro Yamada
[Merge everything to U-Boot, rework dee81e988674]
Signed-off-by: Tom Rini
---
scripts/basic/fixdep.c | 351 ++---
1 file changed, 150 insertions(+), 201 deletions(-)
diff --git a/scripts/basic/fixdep.c b/scripts/basic/fixdep.c
index 6a668f114096..a524f72e9e8b 100644
--- a/scripts/basic/fixdep.c
+++ b/scripts/basic/fixdep.c
@@ -25,7 +25,7 @@
*
* So we play the same trick that "mkdep" played before. We replace
* the dependency on autoconf.h by a dependency on every config
- * option which is mentioned in any of the listed prequisites.
+ * option which is mentioned in any of the listed prerequisites.
*
* kconfig populates a tree in include/config/ with an empty file
* for each config symbol and when the configuration is updated
@@ -34,7 +34,7 @@
* the config symbols are rebuilt.
*
* So if the user changes his CONFIG_HIS_DRIVER option, only the objects
- * which depend on "include/linux/config/his/driver.h" will be rebuilt,
+ * which depend on "include/config/his/driver.h" will be rebuilt,
* so most likely only his driver ;-)
*
* The idea above dates, by the way, back to Michael E Chastain, AFAIK.
@@ -75,15 +75,14 @@
* and then basically copies the ..d file to stdout, in the
* process filtering out the dependency on autoconf.h and adding
* dependencies on include/config/my/option.h for every
- * CONFIG_MY_OPTION encountered in any of the prequisites.
+ * CONFIG_MY_OPTION encountered in any of the prerequisites.
*
* It will also filter out all the dependencies on *.ver. We need
* to make sure that the generated version checksum are globally up
* to date before even starting the recursive build, so it's too late
* at this point anyway.
*
- * The algorithm to grep for "CONFIG_..." is bit unusual, but should
- * be fast ;-) We don't even try to really parse the header files, but
+ * We don't even try to really parse the header files, but
* merely grep, i.e. if CONFIG_FOO is mentioned in a comment, it will
* be picked up as well. It's not a problem with respect to
* correctness, since that can only give too many dependencies, thus
@@ -94,49 +93,57 @@
* (Note: it'd be easy to port over the complete mkdep state machine,
* but I don't think the added complexity is worth it)
*/
-/*
- * Note 2: if somebody writes HELLO_CONFIG_BOOM in a file, it will depend onto
- * CONFIG_BOOM. This could seem a bug (not too hard to fix), but please do not
- * fix it! Some UserModeLinux files (look at arch/um/) call CONFIG_BOOM as
- * UML_CONFIG_BOOM, to avoid conflicts with /usr/include/linux/autoconf.h,
- * through arch/um/include/uml-config.h; this fixdep "bug" makes sure that
- * those files will have correct dependencies.
- */
#include
#include
-#include
#include
#include
#include
#include
#include
-#include
#include
-#include
-
-#define INT_CONF ntohl(0x434f4e46)
-#define INT_ONFI ntohl(0x4f4e4649)
-#define INT_NFIG ntohl(0x4e464947)
-#define INT_FIG_ ntohl(0x4649475f)
-char *target;
-char *depfile;
-char *cmdline;
int is_spl_build = 0; /* hack for U-Boot */
static void usage(void)
{
- fprintf(stderr, "Usage: fixdep \n");
+ fprintf(stderr, "Usage: fixdep [-e] \n");
+ fprintf(stderr, " -e insert extra dependencies given on stdin\n");
exit(1);
}
/*
- * Print out the commandline prefixed with cmd_ :=
+ * Print out a dependency path from a symbol name
*/
-static void print_cmdline(void)
+static void print_dep(const char *m, int
[PATCHv2 4/4] scripts/Makefile.lib: Re-add -Wno-simple_bus_reg to DTC_FLAGS
This exists in Linux Kernel with commit 70523a3ce5ff so put it in the list of DTC_FLAGS that mirror Linux as we will catch up there. Signed-off-by: Tom Rini --- scripts/Makefile.lib | 1 + 1 file changed, 1 insertion(+) diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index a8196678b2e9..63d790e4e287 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -280,6 +280,7 @@ DTC_FLAGS += -Wno-unit_address_vs_reg \ -Wno-unit_address_format \ -Wno-avoid_unnecessary_addr_size \ -Wno-alias_paths \ + -Wno-simple_bus_reg \ -Wno-pci_device_reg # U-Boot specific disables -- 2.17.1
[PATCHv2 3/4] scripts/Makefile.lib: Restore PCI related warnings to DTC_FLAGS
While we are working on correcting usage related to the pci_bridge and pci_device_bus_num warnings, disable these flags for now. Signed-off-by: Tom Rini --- scripts/Makefile.lib | 4 1 file changed, 4 insertions(+) diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index bfb5851e9bfa..a8196678b2e9 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -281,6 +281,10 @@ DTC_FLAGS += -Wno-unit_address_vs_reg \ -Wno-avoid_unnecessary_addr_size \ -Wno-alias_paths \ -Wno-pci_device_reg + +# U-Boot specific disables +DTC_FLAGS += -Wno-pci_bridge \ +-Wno-pci_device_bus_num endif ifneq ($(findstring 2,$(KBUILD_ENABLE_EXTRA_GCC_CHECKS)),) -- 2.17.1
[PATCHv2 2/4] kbuild: Re-sync DTC flag logic with v4.17
The way that we have been handling additional DTC warning flags hasn't matched the way the Linux Kernel does. Resync this logic with v4.17. Signed-off-by: Tom Rini --- scripts/Makefile.extrawarn | 21 - scripts/Makefile.lib | 16 2 files changed, 16 insertions(+), 21 deletions(-) diff --git a/scripts/Makefile.extrawarn b/scripts/Makefile.extrawarn index 1105c76be12f..80231fbddfda 100644 --- a/scripts/Makefile.extrawarn +++ b/scripts/Makefile.extrawarn @@ -56,25 +56,4 @@ endif KBUILD_CFLAGS += $(warning) -dtc-warning-2 += -Wnode_name_chars_strict -dtc-warning-2 += -Wproperty_name_chars_strict - -dtc-warning := $(dtc-warning-$(findstring 1, $(KBUILD_ENABLE_EXTRA_GCC_CHECKS))) -dtc-warning += $(dtc-warning-$(findstring 2, $(KBUILD_ENABLE_EXTRA_GCC_CHECKS))) -dtc-warning += $(dtc-warning-$(findstring 3, $(KBUILD_ENABLE_EXTRA_GCC_CHECKS))) - -DTC_FLAGS += $(dtc-warning) - -else - -# Disable noisy checks by default -DTC_FLAGS += -Wno-unit_address_vs_reg -DTC_FLAGS += -Wno-simple_bus_reg -DTC_FLAGS += -Wno-unit_address_format -DTC_FLAGS += -Wno-pci_bridge -DTC_FLAGS += -Wno-pci_device_bus_num -DTC_FLAGS += -Wno-pci_device_reg -DTC_FLAGS += -Wno-avoid_unnecessary_addr_size -DTC_FLAGS += -Wno-alias_paths - endif diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 30f392fdfb08..bfb5851e9bfa 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -274,6 +274,22 @@ cmd_gzip = (cat $(filter-out FORCE,$^) | gzip -n -f -9 > $@) || \ # DTC # --- +# Disable noisy checks by default +ifeq ($(findstring 1,$(KBUILD_ENABLE_EXTRA_GCC_CHECKS)),) +DTC_FLAGS += -Wno-unit_address_vs_reg \ + -Wno-unit_address_format \ + -Wno-avoid_unnecessary_addr_size \ + -Wno-alias_paths \ + -Wno-pci_device_reg +endif + +ifneq ($(findstring 2,$(KBUILD_ENABLE_EXTRA_GCC_CHECKS)),) +DTC_FLAGS += -Wnode_name_chars_strict \ + -Wproperty_name_chars_strict +endif + +DTC_FLAGS += $(DTC_FLAGS_$(basetarget)) + # Generate an assembly file to wrap the output of the device tree compiler quiet_cmd_dt_S_dtb= DTB $@ # Modified for U-Boot -- 2.17.1
[PATCH 1/1] README: replace reference to boards.cfg
boards.cfg is not delivered with the U-Boot source. So it is preferable to look at configs/*_defconfig to identify available deconfigs. Fix a typo. Signed-off-by: Heinrich Schuchardt --- README | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/README b/README index 8cfa92fac9..d5d10d142e 100644 --- a/README +++ b/README @@ -3203,9 +3203,9 @@ is done by typing: make NAME_defconfig where "NAME_defconfig" is the name of one of the existing configu- -rations; see boards.cfg for supported names. +rations; see configs/*_defconfig for supported names. -Note: for some board special configuration names may exist; check if +Note: for some boards special configuration names may exist; check if additional information is available from the board vendor; for instance, the TQM823L systems are available without (standard) or with LCD support. You can select such additional "features" -- 2.25.0
[PATCH] spl.h: make self-contained
The static inline function spl_phase needs . Some functions take pointers to struct blk_desc or image_header. Add forward declarations. Signed-off-by: Masahiro Yamada --- include/spl.h | 4 1 file changed, 4 insertions(+) diff --git a/include/spl.h b/include/spl.h index 6087cd793c..5d8d14dbf5 100644 --- a/include/spl.h +++ b/include/spl.h @@ -10,9 +10,13 @@ /* Platform-specific defines */ #include +#include #include #include +struct blk_desc; +struct image_header; + /* Value in r0 indicates we booted from U-Boot */ #define UBOOT_NOT_LOADED_FROM_SPL 0x13578642 -- 2.17.1
[PATCH] debug_uart.h: make self-contained
'uint' is not a primitive type. You need to include
or otherwise change it to (unsigned int).
Signed-off-by: Masahiro Yamada
---
include/debug_uart.h | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/include/debug_uart.h b/include/debug_uart.h
index cd70ae1a04..4d1c58075c 100644
--- a/include/debug_uart.h
+++ b/include/debug_uart.h
@@ -88,28 +88,28 @@ void printascii(const char *str);
*
* @value: Value to output
*/
-void printhex2(uint value);
+void printhex2(unsigned int value);
/**
* printhex4() - Output a 4-digit hex value
*
* @value: Value to output
*/
-void printhex4(uint value);
+void printhex4(unsigned int value);
/**
* printhex8() - Output a 8-digit hex value
*
* @value: Value to output
*/
-void printhex8(uint value);
+void printhex8(unsigned int value);
/**
* printdec() - Output a decimalism value
*
* @value: Value to output
*/
-void printdec(uint value);
+void printdec(unsigned int value);
#ifdef CONFIG_DEBUG_UART_ANNOUNCE
#define _DEBUG_UART_ANNOUNCE printascii(" ");
@@ -151,34 +151,34 @@ void printdec(uint value);
_printch(*str++); \
} \
\
- static inline void printhex1(uint digit) \
+ static inline void printhex1(unsigned int digit) \
{ \
digit &= 0xf; \
_debug_uart_putc(digit > 9 ? digit - 10 + 'a' : digit + '0'); \
} \
\
- static inline void printhex(uint value, int digits) \
+ static inline void printhex(unsigned int value, int digits) \
{ \
while (digits-- > 0) \
printhex1(value >> (4 * digits)); \
} \
\
- void printhex2(uint value) \
+ void printhex2(unsigned int value) \
{ \
printhex(value, 2); \
} \
\
- void printhex4(uint value) \
+ void printhex4(unsigned int value) \
{ \
printhex(value, 4); \
} \
\
- void printhex8(uint value) \
+ void printhex8(unsigned int value) \
{ \
printhex(value, 8); \
} \
\
- void printdec(uint value) \
+ void printdec(unsigned int value) \
{ \
if (value > 10) { \
printdec(value / 10); \
--
2.17.1
[PATCH] mmc: make self-contained
This header uses bd_t without including its definition. Change it to (struct bd_info), and add the forward declaration to specify it as a structure. Signed-off-by: Masahiro Yamada --- include/mmc.h | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/include/mmc.h b/include/mmc.h index 71e2e1735a..4bdeb929d7 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -15,6 +15,8 @@ #include #include +struct bd_info; + #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) #define MMC_SUPPORTS_TUNING #endif @@ -712,7 +714,7 @@ void mmc_destroy(struct mmc *mmc); * @return 0 if OK, -ve on error */ int mmc_unbind(struct udevice *dev); -int mmc_initialize(bd_t *bis); +int mmc_initialize(struct bd_info *bis); int mmc_init_device(int num); int mmc_init(struct mmc *mmc); int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error); @@ -857,8 +859,8 @@ void mmc_set_preinit(struct mmc *mmc, int preinit); #endif void board_mmc_power_init(void); -int board_mmc_init(bd_t *bis); -int cpu_mmc_init(bd_t *bis); +int board_mmc_init(struct bd_info *bis); +int cpu_mmc_init(struct bd_info *bis); int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr); # ifdef CONFIG_SYS_MMC_ENV_PART extern uint mmc_get_env_part(struct mmc *mmc); -- 2.17.1
[PATCH] asm-generic/u-boot.h: make self-contained
This header uses 'phys_addr_t' and 'ulong'. Include the definitions. Signed-off-by: Masahiro Yamada --- include/asm-generic/u-boot.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h index eee84f49bb..d0fd24446f 100644 --- a/include/asm-generic/u-boot.h +++ b/include/asm-generic/u-boot.h @@ -15,6 +15,8 @@ #ifndef __ASM_GENERIC_U_BOOT_H__ #define __ASM_GENERIC_U_BOOT_H__ +#include + /* * Board information passed to Linux kernel from U-Boot * -- 2.17.1
[PATCH] global_data.h: make self-contained
The compiler never knows what 'bd_t' is without including .
By changing it to (struct bd_info), the compiler learns it is struct.
Signed-off-by: Masahiro Yamada
---
Maybe, we should replace 'bd_t' with 'struct bd_info' globally
by using coccinelle or something.
Linux coding style (Documentation/process/coding-style.rst)
apparently discourages typedef for cases like this.
include/asm-generic/global_data.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/asm-generic/global_data.h
b/include/asm-generic/global_data.h
index 5d027329fe..d9e220cfe3 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -25,7 +25,7 @@
#include
typedef struct global_data {
- bd_t *bd;
+ struct bd_info *bd;
unsigned long flags;
unsigned int baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
--
2.17.1
RE: [PATCH 1/1] stm32mp1: rng: remove superfluous assignment
Hi,
> From: U-Boot On Behalf Of Heinrich Schuchardt
> Sent: dimanche 16 février 2020 10:11
>
> We should not assign a value that is overwritten before use.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> drivers/rng/stm32mp1_rng.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/rng/stm32mp1_rng.c b/drivers/rng/stm32mp1_rng.c index
> dab3b995eb..e0f0a66c6e 100644
> --- a/drivers/rng/stm32mp1_rng.c
> +++ b/drivers/rng/stm32mp1_rng.c
> @@ -33,7 +33,7 @@ struct stm32_rng_platdata {
>
> static int stm32_rng_read(struct udevice *dev, void *data, size_t len) {
> - int retval = 0, i;
> + int retval, i;
> u32 sr, count, reg;
> size_t increment;
> struct stm32_rng_platdata *pdata = dev_get_platdata(dev);
> --
> 2.25.0
Reviewed-by: Patrick Delaunay
Regards
Patrick
Aw: [U-Boot 1/1] eth: mtk-eth: add mt7531 switch support in mediatek eth driver
Hi Tested this Patch on bananapi-r64 and bananapi-r2, on both loading kernel/fdt from tftp. Tested-by: Frank Wunderlich regards Frank
[PATCH] Azure / GitLab: Update Docker image
Bring in a newer Docker image to build on that has everything required for running 'make htmldocs'. Signed-off-by: Tom Rini --- .azure-pipelines.yml | 2 +- .gitlab-ci.yml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index c22095830c0c..c2f7f0f1337a 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -1,7 +1,7 @@ variables: windows_vm: vs2017-win2016 ubuntu_vm: ubuntu-18.04 - ci_runner_image: trini/u-boot-gitlab-ci-runner:bionic-20200112-07Feb2020 + ci_runner_image: trini/u-boot-gitlab-ci-runner:bionic-20200112-21Feb2020 # Add '-u 0' options for Azure pipelines, otherwise we get "permission # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer", # since our $(ci_runner_image) user is not root. diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index d486e72042fb..a525ea2ce020 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -2,7 +2,7 @@ # Grab our configured image. The source for this is found at: # https://gitlab.denx.de/u-boot/gitlab-ci-runner -image: trini/u-boot-gitlab-ci-runner:bionic-20200112-07Feb2020 +image: trini/u-boot-gitlab-ci-runner:bionic-20200112-21Feb2020 # We run some tests in different order, to catch some failures quicker. stages: -- 2.17.1
Re: [U-Boot] [PATCH] usb: ehci-mx5: Fix bus enumeration for DM case
Hi Marek,
> On Thu, 20 Jun 2019 22:53:58 +0200
> Marek Vasut wrote:
>
> > It is likely that the DM conversion of EHCI iMX5 driver was a
> > derivative of EHCI VF, however the conversion is incomplete and is
> > missing the bind workaround, which updates dev->seq number. Without
> > this, all controllers have dev->seq number 0 . Add this bind
> > workaround into EHCI iMX5 driver as well.
> >
> > Signed-off-by: Marek Vasut
> > Cc: Abel Vesa
> > Cc: Adam Ford
> > Cc: Fabio Estevam
> > Cc: Ludwig Zenz
> > Cc: Peng Fan
> > Cc: Stefano Babic
> > Cc: Vagrant Cascadian
> > ---
> > drivers/usb/host/ehci-mx5.c | 17 +
> > 1 file changed, 17 insertions(+)
> >
> > diff --git a/drivers/usb/host/ehci-mx5.c
> > b/drivers/usb/host/ehci-mx5.c index 0b32728c57..4db513f4e5 100644
> > --- a/drivers/usb/host/ehci-mx5.c
> > +++ b/drivers/usb/host/ehci-mx5.c
> > @@ -301,6 +301,22 @@ static int ehci_usb_ofdata_to_platdata(struct
> > udevice *dev) return 0;
> > }
> >
> > +static int ehci_usb_bind(struct udevice *dev)
> > +{
> > + static int num_controllers;
> > +
> > + /*
> > +* Without this hack, if we return ENODEV for USB
> > Controller 0, on
> > +* probe for the next controller, USB Controller 1 will be
> > given a
> > +* sequence number of 0. This conflicts with our
> > requirement of
> > +* sequence numbers while initialising the peripherals.
> > +*/
> > + dev->req_seq = num_controllers;
> > + num_controllers++;
> > +
> > + return 0;
> > +}
> > +
> > static int ehci_usb_probe(struct udevice *dev)
> > {
> > struct usb_platdata *plat = dev_get_platdata(dev);
> > @@ -362,6 +378,7 @@ U_BOOT_DRIVER(usb_mx5) = {
> > .id = UCLASS_USB,
> > .of_match = mx5_usb_ids,
> > .ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
> > + .bind = ehci_usb_bind,
> > .probe = ehci_usb_probe,
> > .remove = ehci_deregister,
> > .ops= _usb_ops,
>
> Tested-by: Lukasz Majewski
>
> Tested on HSC|DDC i.MX53 board (usb start works as previously).
>
Gentle ping on this patch :-)
It must have been overlooked in some way ...
Marek, could you please apply this fix?
Otherwise kp_imx53 boards (and probably some other ones) are broken -
and cannot be easily debricked.
> master branch
> SHA1: 77f6e2dd0551d8a825bab391a1bd6b838874bcd4
It applies also on top of newest -master:
SHA1: 8e51bf746a11d7f67416859da73a83109af4e0a3
Thanks in advance.
>
> Best regards,
>
> Lukasz Majewski
>
> --
>
> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> lu...@denx.de
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de
pgp8pACpnwfJo.pgp
Description: OpenPGP digital signature
Re: spi_flash_read issue
Hello Fabio, It's IMX6UL. I didn't know why I had that strange issue. With you suggestion, I switched to the latest version from the mainline U-Boot and it solved the issue. Thank you, Dan -- Sent from: http://u-boot.10912.n7.nabble.com/
Re: [PATCH v3 15/21] reset: add driver for generic reset controllers
On Sat, 25 Jan 2020 17:52:57 +0530
Amit Singh Tomar wrote:
Hi,
> The simplest and most generic form of a reset controller just exposes
> multiple MMIO registers, where each bit toggles a separate reset line.
> Add a generic driver to describe this kind of reset controller.
>
> This is used on the Action Semi S700, for instance, but also by other
> SoCs.
As tempting as this may be, but the S900 uses the more common style of
integrating the reset controller in the CMU device:
mmc0: mmc@e033 {
...
clocks = < CLK_SD0>;
resets = < RESET_SD0>;
...
So you should probably follow suit here for the S700 as well, especially as the
Linux S700 CMU driver already defines resets, they just don't seem to be used
yet.
So please drop this patch and the next one, and integrate the reset
functionality in clk_owl.c, similar to what we do for sunxi.
Cheers,
Andre.
>
> Signed-off-by: Amit Singh Tomar
> [Andre: make more generic, let it cover multiple registers, slight rework]
> Signed-off-by: Andre Przywara
> ---
> Changes since v2:
> * Newly added patch, not there in v2/v1.
> ---
> drivers/reset/Kconfig | 6 +++
> drivers/reset/Makefile| 1 +
> drivers/reset/reset-generic.c | 111
> ++
> 3 files changed, 118 insertions(+)
> create mode 100644 drivers/reset/reset-generic.c
>
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index 75ccd65..1cdc159 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -12,6 +12,12 @@ config DM_RESET
> although driving such reset isgnals using GPIOs may be more
> appropriate in this case.
>
> +config GENERIC_RESET
> +bool "Generic Reset controller driver"
> +depends on DM_RESET
> +help
> + Support Generic reset controller.
> +
> config SANDBOX_RESET
> bool "Enable the sandbox reset test driver"
> depends on DM_MAILBOX && SANDBOX
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index 0a044d5..5e027a1 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -4,6 +4,7 @@
> #
>
> obj-$(CONFIG_DM_RESET) += reset-uclass.o
> +obj-$(CONFIG_GENERIC_RESET) += reset-generic.o
> obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o
> obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
> obj-$(CONFIG_STI_RESET) += sti-reset.o
> diff --git a/drivers/reset/reset-generic.c b/drivers/reset/reset-generic.c
> new file mode 100644
> index 000..9c45087
> --- /dev/null
> +++ b/drivers/reset/reset-generic.c
> @@ -0,0 +1,111 @@
> +/*
> + * Copyright (C) 2017 Amit Singh Tomar
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct generic_reset_priv {
> + void __iomem *membase;
> + int max_reset;
> +};
> +
> +#define BITS_PER_BYTE 8
> +static int generic_reset_toggle(struct reset_ctl *rst, bool assert)
> +{
> + struct generic_reset_priv *priv = dev_get_priv(rst->dev);
> + int reg_width = sizeof(u32);
> + int bank, offset;
> + u32 reg;
> +
> + if (rst->id >= priv->max_reset)
> + return -EINVAL;
> +
> + bank = rst->id / (reg_width * BITS_PER_BYTE);
> + offset = rst->id % (reg_width * BITS_PER_BYTE);
> +
> + reg = readl(priv->membase + (bank * reg_width));
> + if (assert)
> + writel(reg & ~BIT(offset), priv->membase + (bank * reg_width));
> + else
> + writel(reg | BIT(offset), priv->membase + (bank * reg_width));
> +
> + return 0;
> +}
> +
> +static int generic_reset_assert(struct reset_ctl *rst)
> +{
> + return generic_reset_toggle(rst, true);
> +}
> +
> +static int generic_reset_deassert(struct reset_ctl *rst)
> +{
> + return generic_reset_toggle(rst, false);
> +}
> +
> +static int generic_reset_free(struct reset_ctl *rst)
> +{
> + return 0;
> +}
> +
> +static int generic_reset_request(struct reset_ctl *rst)
> +{
> + struct generic_reset_priv *priv = dev_get_priv(rst->dev);
> +
> + if (rst->id >= priv->max_reset)
> + return -EINVAL;
> +
> + return generic_reset_assert(rst);
> +}
> +
> +struct reset_ops generic_reset_reset_ops = {
> + .free = generic_reset_free,
> + .request = generic_reset_request,
> + .rst_assert = generic_reset_assert,
> + .rst_deassert = generic_reset_deassert,
> +};
> +
> +static const struct udevice_id generic_reset_ids[] = {
> + { .compatible = "generic-reset" },
> + { .compatible = "actions,s700-reset" },
> + { }
> +};
> +
> +static int generic_reset_probe(struct udevice *dev)
> +{
> + struct generic_reset_priv *priv = dev_get_priv(dev);
> + fdt_addr_t addr;
> + fdt_size_t size;
> +
> + addr = devfdt_get_addr_size_index(dev, 0, );
> + if (addr == FDT_ADDR_T_NONE)
> + return -EINVAL;
> +
> +
Re: [PATCH 3/5] env/fat.c: remove private CMD_SAVEENV logic
On 21/02/2020 17.19, Tom Rini wrote: > On Fri, Feb 21, 2020 at 05:14:14PM +0100, Wolfgang Denk wrote: >> Dear Rasmus, >> >> In message <5265fdd5-3992-4e5f-3235-5586b3b77...@prevas.dk> you wrote: >>> >>> So without the fat.c patch, CONFIG_SPL_SAVEENV is effectively ignored. >> >> OK, but what about bords that don't store the envionment in a file >> system, but instead for example in (parallel or SPI) NOR flash or in >> a UBI volume? > > I think the intent is that there is no change today but the door is now > open for someone that can test / confirm changes there to do so. Yes, exactly. I could have just fixed sf.c which is the one I need for my current project, but it turns out that without the ability to say CONFIG_IS_ENABLED(SAVEENV) the changes to sf.c would be significantly uglier, so it seemed better to provide the infrastructure that will also be useful for converting other storage drivers to honour CONFIG_SPL_SAVEENV. Rasmus
Re: [PATCH v3 09/21] arm: dts: Use consistent name "CLK_ETHERNET" for the Ethernet clock binding
On Mon, Feb 24, 2020 at 02:37:22PM +, Andre Przywara wrote: > On Sun, 23 Feb 2020 23:08:25 +0530 > Manivannan Sadhasivam wrote: > > Hi Amit, > > > On Sat, Jan 25, 2020 at 05:52:51PM +0530, Amit Singh Tomar wrote: > > > Right now, Clock bindings for ethernet uses different names(even in Linux) > > > CLK_ETH_MAC for S900 and CLK_ETHERNET for S700, It causes compilation > > > problem > > > when using them for common clock driver. > > > > > > Let's use same name CLK_ETHERNET for both S700 and S900. > > So are you changing the include file that you just imported from Linux? I > don't think that's a good idea, as you start to divert from the kernel in a > subtle way. And especially the header files should stay unchanged. > So either you send this patch to the kernel first, or, probably better, you > drop this change here, and unify the name at the point where it's used > (#ifndef CLK_ETHERNET ) > Good point. I'm happy to accept this change in kernel but not sure what Andreas will say. Thanks, Mani > Cheers, > Andre. > > > > > > > Signed-off-by: Amit Singh Tomar > > > > Reviewed-by: Manivannan Sadhasivam > > > > Thanks, > > Mani > > > > > --- > > > Changes since v2: > > > * Newly added patch, not there in v2/v1. > > > --- > > > include/dt-bindings/clock/actions,s900-cmu.h | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/include/dt-bindings/clock/actions,s900-cmu.h > > > b/include/dt-bindings/clock/actions,s900-cmu.h > > > index 7c12515..2247f1c 100644 > > > --- a/include/dt-bindings/clock/actions,s900-cmu.h > > > +++ b/include/dt-bindings/clock/actions,s900-cmu.h > > > @@ -121,7 +121,7 @@ > > > #define CLK_DDR1 97 > > > #define CLK_DMM 98 > > > > > > -#define CLK_ETH_MAC 99 > > > +#define CLK_ETHERNET 99 > > > #define CLK_RMII_REF 100 > > > > > > #define CLK_NR_CLKS (CLK_RMII_REF + 1) > > > -- > > > 2.7.4 > > > >
Re: [PATCH v3 09/21] arm: dts: Use consistent name "CLK_ETHERNET" for the Ethernet clock binding
On Sun, 23 Feb 2020 23:08:25 +0530 Manivannan Sadhasivam wrote: Hi Amit, > On Sat, Jan 25, 2020 at 05:52:51PM +0530, Amit Singh Tomar wrote: > > Right now, Clock bindings for ethernet uses different names(even in Linux) > > CLK_ETH_MAC for S900 and CLK_ETHERNET for S700, It causes compilation > > problem > > when using them for common clock driver. > > > > Let's use same name CLK_ETHERNET for both S700 and S900. So are you changing the include file that you just imported from Linux? I don't think that's a good idea, as you start to divert from the kernel in a subtle way. And especially the header files should stay unchanged. So either you send this patch to the kernel first, or, probably better, you drop this change here, and unify the name at the point where it's used (#ifndef CLK_ETHERNET ) Cheers, Andre. > > > > Signed-off-by: Amit Singh Tomar > > Reviewed-by: Manivannan Sadhasivam > > Thanks, > Mani > > > --- > > Changes since v2: > > * Newly added patch, not there in v2/v1. > > --- > > include/dt-bindings/clock/actions,s900-cmu.h | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/include/dt-bindings/clock/actions,s900-cmu.h > > b/include/dt-bindings/clock/actions,s900-cmu.h > > index 7c12515..2247f1c 100644 > > --- a/include/dt-bindings/clock/actions,s900-cmu.h > > +++ b/include/dt-bindings/clock/actions,s900-cmu.h > > @@ -121,7 +121,7 @@ > > #define CLK_DDR1 97 > > #define CLK_DMM98 > > > > -#define CLK_ETH_MAC99 > > +#define CLK_ETHERNET 99 > > #define CLK_RMII_REF 100 > > > > #define CLK_NR_CLKS(CLK_RMII_REF + 1) > > -- > > 2.7.4 > >
[PATCH] spi: cadence-qspi: Move ref clock calculation to probe
"assigned-clock-parents" and "assigned-clock-rates" DT properties take
effect only after ofdata_to_platdata() when clk_set_defaults() is called
in device_probe(). Therefore clk get rate() would return a wrong value
in ofdata_to_platdata() when compared with probe. Hence it needs to be
moved to probe.
Tested on u-boot-ti/next.
Signed-off-by: Pratyush Yadav
---
drivers/spi/cadence_qspi.c | 33 +
1 file changed, 17 insertions(+), 16 deletions(-)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 83b114ffe7..994a5948f1 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -166,11 +166,28 @@ static int cadence_spi_probe(struct udevice *bus)
{
struct cadence_spi_platdata *plat = bus->platdata;
struct cadence_spi_priv *priv = dev_get_priv(bus);
+ struct clk clk;
int ret;
priv->regbase = plat->regbase;
priv->ahbbase = plat->ahbbase;
+ if (plat->ref_clk_hz == 0) {
+ ret = clk_get_by_index(bus, 0, );
+ if (ret) {
+#ifdef CONFIG_CQSPI_REF_CLK
+ plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK;
+#else
+ return ret;
+#endif
+ } else {
+ plat->ref_clk_hz = clk_get_rate();
+ clk_free();
+ if (IS_ERR_VALUE(plat->ref_clk_hz))
+ return plat->ref_clk_hz;
+ }
+ }
+
ret = reset_get_bulk(bus, >resets);
if (ret)
dev_warn(bus, "Can't get reset: %d\n", ret);
@@ -268,8 +285,6 @@ static int cadence_spi_ofdata_to_platdata(struct udevice
*bus)
{
struct cadence_spi_platdata *plat = bus->platdata;
ofnode subnode;
- struct clk clk;
- int ret;
plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
plat->ahbbase = (void *)devfdt_get_addr_size_index(bus, 1,
@@ -305,20 +320,6 @@ static int cadence_spi_ofdata_to_platdata(struct udevice
*bus)
plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20);
plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20);
- ret = clk_get_by_index(bus, 0, );
- if (ret) {
-#ifdef CONFIG_CQSPI_REF_CLK
- plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK;
-#else
- return ret;
-#endif
- } else {
- plat->ref_clk_hz = clk_get_rate();
- clk_free();
- if (IS_ERR_VALUE(plat->ref_clk_hz))
- return plat->ref_clk_hz;
- }
-
debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
__func__, plat->regbase, plat->ahbbase, plat->max_hz,
plat->page_size);
--
2.25.0
[PATCH 1/3] clk: imx6: Add definition for IMX6QDL_CLK_ENET clock
After commit 673f6597321d ("net: fec_mxc: support i.MX8M with CLK_CCF") all
NXP boards, which are not IMX8 and in the same time are supporting CCF
need to provide IMX6QDL_CLK_ENET.
This change defines the missing clock in i.MX6Q's CCF.
Signed-off-by: Lukasz Majewski
---
drivers/clk/imx/clk-imx6q.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index bd0d3e4f47..ace60ecec6 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -182,6 +182,7 @@ static int imx6q_clk_probe(struct udevice *dev)
clk_dm(IMX6QDL_CLK_I2C2,
imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8));
+ clk_dm(IMX6QDL_CLK_ENET, imx_clk_gate2("enet", "ipg", base + 0x6c, 10));
return 0;
}
--
2.20.1
[PATCH 2/3] clk: imx: Add support for pllv3 enet clock
This code has been ported from Linux kernel v5.5.5 (tag) and has been
adjusted to U-Boot's DM.
It adds support for correct recognition of IMX_PLLV3_ENET flag in the
clk-pllv3.c driver.
Signed-off-by: Lukasz Majewski
---
drivers/clk/imx/clk-pllv3.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index 525442debf..88baf10f6a 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -20,6 +20,7 @@
#define UBOOT_DM_CLK_IMX_PLLV3_SYS "imx_clk_pllv3_sys"
#define UBOOT_DM_CLK_IMX_PLLV3_USB "imx_clk_pllv3_usb"
#define UBOOT_DM_CLK_IMX_PLLV3_AV "imx_clk_pllv3_av"
+#define UBOOT_DM_CLK_IMX_PLLV3_ENET "imx_clk_pllv3_enet"
#define PLL_NUM_OFFSET 0x10
#define PLL_DENOM_OFFSET 0x20
@@ -34,6 +35,7 @@ struct clk_pllv3 {
boolpowerup_set;
u32 div_mask;
u32 div_shift;
+ unsigned long ref_clock;
};
#define to_clk_pllv3(_clk) container_of(_clk, struct clk_pllv3, clk)
@@ -224,6 +226,19 @@ static const struct clk_ops clk_pllv3_av_ops = {
.set_rate = clk_pllv3_av_set_rate,
};
+static ulong clk_pllv3_enet_get_rate(struct clk *clk)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(clk);
+
+ return pll->ref_clock;
+}
+
+static const struct clk_ops clk_pllv3_enet_ops = {
+ .enable = clk_pllv3_generic_enable,
+ .disable= clk_pllv3_generic_disable,
+ .get_rate = clk_pllv3_enet_get_rate,
+};
+
struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
const char *parent_name, void __iomem *base,
u32 div_mask)
@@ -260,6 +275,10 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const
char *name,
pll->div_shift = 0;
pll->powerup_set = false;
break;
+ case IMX_PLLV3_ENET:
+ drv_name = UBOOT_DM_CLK_IMX_PLLV3_ENET;
+ pll->ref_clock = 5;
+ break;
default:
kfree(pll);
return ERR_PTR(-ENOTSUPP);
@@ -305,3 +324,9 @@ U_BOOT_DRIVER(clk_pllv3_av) = {
.ops= _pllv3_av_ops,
.flags = DM_FLAG_PRE_RELOC,
};
+
+U_BOOT_DRIVER(clk_pllv3_enet) = {
+ .name = UBOOT_DM_CLK_IMX_PLLV3_ENET,
+ .id = UCLASS_CLK,
+ .ops= _pllv3_enet_ops,
+};
--
2.20.1
Re: [PATCH 1/2] Makefile: Add environment variable DEVICE_TREE to header
On Tue, Feb 18, 2020 at 05:02:36PM +0100, Michal Simek wrote:
> Users have option to overwrite default device tree
> (CONFIG_DEFAULT_DEVICE_TREE) via environment variable DEVICE_TREE.
>
> Feature has been added long time ago by commit 74de8c9a1672
> ("dts/Makefile: Build the user specified dts") for a little bit different
> reason.
>
> But this variable can be also used for different purpose like choosing
> proper configuration from FIT image in SPL.
> And this is the functionality I would like to use on Xilinx Zynq devices
> that current u-boot.img can be composed in the same way based on OF_LIST
> and different configuration is taken based on platform specific SPL.
> SPL requires low level ps7_init_gpl configuration that's why different
> boards require different SPL with fixed board_fit_config_name_match().
>
> Signed-off-by: Michal Simek
Reviewed-by: Tom Rini
--
Tom
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[PATCH 0/3] clk: Fix ETH initialization on i.MX6Q boards using CCF
This short patch series fixes boards, which after the commit 673f6597321d
("net: fec_mxc: support i.MX8M with CLK_CCF") were required to support in
CCF 'ipg' (i.e. IMX6QDL_CLK_ENET) and 'ptp' (i.e. IMX6QDL_CLK_ENET_REF)
clocks during ETH initialization.
Lack of those clocks supported in CCF resulted in non-functional ETH.
Lukasz Majewski (3):
clk: imx6: Add definition for IMX6QDL_CLK_ENET clock
clk: imx: Add support for pllv3 enet clock
clk: imx6: Add definition for IMX6QDL_CLK_ENET_REF clock
drivers/clk/imx/clk-imx6q.c | 8
drivers/clk/imx/clk-pllv3.c | 25 +
2 files changed, 33 insertions(+)
--
2.20.1
[PATCH 3/3] clk: imx6: Add definition for IMX6QDL_CLK_ENET_REF clock
After commit 673f6597321d ("net: fec_mxc: support i.MX8M with CLK_CCF") all
NXP boards, which are not IMX8 and in the same time are supporting CCF need
to provide PTP clock.
On the i.MX6Q this clock is provided with IMX6QDL_CLK_ENET_REF in the Linux
kernel's CCF.
Code in this change models the simplest case when enet reference clock is
generated from 'osc' clock.
Signed-off-by: Lukasz Majewski
---
drivers/clk/imx/clk-imx6q.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index ace60ecec6..0f4c1f881d 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -112,6 +112,10 @@ static int imx6q_clk_probe(struct udevice *dev)
imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0));
clk_dm(IMX6QDL_CLK_PLL2_PFD2_396M,
imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2));
+ clk_dm(IMX6QDL_CLK_PLL6,
+ imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3));
+ clk_dm(IMX6QDL_CLK_PLL6_ENET,
+ imx_clk_gate("pll6_enet", "pll6", base + 0xe0, 13));
/* CCM clocks */
base = dev_read_addr_ptr(dev);
@@ -183,6 +187,9 @@ static int imx6q_clk_probe(struct udevice *dev)
imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8));
clk_dm(IMX6QDL_CLK_ENET, imx_clk_gate2("enet", "ipg", base + 0x6c, 10));
+ clk_dm(IMX6QDL_CLK_ENET_REF,
+ imx_clk_fixed_factor("enet_ref", "pll6_enet", 1, 1));
+
return 0;
}
--
2.20.1
Re: [U-Boot] Sharing a hardware lab
Hello Simon, On Sun, 2020-02-23 at 19:34 -0700, Simon Glass wrote: > Hi Heiko, > > Thanks for the hints! I pushed your things here: > > https://github.com/sglass68/tbot/tree/simon > > Then I try: > tbot -l kea.py -b pcduino3.py uboot_build > > and get an error: > > tbot starting ... > type > ├─Calling uboot_build ... > │ └─Fail. (0.000s) > ├─Exception: > │ Traceback (most recent call last): > │ File > "/home/sglass/.local/lib/python3.6/site-packages/tbot-0.8.0-py3.6.egg/tbot/main.py", > line 318, in main > │ func(**params) > │ File > "/home/sglass/.local/lib/python3.6/site-packages/tbot-0.8.0-py3.6.egg/tbot/decorators.py", > line 103, in wrapped > │ result = tc(*args, **kwargs) > │ File > "/home/sglass/.local/lib/python3.6/site-packages/tbot-0.8.0-py3.6.egg/tbot/tc/uboot/build.py", > line 271, in _build > │ builder = UBootBuilder._get_selected_builder() > │ File > "/home/sglass/.local/lib/python3.6/site-packages/tbot-0.8.0-py3.6.egg/tbot/tc/uboot/build.py", > line 160, in _get_selected_builder > │ builder = getattr(tbot.selectable.UBootMachine, "build") > │ AttributeError: type object 'UBootMachine' has no attribute 'build' > > I'm a bit lost in all the classes and functions. A working example or > a patch would be great! > > I've pushed all my scripts here: > > https://github.com/sglass68/ubtest > > The top commit is your patches. I think you mixed a few things up while adding Heiko's stuff. Instead of your last commit, attempt the attached patch. It is untested of course but should point you in the right direction; here is a short summary of what it adds: 1. Your `kea` lab needs to be marked as a build-host. This means it needs the `toolchains` property which returns what toolchains are available. I added a dummy armv7-a toolchain which might need a bit more adjustment to work for you. 2. I created a UBootBuilder for pcduino3. This builder just specifies what defconfig to build and what toolchain to use (need to be defined in the selected lab). Heiko's builder config is a bit more elaborate and also does some patching after applying the defconfig. This is of course also possible if you want to. 3. I added a U-Boot config for your board which is needed because its `build` property specifies which U-Boot builder to use. This will make the `uboot_build` testcase work properly. Later you might want to adjust this U-Boot config to actually work so you can make use of it for flashing the new U-Boot binary. Some more links to documentation: - Build-host config: https://tbot.tools/modules/machine_linux.html#builder - UBootBuilder class: https://tbot.tools/modules/tc.html#tbot.tc.uboot.UBootBuilder Hope this helps! -- Harald DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-62 Fax: +49-8142-66989-80 Email: h...@denx.de > Regards, > Simon > > On Wed, 12 Feb 2020 at 22:49, Heiko Schocher wrote: > > Hello Simon, > > > > Am 12.02.2020 um 18:14 schrieb Simon Glass: > > > Hi Heiko, > > > > > > On Wed, 12 Feb 2020 at 01:50, Heiko Schocher wrote: > > > > Hello Simon, > > > > > > > > Am 05.02.2020 um 15:10 schrieb Simon Glass: > > > > > Hi Tom, > > > > > > > > > > On Wed, 4 Dec 2019 at 15:30, Tom Rini wrote: > > > > > > On Fri, Nov 29, 2019 at 09:23:43PM -0700, Simon Glass wrote: > > > > > > > > > > > > > Hi Tom, > > > > > > > > > > > > > > I have been meaning to have a crack at setting up a little > > > > > > > hardware > > > > > > > lab for a while. > > > > > > > > > > > > > > I made some progress recently and hooked up a rpi_3 with sdwire > > > > > > > for > > > > > > > USB/SD, ykush for power and a little computer to control it. It > > > > > > > builds > > > > > > > U-Boot, sticks it on the SD card and runs pytest. > > > > > > > > > > > > > > I pushed a tree here and hopefully you can see the 'hwlab' thing > > > > > > > at the end: > > > > > > > > > > > > > > https://gitlab.denx.de/u-boot/custodians/u-boot-dm/pipelines/148 > > > > > > > > > > > > > > So far it is just running the 'help' test. It seems to hang with > > > > > > > serial console problems if I try to do more. It is not 100% > > > > > > > reliable > > > > > > > yet. I based it on Stephen's test hooks: > > > > > > > > > > > > > > https://github.com/sglass68/uboot-test-hooks > > > > > > > > > > > > > > Is it possible to share this so that others can use the lab when > > > > > > > they > > > > > > > push trees? Is it as simple as adding to the .gitlab-ci.yml file > > > > > > > as I > > > > > > > have done here? > > > > > > > > > > > > > > https://gitlab.denx.de/u-boot/custodians/u-boot-dm/blob/gitlab-working/.gitlab-ci.yml > > > > > > > > > > > > > > I also got tbot going in a similar way, to test booting into > > > > > > > Linux. > > >
Re: [PATCH v2] env: ti: boot: Fix Android boot on AM57x EVM
Hi Lokesh, On Fri, Feb 21, 2020 at 4:35 PM Sam Protsenko wrote: > > When applying DTBO on top of DTB (with "fdt apply" command) on AM57x EVM > board, there is not enough memory reserved in RAM for DTB blob. Hence, > DTBO can't be merged in DTB. It leads to inability to boot Android with > next error message: > > failed on fdt_overlay_apply(): FDT_ERR_NOSPACE > > To overcome that issue let's provide 512 KiB of space to keep DTB and > all merged DTBO blobs. To do so, "length" parameter should be specified > for "fdt addr" command: > > => fdt addr $fdtaddr 0x8 > > 512 KiB is the maximum size we can use for this, because next address > after $fdtaddr is 512 KiB ahead of it: > > fdtaddr=0x8800 > rdaddr=0x8808 > > Also add size variables to 'adtimg' command invocations, to avoid > cluttering the console with DTBO blob sizes. > > Signed-off-by: Sam Protsenko > --- Can you please review and pull this one? Thanks! > Changes in v2: > - Reserve 512 KiB for DTB area, not 1 MiB > > include/environment/ti/boot.h | 8 > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/include/environment/ti/boot.h b/include/environment/ti/boot.h > index 523c8fc4fe..11a57af0a4 100644 > --- a/include/environment/ti/boot.h > +++ b/include/environment/ti/boot.h > @@ -103,18 +103,18 @@ > "echo \" Reading DTB for AM57x EVM RevA3...\"; " \ > "abootimg get dtb --index=0 dtb_start dtb_size; " \ > "cp.b $dtb_start $fdtaddr $dtb_size; " \ > - "fdt addr $fdtaddr; " \ > + "fdt addr $fdtaddr 0x8; " \ > "echo \" Applying DTBOs for AM57x EVM RevA3...\"; " \ > "adtimg addr $dtboaddr; " \ > - "adtimg get dt --index=0 dtbo0_addr; " \ > + "adtimg get dt --index=0 dtbo0_addr dtbo0_size; " \ > "fdt apply $dtbo0_addr; " \ > - "adtimg get dt --index=1 dtbo1_addr; " \ > + "adtimg get dt --index=1 dtbo1_addr dtbo1_size; " \ > "fdt apply $dtbo1_addr; " \ > "elif test $board_name = beagle_x15_revc; then " \ > "echo \" Reading DTB for Beagle X15 RevC...\"; " \ > "abootimg get dtb --index=0 dtb_start dtb_size; " \ > "cp.b $dtb_start $fdtaddr $dtb_size; " \ > - "fdt addr $fdtaddr; " \ > + "fdt addr $fdtaddr 0x8; " \ > "else " \ > "echo Error: Android boot is not supported for $board_name; " > \ > "exit; " \ > -- > 2.24.1 >
Re: U-Boot Logo showing incorrect colors with eLCDIF
Hi Fabio, On Mon, 24 Feb 2020 09:38:04 -0300 Fabio Estevam feste...@gmail.com wrote: > Hi Anatolij, > > On Wed, Feb 5, 2020 at 2:45 PM Fabio Estevam wrote: > > > > Hi Anatolij, > > > > On Wed, Feb 5, 2020 at 2:00 PM Anatolij Gustschin wrote: > > > > > I tried to extend the BMP code to fix this, but my testing with > > > sandbox SDL end of last week has shown incorrect colors in 24bpp > > > mode, and I didn't find the reason for it. I do not see what is > > > wrong in the code, maybe there is some issue with sandbox SDL. > > > So I've submitted some patches [1], [2], [3]. Could you please > > > test them on mx6ul-14x14-evk ? Thanks! > > > > Thanks for the patches. > > > > I can see the logo colors correctly now, but there is some breakage now. > > > > Please see the result at: > > https://ibb.co/0YKwTxJ > > Would you have a fix for this? it seems this is not video driver related, I didn't find a solution for this yet. First I guessed that this could be caused by removed lcd pads init in board code, but this is not the case. I tried to bisect but it is pretty difficult since the older released U-Boot versions do not boot on this board. I didn't have enough time to finish this, sorry. I hope we still can address this before release. -- Anatolij
Re: U-Boot Logo showing incorrect colors with eLCDIF
Hi Anatolij, On Wed, Feb 5, 2020 at 2:45 PM Fabio Estevam wrote: > > Hi Anatolij, > > On Wed, Feb 5, 2020 at 2:00 PM Anatolij Gustschin wrote: > > > I tried to extend the BMP code to fix this, but my testing with > > sandbox SDL end of last week has shown incorrect colors in 24bpp > > mode, and I didn't find the reason for it. I do not see what is > > wrong in the code, maybe there is some issue with sandbox SDL. > > So I've submitted some patches [1], [2], [3]. Could you please > > test them on mx6ul-14x14-evk ? Thanks! > > Thanks for the patches. > > I can see the logo colors correctly now, but there is some breakage now. > > Please see the result at: > https://ibb.co/0YKwTxJ Would you have a fix for this? Thanks
Re: [PATCH] watchdog: Handle timer wrap around
On 24.02.20 01:20, Chris Packham wrote: On some platforms/architectures the value from get_timer() can wrap. This is particularly problematic when long-running code needs to measure a time difference as is the case with watchdog_reset() which tries to avoid tickling the watchdog too frequently. Use time_after() from time.h instead of a plain > comparison to avoid any issues with the time wrapping on a system that has been sitting in u-boot for a long time. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese Thanks, Stefan
RE: [PATCH v1 2/2] cpu: clk: riscv: populate proper CPU core clk frequency
Hello Sean,
> -Original Message-
> From: Sean Anderson
> Sent: Friday, February 21, 2020 11:48 AM
> To: Sagar Kadam ; Bin Meng
>
> Cc: U-Boot Mailing List ; Lukasz Majewski
> ; Anup Patel ; Paul Walmsley (
> Sifive) ; Vincent Chen
>
> Subject: Re: [PATCH v1 2/2] cpu: clk: riscv: populate proper CPU core clk
> frequency
>
> On 2/21/20 12:59 AM, Sagar Kadam wrote:
> >> What you were trying to do in this patch, I believe the following 2
> >> patches already did it.
> >>
> >> http://patchwork.ozlabs.org/patch/1236177/
> >> http://patchwork.ozlabs.org/patch/1236180/
> >>
> >
> > Thanks for sharing the links. Unfortunately I didn’t come across it.
> > I applied these two patches within my repo (assuming there are not
> > extra dependencies) and would like to share my observation:
> > The implementation in the patch links shared here read's clock dt
> > property in clk_get_by_index. If the cpu dt node doesn't contain clock
> > property it return's negative value and so the clk_get_rate here won't be be
> executed.
> >
> > + ret = clk_get_by_index(dev, 0, );
> > + if (!ret) {
> > + ret = clk_get_rate();
>
> This is working as designed. The idea is to use the clocks property if it
> exists
> and to fall back on clock-frequency otherwise.
Thanks for clarifying.
>
> > Thus when I tested this on hifive unleashed the "cpu detail" showed
> frequency as 0 Hz.
>
> This is because the cpu nodes in the hifive/fu540 device tree have neither a
> clock-frequency property or a clocks property.
>
Yes, I will add clocks dt property.
> > Please correct me if I am wrong, but IMHO here we can check for
> > negative return code [if (ret < 0)] instead of (!ret) and if "clocks"
> > is missing in dt property then get the clock driver using
> > uclass_get_device_by_driver->request the clock -> and get clock rate,
> > just like below
> >
> > - if (!ret) {
> > + if (ret < 0) {
> > + ret = uclass_get_device_by_driver(UCLASS_CLK,
> > +
> > DM_GET_DRIVER(sifive_fu540_prci),
> > + );
>
> This is again adding board-specific code to a generic driver. Add a
> UCLASS_CLOCK driver if you want to support clocks. That way there is no
> need for code like this.
Thanks for suggestion.
I will remove board-specific code from generic driver.
>
> > + clk.id = 0;
> > + ret = clk_request(dev, );
> > + if (ret < 0) {
> > + pr_err("%s: request to clock device
> > + failed...\n", __func__);
>
> I belive pr_err is supported for linux compatibility. New code should use
> log_*. This is also probably debug-level and not err-level.
Ok. I will replace pr_err with log_debug.
>
> > + return ret;
> > + }
> > +
> >
> > Also there is missing "include linux/err.h" which is needed by
> > IS_ERR_VALUE
>
> Yes, I noticed that when rebasing. It will be fixed in the next version of the
> series.
Thanks for updating.
BR,
Sagar Kadam
>
> > Please let me know if I can rebase and update my patches above the two
> > patch's you pointed to.
> >
> >> Regards,
> >> Bin
>
> --Sean
RE: [PATCH v1 1/2] fu540: prci: add request and free clock handlers
Hi Sean,
> -Original Message-
> From: Sean Anderson
> Sent: Friday, February 21, 2020 11:53 AM
> To: Sagar Kadam ; u-boot@lists.denx.de
> Cc: lu...@denx.de; bmeng...@gmail.com; anup.pa...@wdc.com; Paul
> Walmsley ( Sifive) ; Vincent Chen
>
> Subject: Re: [PATCH v1 1/2] fu540: prci: add request and free clock handlers
>
> On 2/18/20 11:13 AM, Sagar Shrikant Kadam wrote:
> > +static int sifive_fu540_prci_clk_free(struct clk *clk) {
> > + debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
> > + clk->id);
> > +
> > + if (clk->id >= ARRAY_SIZE(__prci_init_clocks))
> > + return -EINVAL;
> > +
> > + return 0;
> > +}
> > +
>
> I don't think this function is necessary, since no struct clk should be
> passed to
> clk_free except one which was previously successfully requested.
>
Thanks for suggestion.
I can drop this id check and keep the debug message as done in other similar
drivers.
BR,
Sagar Kadam
> > static int sifive_fu540_prci_probe(struct udevice *dev) {
> > int i, err;
> > @@ -611,6 +633,8 @@ static int sifive_fu540_prci_probe(struct udevice
> > *dev) static struct clk_ops sifive_fu540_prci_ops = {
> > .set_rate = sifive_fu540_prci_set_rate,
> > .get_rate = sifive_fu540_prci_get_rate,
> > + .request = sifive_fu540_prci_clk_request,
> > + .rfree= sifive_fu540_prci_clk_free,
> > };
> >
> > static const struct udevice_id sifive_fu540_prci_ids[] = {
> >
>
> --Sean
[PATCH] spi: nxp-fspi: Add 1us delay to make controller ready for next transaction
Board gets reset when performing burst read/write operations. On the other hand, no such behaviour is observed on small size operations. In Linux, readl_poll_timeout API already add delay of 1us which is skipped in U-boot. Since, NXP Flexspi U-boot driver is a ported version of Linux driver and U-boot poll_timeout API lacks delay functionality, add 1us delay so as to make controller ready for other transactions. Signed-off-by: Kuldeep Singh --- drivers/spi/nxp_fspi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/nxp_fspi.c b/drivers/spi/nxp_fspi.c index 0e6c7be..9703642 100644 --- a/drivers/spi/nxp_fspi.c +++ b/drivers/spi/nxp_fspi.c @@ -756,6 +756,7 @@ static int nxp_fspi_exec_op(struct spi_slave *slave, err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0, FSPI_STS0_ARB_IDLE, 1, POLL_TOUT, true); WARN_ON(err); + udelay(1); nxp_fspi_prepare_lut(f, op); /* -- 2.7.4
RE: [PATCH v2 11/21] arm: socfpga: Secure register access for clock manager (SoC 64bits)
Ang, Chee Hong mailto:chee.hong@intel.com>>
schrieb am Sa., 22. Feb. 2020, 06:30:
> From: Chee Hong Ang mailto:chee.hong@intel.com>>
>
> Allow clock manager driver to access the System Manager's Boot Scratch
> Register 0 in non-secure mode (EL2) on SoC 64bits platform.
>
> Signed-off-by: Chee Hong Ang
> mailto:chee.hong@intel.com>>
> ---
> arch/arm/mach-socfpga/clock_manager_agilex.c | 5 +++--
> arch/arm/mach-socfpga/clock_manager_s10.c| 5 +++--
> 2 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c b/arch/arm/mach-
> socfpga/clock_manager_agilex.c
> index 4ee2b7b..e5a0998 100644
> --- a/arch/arm/mach-socfpga/clock_manager_agilex.c
> +++ b/arch/arm/mach-socfpga/clock_manager_agilex.c
> @@ -12,6 +12,7 @@
> #include
> #include
> #include
> +#include
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -65,8 +66,8 @@ unsigned int cm_get_l4_sys_free_clk_hz(void)
>
> u32 cm_get_qspi_controller_clk_hz(void)
> {
> - return readl(socfpga_get_sysmgr_addr() +
> - SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> + return socfpga_secure_reg_read32(socfpga_get_sysmgr_addr() +
> +
> SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> }
>
> void cm_print_clock_quick_summary(void)
> diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-
> socfpga/clock_manager_s10.c
> index 05e4212..02578cc 100644
> --- a/arch/arm/mach-socfpga/clock_manager_s10.c
> +++ b/arch/arm/mach-socfpga/clock_manager_s10.c
> @@ -9,6 +9,7 @@
> #include
> #include
> #include
> +#include
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -385,8 +386,8 @@ unsigned int cm_get_l4_sp_clk_hz(void)
>
> unsigned int cm_get_qspi_controller_clk_hz(void)
> {
> - return readl(socfpga_get_sysmgr_addr() +
> - SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> + return socfpga_secure_reg_read32(socfpga_get_sysmgr_addr() +
> +
> SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> }
>
> unsigned int cm_get_spi_controller_clk_hz(void)
> --
> 2.7.4
>SPL reads the clock info from handoff table (OCRAM) and write
>the clock info into the System Manager's boot scratch register.
>U-Boot proper will read from the System Manager's boot scratch
>register to get the clock info in case the handoff table (OCRAM)
>is no longer available.
>After some investigations, the handoff table in OCRAM should be preserved
>for warm boot. In other words, this handoff table should be left untouched.
>SPL and U-Boot should directly read the clock info from handoff table in OCRAM.
>Therefore, U-Boot proper no longer need to read the clock info from
>System Manager's boot scratch register (secure zone) from non-secure world
>(EL2).
>I don't think that's a good idea: for security reasons, SPL memory should not
>be accessible from EL2 if it is required/used for the next reboot.
>
>Regards,
>Simon
Right. I think I will have to go for proper high-level API in ATF for EL2 to
query the clock frequency:
INTEL_SIP_SMC_CLK_GET_QSPI
I found out System Manager is read only in EL2 and read/write in EL3.
Will drop this patch.
No change required since it only read back from System Manager’s registers.
>So reading these registers is allowed in EL2? I would have expected all access
>is blocked? Is this specified somewhere, or will it be?
>
>Regards,
>Simon
Yes. I know this is confusing.
I would have expected the read access be blocked as well. Unfortunately, this
is not the case.
Let me clarify further:
Here is a list of Stratix10 System Manager’s register map:
https://www.intel.com/content/www/us/en/programmable/hps/stratix-10/hps.html#topic/dwh1505406933720.html
Any R/W registers between ‘siliconid1’ to ‘mpu’ are READ-ONLY in EL2. But are
read/writable in EL3.
If you click into one of these R/W registers:
You will see a notice like this:
Access: RW
Access mode: PRIVILEGEMODE | SECURE
Note: The processor must make a secure, privileged bus access to this register.
It just said this register is read/writable in EL3 but it doesn’t specify it is
read-only in EL2.
I did some tests to read from these registers in EL2. It worked.
It crashed the U-Boot with ‘SError’ exception if I tried to write something
into one of these registers.
For registers after ‘mpu’ which are ‘boot_scratch_cold0’ – ‘boot_scratch_cold9’:
If you click into one of this boot scratch registers:
https://www.intel.com/content/www/us/en/programmable/hps/stratix-10/hps.html#topic/lom1505406925262.html
You don’t see any requirement about the processor need to be in secure mode to
access this register.
Previously I mentioned these registers are read-only in EL2.
They are actually read/writable in EL2 and EL3. Sorry for the misinformation
The clock manager drivers are writing/reading clock settings into these boot
scratch registers
so changes are not necessary for EL2.
In summary, although ‘boot_scratch_cold0’ – ‘boot_scratch_cold9’ registers are
part of
System Manager, but they are not marked as ‘secure zone’.
I missed this when working on this ATF flow
[PATCH v2] arm: imx6: configure NoC on i.MX6DQP
The i.MX6DP and i.MX6QP incorporate NoC interconnect logic
which needs to be configured in order to use external DDR memory.
This patch enables the SPL to configure the necessary registers
in accordance with the NXP engineering bulletin EB828.
Signed-off-by: Bernhard Messerklinger
---
This patch is a revised version of the patch "arm: imx6: configure NoC on
i.MX6DQP" from the original author Filip Brozovic .
It takes care of the review notes for the original patch.
patchwork: https://patchwork.ozlabs.org/patch/670208/
mail-archive: https://lists.denx.de/pipermail/u-boot/2016-September/27.html
I'm not sure how to handle a patch which is based on a patch from another
author. Guidance from the maintainers regarding this question would be welcome.
My assumption would be that this can be solved by adding "Co-Developed-by:" and
"Signed-off-by:" lines to this patch for Filip Brozovic (see [1] for a
discussion of this topic on LKML). Filip, would this be ok for you?
[1] http://lkml.iu.edu/hypermail/linux/kernel/1711.2/00256.html
Changes in v2:
- Added missing link to lkml discussion
arch/arm/include/asm/arch-mx6/mx6-ddr.h | 19 +
arch/arm/mach-imx/mx6/ddr.c | 96 +
2 files changed, 115 insertions(+)
diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
index 19d2f1d9c5..25168c9865 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -307,6 +307,25 @@ struct mx6dq_iomux_grp_regs {
u32 grp_b6ds;
};
+/*
+ * NoC scheduler registers - only on IMX6DQP
+ */
+#define MX6DQP_NOC_SCHED_BASE 0x00bb
+struct mx6dqp_noc_sched_regs {
+ u32 coreid;
+ u32 revid;
+ u32 ddrconf;
+ u32 ddrtiming;
+ u32 ddrmode;
+ u32 rlat;
+ u32 res1[4];
+ u32 ipu1;
+ u32 ipu2;
+ u32 res2[2];
+ u32 activate;
+ u32 res3[16];
+};
+
#define MX6SDL_IOM_DDR_BASE 0x020e0400
struct mx6sdl_iomux_ddr_regs {
u32 res1[25];
diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c
index 6e5e40dd1a..3521d8eac7 100644
--- a/arch/arm/mach-imx/mx6/ddr.c
+++ b/arch/arm/mach-imx/mx6/ddr.c
@@ -936,6 +936,27 @@ void mx6sdl_dram_iocfg(unsigned width,
mmdc1->entry = value; \
} while (0)
+/* see BOOT_CFG3 description Table 5-4. EIM Boot Fusemap */
+#define BOOT_CFG3_DDR_MASK 0x30
+#define BOOT_CFG3_EXT_DDR_MASK 0x33
+
+#define DDR_MMAP_NOC_SINGLE0
+#define DDR_MMAP_NOC_DUAL 0x31
+
+/* NoC ACTIVATE shifts */
+#define NOC_RD_SHIFT 0
+#define NOC_FAW_PERIOD_SHIFT 4
+#define NOC_FAW_BANKS_SHIFT10
+
+/* NoC DdrTiming shifts */
+#define NOC_ACT_TO_ACT_SHIFT 0
+#define NOC_RD_TO_MISS_SHIFT 6
+#define NOC_WR_TO_MISS_SHIFT 12
+#define NOC_BURST_LEN_SHIFT18
+#define NOC_RD_TO_WR_SHIFT 21
+#define NOC_WR_TO_RD_SHIFT 26
+#define NOC_BW_RATIO_SHIFT 31
+
/*
* According JESD209-2B-LPDDR2: Table 103
* WL: write latency
@@ -1225,6 +1246,8 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
{
volatile struct mmdc_p_regs *mmdc0;
volatile struct mmdc_p_regs *mmdc1;
+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+ u8 soc_boot_cfg3 = (readl(_regs->sbmr1) >> 16) & 0xff;
u32 val;
u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
@@ -1517,6 +1540,79 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
/* Step 12: Configure and activate periodic refresh */
mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
+ /*
+* Step 13: i.MX6DQP only: If the NoC scheduler is enabled,
+* configure it and disable MMDC arbitration/reordering (see EB828)
+*/
+ if (is_mx6dqp() &&
+ ((soc_boot_cfg3 & BOOT_CFG3_DDR_MASK) == DDR_MMAP_NOC_SINGLE ||
+ (soc_boot_cfg3 & BOOT_CFG3_EXT_DDR_MASK) == DDR_MMAP_NOC_DUAL)) {
+ struct mx6dqp_noc_sched_regs *noc_sched =
+ (struct mx6dqp_noc_sched_regs *)MX6DQP_NOC_SCHED_BASE;
+
+ /*
+* These values are fixed based on integration parameters and
+* should not be modified
+*/
+ noc_sched->rlat = 0x0040;
+ noc_sched->ipu1 = 0x0020;
+ noc_sched->ipu2 = 0x0020;
+
+ noc_sched->activate = (1 << NOC_FAW_BANKS_SHIFT) |
+ (tfaw << NOC_FAW_PERIOD_SHIFT) |
+ (trrd << NOC_RD_SHIFT);
+ noc_sched->ddrtiming = (((sysinfo->dsize == 1) ? 1 : 0)
+<< NOC_BW_RATIO_SHIFT) |
+ ((tcwl + twtr) << NOC_WR_TO_RD_SHIFT) |
+ ((tcl - tcwl + 2) << NOC_RD_TO_WR_SHIFT)
|
+
[PATCH] arm: imx6: configure NoC on i.MX6DQP
The i.MX6DP and i.MX6QP incorporate NoC interconnect logic
which needs to be configured in order to use external DDR memory.
This patch enables the SPL to configure the necessary registers
in accordance with the NXP engineering bulletin EB828.
Signed-off-by: Bernhard Messerklinger
---
This patch is a revised version of the patch "arm: imx6: configure NoC on
i.MX6DQP" from the original author Filip Brozovic .
It takes care of the review notes for the original patch.
patchwork: https://patchwork.ozlabs.org/patch/670208/
mail-archive: https://lists.denx.de/pipermail/u-boot/2016-September/27.html
I'm not sure how to handle a patch which is based on a patch from another
author. Guidance from the maintainers regarding this question would be welcome.
My assumption would be that this can be solved by adding "Co-Developed-by:" and
"Signed-off-by:" lines to this patch for Filip Brozovic (see [1] for a
discussion of this topic on LKML). Filip, would this be ok for you?
arch/arm/include/asm/arch-mx6/mx6-ddr.h | 19 +
arch/arm/mach-imx/mx6/ddr.c | 96 +
2 files changed, 115 insertions(+)
diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
index 19d2f1d9c5..25168c9865 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -307,6 +307,25 @@ struct mx6dq_iomux_grp_regs {
u32 grp_b6ds;
};
+/*
+ * NoC scheduler registers - only on IMX6DQP
+ */
+#define MX6DQP_NOC_SCHED_BASE 0x00bb
+struct mx6dqp_noc_sched_regs {
+ u32 coreid;
+ u32 revid;
+ u32 ddrconf;
+ u32 ddrtiming;
+ u32 ddrmode;
+ u32 rlat;
+ u32 res1[4];
+ u32 ipu1;
+ u32 ipu2;
+ u32 res2[2];
+ u32 activate;
+ u32 res3[16];
+};
+
#define MX6SDL_IOM_DDR_BASE 0x020e0400
struct mx6sdl_iomux_ddr_regs {
u32 res1[25];
diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c
index 6e5e40dd1a..3521d8eac7 100644
--- a/arch/arm/mach-imx/mx6/ddr.c
+++ b/arch/arm/mach-imx/mx6/ddr.c
@@ -936,6 +936,27 @@ void mx6sdl_dram_iocfg(unsigned width,
mmdc1->entry = value; \
} while (0)
+/* see BOOT_CFG3 description Table 5-4. EIM Boot Fusemap */
+#define BOOT_CFG3_DDR_MASK 0x30
+#define BOOT_CFG3_EXT_DDR_MASK 0x33
+
+#define DDR_MMAP_NOC_SINGLE0
+#define DDR_MMAP_NOC_DUAL 0x31
+
+/* NoC ACTIVATE shifts */
+#define NOC_RD_SHIFT 0
+#define NOC_FAW_PERIOD_SHIFT 4
+#define NOC_FAW_BANKS_SHIFT10
+
+/* NoC DdrTiming shifts */
+#define NOC_ACT_TO_ACT_SHIFT 0
+#define NOC_RD_TO_MISS_SHIFT 6
+#define NOC_WR_TO_MISS_SHIFT 12
+#define NOC_BURST_LEN_SHIFT18
+#define NOC_RD_TO_WR_SHIFT 21
+#define NOC_WR_TO_RD_SHIFT 26
+#define NOC_BW_RATIO_SHIFT 31
+
/*
* According JESD209-2B-LPDDR2: Table 103
* WL: write latency
@@ -1225,6 +1246,8 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
{
volatile struct mmdc_p_regs *mmdc0;
volatile struct mmdc_p_regs *mmdc1;
+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+ u8 soc_boot_cfg3 = (readl(_regs->sbmr1) >> 16) & 0xff;
u32 val;
u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
@@ -1517,6 +1540,79 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
/* Step 12: Configure and activate periodic refresh */
mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
+ /*
+* Step 13: i.MX6DQP only: If the NoC scheduler is enabled,
+* configure it and disable MMDC arbitration/reordering (see EB828)
+*/
+ if (is_mx6dqp() &&
+ ((soc_boot_cfg3 & BOOT_CFG3_DDR_MASK) == DDR_MMAP_NOC_SINGLE ||
+ (soc_boot_cfg3 & BOOT_CFG3_EXT_DDR_MASK) == DDR_MMAP_NOC_DUAL)) {
+ struct mx6dqp_noc_sched_regs *noc_sched =
+ (struct mx6dqp_noc_sched_regs *)MX6DQP_NOC_SCHED_BASE;
+
+ /*
+* These values are fixed based on integration parameters and
+* should not be modified
+*/
+ noc_sched->rlat = 0x0040;
+ noc_sched->ipu1 = 0x0020;
+ noc_sched->ipu2 = 0x0020;
+
+ noc_sched->activate = (1 << NOC_FAW_BANKS_SHIFT) |
+ (tfaw << NOC_FAW_PERIOD_SHIFT) |
+ (trrd << NOC_RD_SHIFT);
+ noc_sched->ddrtiming = (((sysinfo->dsize == 1) ? 1 : 0)
+<< NOC_BW_RATIO_SHIFT) |
+ ((tcwl + twtr) << NOC_WR_TO_RD_SHIFT) |
+ ((tcl - tcwl + 2) << NOC_RD_TO_WR_SHIFT)
|
+ (4 << NOC_BURST_LEN_SHIFT) | /* BL8 */
+ ((tcwl +
Re: [PATCH v2 11/21] arm: socfpga: Secure register access for clock manager (SoC 64bits)
Ang, Chee Hong schrieb am Mo., 24. Feb. 2020,
10:12:
>
>
>
>
> *From:* Ang, Chee Hong
> *Sent:* Saturday, February 22, 2020 6:00 PM
> *To:* Simon Goldschmidt
> *Cc:* U-Boot Mailing List ; Marek Vasut <
> ma...@denx.de>; See, Chin Liang ; Tan, Ley Foon
> ; Westergreen, Dalon ;
> Gong, Richard
> *Subject:* RE: [PATCH v2 11/21] arm: socfpga: Secure register access for
> clock manager (SoC 64bits)
>
>
>
> Ang, Chee Hong schrieb am Sa., 22. Feb. 2020,
> 06:30:
>
> > From: Chee Hong Ang
> >
> > Allow clock manager driver to access the System Manager's Boot Scratch
> > Register 0 in non-secure mode (EL2) on SoC 64bits platform.
> >
> > Signed-off-by: Chee Hong Ang
> > ---
> > arch/arm/mach-socfpga/clock_manager_agilex.c | 5 +++--
> > arch/arm/mach-socfpga/clock_manager_s10.c| 5 +++--
> > 2 files changed, 6 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c
> b/arch/arm/mach-
> > socfpga/clock_manager_agilex.c
> > index 4ee2b7b..e5a0998 100644
> > --- a/arch/arm/mach-socfpga/clock_manager_agilex.c
> > +++ b/arch/arm/mach-socfpga/clock_manager_agilex.c
> > @@ -12,6 +12,7 @@
> > #include
> > #include
> > #include
> > +#include
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > @@ -65,8 +66,8 @@ unsigned int cm_get_l4_sys_free_clk_hz(void)
> >
> > u32 cm_get_qspi_controller_clk_hz(void)
> > {
> > - return readl(socfpga_get_sysmgr_addr() +
> > - SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> > + return socfpga_secure_reg_read32(socfpga_get_sysmgr_addr() +
> > +
> > SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> > }
> >
> > void cm_print_clock_quick_summary(void)
> > diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-
> > socfpga/clock_manager_s10.c
> > index 05e4212..02578cc 100644
> > --- a/arch/arm/mach-socfpga/clock_manager_s10.c
> > +++ b/arch/arm/mach-socfpga/clock_manager_s10.c
> > @@ -9,6 +9,7 @@
> > #include
> > #include
> > #include
> > +#include
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > @@ -385,8 +386,8 @@ unsigned int cm_get_l4_sp_clk_hz(void)
> >
> > unsigned int cm_get_qspi_controller_clk_hz(void)
> > {
> > - return readl(socfpga_get_sysmgr_addr() +
> > - SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> > + return socfpga_secure_reg_read32(socfpga_get_sysmgr_addr() +
> > +
> > SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> > }
> >
> > unsigned int cm_get_spi_controller_clk_hz(void)
> > --
> > 2.7.4
> >SPL reads the clock info from handoff table (OCRAM) and write
> >the clock info into the System Manager's boot scratch register.
> >U-Boot proper will read from the System Manager's boot scratch
> >register to get the clock info in case the handoff table (OCRAM)
> >is no longer available.
> >After some investigations, the handoff table in OCRAM should be preserved
> >for warm boot. In other words, this handoff table should be left
> untouched.
> >SPL and U-Boot should directly read the clock info from handoff table in
> OCRAM.
> >Therefore, U-Boot proper no longer need to read the clock info from
> >System Manager's boot scratch register (secure zone) from non-secure
> world (EL2).
>
>
>
> >I don't think that's a good idea: for security reasons, SPL memory should
> not be accessible from EL2 if it is required/used for the next reboot.
>
> >
>
> >Regards,
>
> >Simon
>
> Right. I think I will have to go for proper high-level API in ATF for EL2
> to query the clock frequency:
>
> INTEL_SIP_SMC_CLK_GET_QSPI
>
>
>
> I found out System Manager is read only in EL2 and read/write in EL3.
>
> Will drop this patch.
>
> No change required since it only read back from System Manager’s registers.
>
So reading these registers is allowed in EL2? I would have expected all
access is blocked? Is this specified somewhere, or will it be?
Regards,
Simon
>
RE: [PATCH v2 13/21] arm: socfpga: Secure register access for reading PLL frequency
> > > On 2/22/20 11:05 AM, Ang, Chee Hong wrote:
> > > >>> From: Chee Hong Ang
> > > >>>
> > > >>> Allow reading external oscillator and FPGA clock's frequency
> > > >>> from System Manager's Boot Scratch Register 1 and Boot Scratch
> > > >>> Register
> > > >>> 2 in non-secure mode (EL2) on SoC 64bits platform.
> > > >>>
> > > >>> Signed-off-by: Chee Hong Ang
> > > >>> ---
> > > >>> arch/arm/mach-socfpga/wrap_pll_config_s10.c | 9 +
> > > >>> 1 file changed, 5 insertions(+), 4 deletions(-)
> > > >>>
> > > >>> diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c
> > > >>> b/arch/arm/mach- socfpga/wrap_pll_config_s10.c index
> > > >>> 3da8579..7bd92d0
> > > >>> 100644
> > > >>> --- a/arch/arm/mach-socfpga/wrap_pll_config_s10.c
> > > >>> +++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
> > > >>> @@ -9,6 +9,7 @@
> > > >>> #include
> > > >>> #include #include
> > > >>>
> > > >>> +#include
> > > >>>
> > > >>> const struct cm_config * const cm_get_default_config(void) {
> > > >>> @@
> > > >>> -39,8 +40,8 @@ const unsigned int cm_get_osc_clk_hz(void)
> > > >>> writel(clock,
> > > >>> socfpga_get_sysmgr_addr() +
> > > >>> SYSMGR_SOC64_BOOT_SCRATCH_COLD1); #endif
> > > >>> - return readl(socfpga_get_sysmgr_addr() +
> > > >>> - SYSMGR_SOC64_BOOT_SCRATCH_COLD1);
> > > >>> + return socfpga_secure_reg_read32(socfpga_get_sysmgr_addr()
> +
> > > >>> +
> > > >>> SYSMGR_SOC64_BOOT_SCRATCH_COLD1); }
> > > >>>
> > > >>> const unsigned int cm_get_intosc_clk_hz(void) @@ -56,6 +57,6 @@
> > > >>> const unsigned int cm_get_fpga_clk_hz(void)
> > > >>> writel(clock,
> > > >>> socfpga_get_sysmgr_addr() +
> > > >>> SYSMGR_SOC64_BOOT_SCRATCH_COLD2); #endif
> > > >>> - return readl(socfpga_get_sysmgr_addr() +
> > > >>> - SYSMGR_SOC64_BOOT_SCRATCH_COLD2);
> > > >>> + return socfpga_secure_reg_read32(socfpga_get_sysmgr_addr()
> +
> > > >>> +
> > > >>> SYSMGR_SOC64_BOOT_SCRATCH_COLD2); }
> > > >>> --
> > > >>> 2.7.4
> > > >> This clock info could be directly read from the handoff table
> > > >> (OCRAM) instead of the System Manager's boot scratch register
> > > >> (secure
> > zone).
> > > >> Please refer to my full explanation in my previous email reply:
> > > >> [PATCH v2 11/21] arm: socfpga: Secure register access for clock
> > > >> manager (SoC
> > > >> 64bits)
> > > > Simon raised a good security concern on this approach. I will drop
> > > > this
> > > approach.
> > > > Will go for high-level APIs in ATF for clock queries:
> > > > INTEL_SIP_SMC_CLK_GET_OSC
> > > > INTEL_SIP_SMC_CLK_GET_FPGA
> > >
> > > Can't you have a clock driver read out the clock tree once and then
> > > have all the drivers in U-Boot just get clock settings from the clock
> > > driver?
> In 'wrap_pll_config_s10.c':
> cm_get_osc_clk_hz()
> cm_get_intosc_clk_hz()
> cm_get_fpga_clk_hz()
>
> All the clock settings returned by S10/Agilex clock manager drivers derived
> from
> these 3 clock sources (listed above) then all other U-Boot drivers get the
> clock
> settings from the clock driver.
>
> Can you help clarify what do you mean by "read out the clock tree once" ?
>
> Anyway, there will be only one high-level API for reading the OSC/FPGA/QSPI
> clock sources depending on which clock source chosen by caller.
>
> Please ignore my reply below.
> > Yes. This could be part of the clock driver (clock_manager_s10 /
> > agilex.c) instead of scattering around in different places.
Please ignore all my replies above. Will drop this patch.
System Manager is read only in EL2 and read/write in EL3.
No change required since it only read back from System Manager’s registers.
RE: [PATCH v2 11/21] arm: socfpga: Secure register access for clock manager (SoC 64bits)
From: Ang, Chee Hong
Sent: Saturday, February 22, 2020 6:00 PM
To: Simon Goldschmidt
Cc: U-Boot Mailing List ; Marek Vasut ;
See, Chin Liang ; Tan, Ley Foon
; Westergreen, Dalon ;
Gong, Richard
Subject: RE: [PATCH v2 11/21] arm: socfpga: Secure register access for clock
manager (SoC 64bits)
Ang, Chee Hong mailto:chee.hong@intel.com>>
schrieb am Sa., 22. Feb. 2020, 06:30:
> From: Chee Hong Ang mailto:chee.hong@intel.com>>
>
> Allow clock manager driver to access the System Manager's Boot Scratch
> Register 0 in non-secure mode (EL2) on SoC 64bits platform.
>
> Signed-off-by: Chee Hong Ang
> mailto:chee.hong@intel.com>>
> ---
> arch/arm/mach-socfpga/clock_manager_agilex.c | 5 +++--
> arch/arm/mach-socfpga/clock_manager_s10.c| 5 +++--
> 2 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c b/arch/arm/mach-
> socfpga/clock_manager_agilex.c
> index 4ee2b7b..e5a0998 100644
> --- a/arch/arm/mach-socfpga/clock_manager_agilex.c
> +++ b/arch/arm/mach-socfpga/clock_manager_agilex.c
> @@ -12,6 +12,7 @@
> #include
> #include
> #include
> +#include
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -65,8 +66,8 @@ unsigned int cm_get_l4_sys_free_clk_hz(void)
>
> u32 cm_get_qspi_controller_clk_hz(void)
> {
> - return readl(socfpga_get_sysmgr_addr() +
> - SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> + return socfpga_secure_reg_read32(socfpga_get_sysmgr_addr() +
> +
> SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> }
>
> void cm_print_clock_quick_summary(void)
> diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-
> socfpga/clock_manager_s10.c
> index 05e4212..02578cc 100644
> --- a/arch/arm/mach-socfpga/clock_manager_s10.c
> +++ b/arch/arm/mach-socfpga/clock_manager_s10.c
> @@ -9,6 +9,7 @@
> #include
> #include
> #include
> +#include
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -385,8 +386,8 @@ unsigned int cm_get_l4_sp_clk_hz(void)
>
> unsigned int cm_get_qspi_controller_clk_hz(void)
> {
> - return readl(socfpga_get_sysmgr_addr() +
> - SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> + return socfpga_secure_reg_read32(socfpga_get_sysmgr_addr() +
> +
> SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> }
>
> unsigned int cm_get_spi_controller_clk_hz(void)
> --
> 2.7.4
>SPL reads the clock info from handoff table (OCRAM) and write
>the clock info into the System Manager's boot scratch register.
>U-Boot proper will read from the System Manager's boot scratch
>register to get the clock info in case the handoff table (OCRAM)
>is no longer available.
>After some investigations, the handoff table in OCRAM should be preserved
>for warm boot. In other words, this handoff table should be left untouched.
>SPL and U-Boot should directly read the clock info from handoff table in OCRAM.
>Therefore, U-Boot proper no longer need to read the clock info from
>System Manager's boot scratch register (secure zone) from non-secure world
>(EL2).
>I don't think that's a good idea: for security reasons, SPL memory should not
>be accessible from EL2 if it is required/used for the next reboot.
>
>Regards,
>Simon
Right. I think I will have to go for proper high-level API in ATF for EL2 to
query the clock frequency:
INTEL_SIP_SMC_CLK_GET_QSPI
I found out System Manager is read only in EL2 and read/write in EL3.
Will drop this patch.
No change required since it only read back from System Manager’s registers.
[PATCH v4 14/14] doc: update FU540 RISC-V documentation
Add descriptions about U-Boot SPL feature and how to build and run. Signed-off-by: Pragnesh Patel --- doc/board/sifive/fu540.rst | 409 ++--- 1 file changed, 385 insertions(+), 24 deletions(-) diff --git a/doc/board/sifive/fu540.rst b/doc/board/sifive/fu540.rst index 3937222c6c..e5414f4eef 100644 --- a/doc/board/sifive/fu540.rst +++ b/doc/board/sifive/fu540.rst @@ -42,8 +42,60 @@ Building export ARCH=riscv export CROSS_COMPILE= -3. make sifive_fu540_defconfig -4. make +User can use FSBL or u-boot-spl as a 1st stage bootloader. + +1) Use FSBL as a 1st stage bootloader + +.. code-block:: console + + git clone https://github.com/sifive/freedom-u540-c000-bootloader.git + cd freedom-u540-c000-bootloader + make + + cd + make sifive_fu540_defconfig + make + + git clone https://github.com/riscv/opensbi.git + cd opensbi + make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH= + +This will generate a fw_payload.bin(build/platform/sifive/fu540/firmware/fw_payload.bin) + +u-boot.bin is used as a payload of the OpenSBI FW_PAYLOAD firmware. + +More detailed description of steps required to build FW_PAYLOAD firmware +is beyond the scope of this document. Please refer OpenSBI documenation. +(Note: OpenSBI git repo is at https://github.com/riscv/opensbi.git) + +2) Use u-boot-spl as a 1st stage bootloader + +Before building U-Boot SPL, OpenSBI must be build first. OpenSBI can be +cloned and build for FU540 as below: + +.. code-block:: console + + git clone https://github.com/riscv/opensbi.git + cd opensbi + make PLATFORM=sifive/fu540 + +Copy OpenSBI FW_DYNAMIC image (build/platform/sifive/fu540/firmware/fw_dynamic.bin) +into U-Boot root directory + +.. code-block:: console + + cp build/platform/sifive/fu540/firmware/fw_dynamic.bin + +Now build the u-boot-spl and u-boot proper + +.. code-block:: console + + cd + make sifive_fu540_defconfig + make + +This will generate spl/u-boot-spl.bin and FIT image(u-boot.itb) + Flashing @@ -53,28 +105,55 @@ The current U-Boot port is supported in S-mode only and loaded from DRAM. A prior stage M-mode firmware/bootloader (e.g OpenSBI) is required to boot the u-boot.bin in S-mode and provide M-mode runtime services. -Currently, the u-boot.bin is used as a payload of the OpenSBI FW_PAYLOAD -firmware. We need to compile OpenSBI with below command: +1) Use FSBL as a 1st stage bootloader + +ZSBL loads the FSBL(fsbl.bin) from a partition with GUID type +5B193300-FC78-40CD-8002-E86C45580B47 + +FSBL loads the fw_payload.bin from a partition with GUID type +2E54B353-1271-4842-806F-E436D6AF6985 + +Once the prior stage firmware/bootloader binary is generated, it should be +copied to the first partition of the sdcard. .. code-block:: none -make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH= + sudo dd if=fsbl.bin of=/dev/disk2s4 bs=1024 + sudo dd if=fw_payload.bin of=/dev/disk2s1 bs=1024 -More detailed description of steps required to build FW_PAYLOAD firmware -is beyond the scope of this document. Please refer OpenSBI documenation. -(Note: OpenSBI git repo is at https://github.com/riscv/opensbi.git) +Assuming that /dev/disk2s4 partition is of GUID type +5B193300-FC78-40CD-8002-E86C45580B47 and /dev/disk2s1 partition +is of GUID type 2E54B353-1271-4842-806F-E436D6AF6985 + +2) Use u-boot-spl as a 1st stage bootloader + +ZSBL loads the U-boot SPL(u-boot-spl.bin) from a partition with GUID type +5B193300-FC78-40CD-8002-E86C45580B47 + +U-boot SPL expects a u-boot FIT image(u-boot.itb) from 1st partition(/dev/sdc1) +of SD card irrespective of GUID + +FIT image(u-boot.itb) is a combination of fw_dynamic.bin, u-boot-nodtb.bin and +device tree blob(hifive-unleashed-a00.dtb) Once the prior stage firmware/bootloader binary is generated, it should be copied to the first partition of the sdcard. .. code-block:: none -sudo dd if= of=/dev/disk2s1 bs=1024 +sudo dd if=spl/u-boot-spl.bin of=/dev/disk2s4 bs=1024 +sudo dd if=u-boot.itb of=/dev/disk2s1 bs=1024 + +Assuming that /dev/disk2s4 partition is of GUID type +5B193300-FC78-40CD-8002-E86C45580B47 and /dev/disk2s1 is of +any GUID type raw partition. Booting --- Once you plugin the sdcard and power up, you should see the U-Boot prompt. +1) Use FSBL as a 1st stage bootloader + Sample boot log from HiFive Unleashed board --- @@ -145,19 +224,6 @@ load uImage. Filename '/sifive/fu540/Image'. Load address: 0x8400 Loading: # -# -# -# -# -
[PATCH v4 13/14] sifive: fix palmer's email address
Fix Palmer's email address Signed-off-by: Pragnesh Patel --- board/sifive/fu540/MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/sifive/fu540/MAINTAINERS b/board/sifive/fu540/MAINTAINERS index 702d803ad8..9bae3d3db7 100644 --- a/board/sifive/fu540/MAINTAINERS +++ b/board/sifive/fu540/MAINTAINERS @@ -1,6 +1,6 @@ SiFive FU540 BOARD M: Paul Walmsley -M: Palmer Dabbelt +M: Palmer Dabbelt M: Anup Patel M: Atish Patra S: Maintained -- 2.17.1
[PATCH v4 12/14] riscv: sifive: fu540: enable all cache ways from u-boot proper
Enable all cache ways from u-boot proper.
Signed-off-by: Pragnesh Patel
---
board/sifive/fu540/Makefile | 1 +
board/sifive/fu540/cache.c | 20
board/sifive/fu540/cache.h | 13 +
board/sifive/fu540/fu540.c | 6 --
4 files changed, 38 insertions(+), 2 deletions(-)
create mode 100644 board/sifive/fu540/cache.c
create mode 100644 board/sifive/fu540/cache.h
diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile
index b05e2f5807..3b867bbd89 100644
--- a/board/sifive/fu540/Makefile
+++ b/board/sifive/fu540/Makefile
@@ -3,6 +3,7 @@
# Copyright (c) 2019 Western Digital Corporation or its affiliates.
obj-y += fu540.o
+obj-y += cache.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
diff --git a/board/sifive/fu540/cache.c b/board/sifive/fu540/cache.c
new file mode 100644
index 00..a0bcd2ba48
--- /dev/null
+++ b/board/sifive/fu540/cache.c
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 SiFive, Inc
+ */
+#include
+
+/* Register offsets */
+#define CACHE_ENABLE 0x008
+
+/* Enable ways; allow cache to use these ways */
+void cache_enable_ways(u64 base_addr, u8 value)
+{
+ volatile u32 *enable = (volatile u32 *)(base_addr +
+ CACHE_ENABLE);
+ /* memory barrier */
+ mb();
+ (*enable) = value;
+ /* memory barrier */
+ mb();
+}
diff --git a/board/sifive/fu540/cache.h b/board/sifive/fu540/cache.h
new file mode 100644
index 00..425124a23b
--- /dev/null
+++ b/board/sifive/fu540/cache.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2019 SiFive, Inc
+ */
+
+#ifndef FU540_CACHE_H
+#define FU540_CACHE_H
+
+#define CACHE_CTRL_ADDR _AC(0x201, UL)
+
+void cache_enable_ways(u64 base_addr, u8 value);
+
+#endif /* FU540_CACHE_H */
diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
index fba9469c2d..661b2ad282 100644
--- a/board/sifive/fu540/fu540.c
+++ b/board/sifive/fu540/fu540.c
@@ -13,6 +13,8 @@
#include
#include
+#include "cache.h"
+
/*
* This define is a value used for error/unknown serial.
* If we really care about distinguishing errors and 0 is
@@ -111,8 +113,8 @@ int misc_init_r(void)
int board_init(void)
{
- /* For now nothing to do here. */
-
+ /* enable all cache ways */
+ cache_enable_ways(CACHE_CTRL_ADDR, 15);
return 0;
}
--
2.17.1
[PATCH v4 07/14] sifive: dts: fu540: Add DDR controller and phy register settings
Add DDR controller and phy register settings, taken from fsbl
(https://github.com/sifive/freedom-u540-c000-bootloader.git)
Signed-off-by: Pragnesh Patel
---
arch/riscv/dts/fu540-c000-u-boot.dtsi |7 +
arch/riscv/dts/fu540-sdram-lpddr4.dtsi| 1489 +
.../dts/hifive-unleashed-a00-u-boot.dtsi |1 +
3 files changed, 1497 insertions(+)
create mode 100644 arch/riscv/dts/fu540-sdram-lpddr4.dtsi
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi
b/arch/riscv/dts/fu540-c000-u-boot.dtsi
index 2d3d62801f..b8cef67885 100644
--- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -40,6 +40,13 @@
reg = <0x0 0x200 0x0 0xc>;
u-boot,dm-spl;
};
+ dmc: dmc@100b {
+ compatible = "sifive,fu540-ddr";
+ reg = <0x0 0x100b 0x0 0x0800
+ 0x0 0x100b2000 0x0 0x2000
+ 0x0 0x100b8000 0x0 0x0fff>;
+ u-boot,dm-spl;
+ };
};
};
diff --git a/arch/riscv/dts/fu540-sdram-lpddr4.dtsi
b/arch/riscv/dts/fu540-sdram-lpddr4.dtsi
new file mode 100644
index 00..370c53800d
--- /dev/null
+++ b/arch/riscv/dts/fu540-sdram-lpddr4.dtsi
@@ -0,0 +1,1489 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2020 SiFive, Inc
+ */
+
+ {
+ sifive,sdram-params = <
+ 0x0a00 /* DENALI_CTL_00_DATA */
+ 0x /* DENALI_CTL_01_DATA */
+ 0x /* DENALI_CTL_02_DATA */
+ 0x /* DENALI_CTL_03_DATA */
+ 0x /* DENALI_CTL_04_DATA */
+ 0x /* DENALI_CTL_05_DATA */
+ 0x000a /* DENALI_CTL_06_DATA */
+ 0x0002d362 /* DENALI_CTL_07_DATA */
+ 0x00071073 /* DENALI_CTL_08_DATA */
+ 0x0a1c0255 /* DENALI_CTL_09_DATA */
+ 0x1c1c0400 /* DENALI_CTL_10_DATA */
+ 0x0404990b /* DENALI_CTL_11_DATA */
+ 0x2b050405 /* DENALI_CTL_12_DATA */
+ 0x0e0c081e /* DENALI_CTL_13_DATA */
+ 0x08090914 /* DENALI_CTL_14_DATA */
+ 0x00fde718 /* DENALI_CTL_15_DATA */
+ 0x00180a05 /* DENALI_CTL_16_DATA */
+ 0x008b130e /* DENALI_CTL_17_DATA */
+ 0x01000118 /* DENALI_CTL_18_DATA */
+ 0x0e032101 /* DENALI_CTL_19_DATA */
+ 0x /* DENALI_CTL_20_DATA */
+ 0x0101 /* DENALI_CTL_21_DATA */
+ 0x /* DENALI_CTL_22_DATA */
+ 0x0a00 /* DENALI_CTL_23_DATA */
+ 0x /* DENALI_CTL_24_DATA */
+ 0x01450100 /* DENALI_CTL_25_DATA */
+ 0x1c36 /* DENALI_CTL_26_DATA */
+ 0x0005 /* DENALI_CTL_27_DATA */
+ 0x00170006 /* DENALI_CTL_28_DATA */
+ 0x014e0300 /* DENALI_CTL_29_DATA */
+ 0x0301 /* DENALI_CTL_30_DATA */
+ 0x000a0e00 /* DENALI_CTL_31_DATA */
+ 0x04030200 /* DENALI_CTL_32_DATA */
+ 0x031f /* DENALI_CTL_33_DATA */
+ 0x00070004 /* DENALI_CTL_34_DATA */
+ 0x /* DENALI_CTL_35_DATA */
+ 0x /* DENALI_CTL_36_DATA */
+ 0x /* DENALI_CTL_37_DATA */
+ 0x /* DENALI_CTL_38_DATA */
+ 0x /* DENALI_CTL_39_DATA */
+ 0x /* DENALI_CTL_40_DATA */
+ 0x /* DENALI_CTL_41_DATA */
+ 0x /* DENALI_CTL_42_DATA */
+ 0x /* DENALI_CTL_43_DATA */
+ 0x /* DENALI_CTL_44_DATA */
+ 0x /* DENALI_CTL_45_DATA */
+ 0x /* DENALI_CTL_46_DATA */
+ 0x /* DENALI_CTL_47_DATA */
+ 0x /* DENALI_CTL_48_DATA */
+ 0x /* DENALI_CTL_49_DATA */
+ 0x /* DENALI_CTL_50_DATA */
+ 0x /* DENALI_CTL_51_DATA */
+ 0x /* DENALI_CTL_52_DATA */
+ 0x /* DENALI_CTL_53_DATA */
+ 0x /* DENALI_CTL_54_DATA */
+ 0x /* DENALI_CTL_55_DATA */
+ 0x /* DENALI_CTL_56_DATA */
+ 0x /* DENALI_CTL_57_DATA */
+ 0x /* DENALI_CTL_58_DATA */
+ 0x /* DENALI_CTL_59_DATA */
+ 0x0424 /* DENALI_CTL_60_DATA */
+ 0x0201 /*
[PATCH v4 09/14] clk: sifive: fu540-prci: Add clock initialization for SPL
Set corepll, ddrpll and ethernet PLL for u-boot-spl
Signed-off-by: Pragnesh Patel
---
drivers/clk/sifive/fu540-prci.c | 94 +
1 file changed, 94 insertions(+)
diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
index c02c0466a8..f043b0eccb 100644
--- a/drivers/clk/sifive/fu540-prci.c
+++ b/drivers/clk/sifive/fu540-prci.c
@@ -41,6 +41,10 @@
#include
#include
+#define DDRCTLPLL_F55
+#define DDRCTLPLL_Q2
+#define MHz100
+
/*
* EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects:
* hfclk and rtcclk
@@ -152,6 +156,27 @@
#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \
(0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT)
+/* PROCMONCFG */
+#define PRCI_PROCMONCFG_OFFSET 0xF0
+#define PRCI_PROCMONCFG_CORE_CLOCK_SHIFT 24
+#define PRCI_PROCMONCFG_CORE_CLOCK_MASK \
+ (0x1 << PRCI_PROCMONCFG_CORE_CLOCK_SHIFT)
+
+#define PLL_R(x) \
+ ((x) << PRCI_DDRPLLCFG0_DIVR_SHIFT) & PRCI_DDRPLLCFG0_DIVR_MASK
+#define PLL_F(x) \
+ ((x) << PRCI_DDRPLLCFG0_DIVF_SHIFT) & PRCI_DDRPLLCFG0_DIVF_MASK
+#define PLL_Q(x) \
+ ((x) << PRCI_DDRPLLCFG0_DIVQ_SHIFT) & PRCI_DDRPLLCFG0_DIVQ_MASK
+#define PLL_RANGE(x) \
+ ((x) << PRCI_DDRPLLCFG0_RANGE_SHIFT) & PRCI_DDRPLLCFG0_RANGE_MASK
+#define PLL_BYPASS(x) \
+ ((x) << PRCI_DDRPLLCFG0_BYPASS_SHIFT) & PRCI_DDRPLLCFG0_BYPASS_MASK
+#define PLL_FSE(x) \
+ ((x) << PRCI_DDRPLLCFG0_FSE_SHIFT) & PRCI_DDRPLLCFG0_FSE_MASK
+#define PLL_LOCK(x) \
+ ((x) << PRCI_DDRPLLCFG0_LOCK_SHIFT) & PRCI_DDRPLLCFG0_LOCK_MASK
+
/*
* Private structures
*/
@@ -672,6 +697,75 @@ static int sifive_fu540_prci_probe(struct udevice *dev)
__prci_wrpll_read_cfg(pd, pc->pwd);
}
+#ifdef CONFIG_SPL_BUILD
+ u32 v;
+ struct clk clock;
+
+ v = __prci_readl(pd, PRCI_CLKMUXSTATUSREG_OFFSET);
+ v &= PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK;
+
+ clock.id = PRCI_CLK_COREPLL;
+
+ if (v) {
+ /* corepll 500 Mhz */
+ sifive_fu540_prci_set_rate(, 500UL * MHz);
+ } else {
+ /* corepll 1 Ghz */
+ sifive_fu540_prci_set_rate(, 1000UL * MHz);
+ }
+
+ sifive_fu540_prci_clock_enable(&__prci_init_clocks[clock.id], 1);
+
+ //DDR init
+ u32 ddrctlmhz =
+ (PLL_R(0)) |
+ (PLL_F(DDRCTLPLL_F)) |
+ (PLL_Q(DDRCTLPLL_Q)) |
+ (PLL_RANGE(0x4)) |
+ (PLL_BYPASS(0)) |
+ (PLL_FSE(1));
+ __prci_writel(ddrctlmhz, PRCI_DDRPLLCFG0_OFFSET, pd);
+
+ clock.id = PRCI_CLK_DDRPLL;
+ sifive_fu540_prci_clock_enable(&__prci_init_clocks[clock.id], 1);
+
+ /* Release DDR reset */
+ v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET);
+ v |= PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK;
+ __prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd);
+
+ // HACK to get the '1 full controller clock cycle'.
+ asm volatile ("fence");
+ v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET);
+ v |= (PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK |
+ PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK |
+ PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK);
+ __prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd);
+ // HACK to get the '1 full controller clock cycle'.
+ asm volatile ("fence");
+
+ /* These take like 16 cycles to actually propagate. We can't go sending
+* stuff before they come out of reset. So wait. (TODO: Add a register
+* to read the current reset states, or DDR Control device?)
+*/
+ for (int i = 0; i < 256; i++)
+ asm volatile ("nop");
+
+ /* GEMGXL init */
+ clock.id = PRCI_CLK_GEMGXLPLL;
+ sifive_fu540_prci_set_rate(, 125UL * MHz);
+ sifive_fu540_prci_clock_enable(&__prci_init_clocks[clock.id], 1);
+
+ /* Release GEMGXL reset */
+ v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET);
+ v |= PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK;
+ __prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd);
+
+ /* Procmon => core clock */
+ __prci_writel(PRCI_PROCMONCFG_CORE_CLOCK_MASK, PRCI_PROCMONCFG_OFFSET,
+ pd);
+#endif
+
return 0;
}
--
2.17.1
[PATCH v4 10/14] riscv: sifive: fu540: add SPL configuration
Add a support for SPL which will boot from L2 LIM (0x0800_) and
then boot U-boot FIT image including OpenSBI FW_DYNAMIC firmware
and U-Boot proper images from 1st partition of MMC boot devices.
SPL related code is leverage from FSBL
(https://github.com/sifive/freedom-u540-c000-bootloader.git)
Signed-off-by: Pragnesh Patel
Tested-by: Yash Shah
---
board/sifive/fu540/Kconfig| 8 +++
board/sifive/fu540/Makefile | 4 ++
board/sifive/fu540/fu540-memory-map.h | 33
board/sifive/fu540/fu540.c| 24 +
board/sifive/fu540/spl.c | 78 +++
board/sifive/fu540/ux00prci.h | 56 +++
include/configs/sifive-fu540.h| 18 +++
7 files changed, 221 insertions(+)
create mode 100644 board/sifive/fu540/fu540-memory-map.h
create mode 100644 board/sifive/fu540/spl.c
create mode 100644 board/sifive/fu540/ux00prci.h
diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
index 900197bbb2..ebe3472f9a 100644
--- a/board/sifive/fu540/Kconfig
+++ b/board/sifive/fu540/Kconfig
@@ -13,12 +13,20 @@ config SYS_CONFIG_NAME
default "sifive-fu540"
config SYS_TEXT_BASE
+ default 0x8020 if SPL
default 0x8000 if !RISCV_SMODE
default 0x8020 if RISCV_SMODE
+config SPL_TEXT_BASE
+ default 0x0800
+
+config SPL_OPENSBI_LOAD_ADDR
+ default 0x8000
+
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select GENERIC_RISCV
+ select SUPPORT_SPL
imply CMD_DHCP
imply CMD_EXT2
imply CMD_EXT4
diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile
index 6e1862c475..b05e2f5807 100644
--- a/board/sifive/fu540/Makefile
+++ b/board/sifive/fu540/Makefile
@@ -3,3 +3,7 @@
# Copyright (c) 2019 Western Digital Corporation or its affiliates.
obj-y += fu540.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
diff --git a/board/sifive/fu540/fu540-memory-map.h
b/board/sifive/fu540/fu540-memory-map.h
new file mode 100644
index 00..c65203726b
--- /dev/null
+++ b/board/sifive/fu540/fu540-memory-map.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2019 SiFive, Inc
+ */
+
+#ifndef FU540_MEMORY_MAP
+#define FU540_MEMORY_MAP
+
+#include
+#include "ux00prci.h"
+
+/
+ * Platform definitions
+ */
+
+/* Memory map */
+#define GPIO_CTRL_ADDR _AC(0x1006, UL)
+
+#define PHYSICAL_FILTER_CTRL_ADDR _AC(0x100b8000, UL)
+
+#define UX00DDR_CTRL_ADDR _AC(0x100b, UL)
+#define UX00PRCI_CTRL_ADDR _AC(0x1000, UL)
+
+/* Helper functions */
+#define _REG32(p, i)(*(volatile uint32_t *)((p) + (i)))
+
+#define UX00PRCI_REG(offset) \
+ _REG32(UX00PRCI_CTRL_ADDR, \
+ offset)
+
+#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
+
+#endif /* FU540_MEMORY_MAP */
diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
index 409471effc..fba9469c2d 100644
--- a/board/sifive/fu540/fu540.c
+++ b/board/sifive/fu540/fu540.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
/*
* This define is a value used for error/unknown serial.
@@ -114,3 +115,26 @@ int board_init(void)
return 0;
}
+
+#ifdef CONFIG_SPL
+void board_boot_order(u32 *spl_boot_list)
+{
+ u8 i;
+ u32 boot_devices[] = {
+#ifdef CONFIG_SPL_MMC_SUPPORT
+ BOOT_DEVICE_MMC1,
+#endif
+ };
+
+ for (i = 0; i < ARRAY_SIZE(boot_devices); i++)
+ spl_boot_list[i] = boot_devices[i];
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ /* boot using first FIT config */
+ return 0;
+}
+#endif
diff --git a/board/sifive/fu540/spl.c b/board/sifive/fu540/spl.c
new file mode 100644
index 00..522bc24753
--- /dev/null
+++ b/board/sifive/fu540/spl.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 SiFive, Inc
+ *
+ * Authors:
+ * Pragnesh Patel
+ */
+
+#include
+#include
+#include
+#include
+
+#include "fu540-memory-map.h"
+
+#define DDRCTLPLL_F 55
+#define DDRCTLPLL_Q 2
+
+#define PHY_NRESET 0x1000
+
+long nsec_per_cyc = 300; /* 33.333MHz */
+void nsleep(long nsec)
+{
+ long step = nsec_per_cyc * 2;
+
+ while (nsec > 0)
+ nsec -= step;
+}
+
+void init_clk_and_ddr(void)
+{
+ int ret;
+ struct udevice *dev;
+
+ /* PRCI init */
+ ret = uclass_get_device(UCLASS_CLK, 0, );
+ if (ret) {
+ debug("Clock init failed: %d\n", ret);
+ return;
+ }
+
+ ret = uclass_get_device(UCLASS_RAM, 0, );
+ if (ret) {
+ printf("DRAM init failed: %d\n", ret);
+ return;
+ }
+
+ /*
+* GEMGXL
[PATCH v4 11/14] configs: fu540: Add config options for U-boot SPL
With sifive_fu540_defconfig: User can use FSBL or u-boot-spl.bin anyone at a time. For FSBL, fsbl->fw_payload.bin(opensbi+u-boot) For u-boot-spl.bin, u-boot-spl.bin->FIT image(opensbi+u-boot+dtb) U-Boot SPL will be loaded by ZSBL from SD card (replace fsbl.bin with u-boot-spl.bin) and runs in L2 LIM in machine mode and then load FIT image u-boot.itb from 1st partition of SD card (replace fw_payload.bin with u-boot.itb) into RAM. U-boot SPL expects u-boot.itb FIT image in the 1st partition of SD card irrespective of GUID Signed-off-by: Pragnesh Patel --- configs/sifive_fu540_defconfig | 11 +++ 1 file changed, 11 insertions(+) diff --git a/configs/sifive_fu540_defconfig b/configs/sifive_fu540_defconfig index 6d61e6c960..24aab7783b 100644 --- a/configs/sifive_fu540_defconfig +++ b/configs/sifive_fu540_defconfig @@ -12,3 +12,14 @@ CONFIG_DISPLAY_BOARDINFO=y CONFIG_DEFAULT_DEVICE_TREE="hifive-unleashed-a00" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=1 +CONFIG_SPL_CLK=y +CONFIG_SPL_PAYLOAD="u-boot.itb" +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_SIFIVE_FU540_DDR=y -- 2.17.1
[PATCH v4 03/14] riscv: Add _image_binary_end for SPL
For SPL_SEPARATE_BSS, Device tree will be put at _image_binary_end
Signed-off-by: Pragnesh Patel
Reviewed-by: Anup Patel
Reviewed-by: Jagan Teki
---
arch/riscv/cpu/u-boot-spl.lds | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/cpu/u-boot-spl.lds b/arch/riscv/cpu/u-boot-spl.lds
index 955dd3106d..d0495ce248 100644
--- a/arch/riscv/cpu/u-boot-spl.lds
+++ b/arch/riscv/cpu/u-boot-spl.lds
@@ -72,6 +72,7 @@ SECTIONS
. = ALIGN(4);
_end = .;
+ _image_binary_end = .;
.bss : {
__bss_start = .;
--
2.17.1
[PATCH v4 06/14] sifive: fu540: add ddr driver
Add driver for fu540 to support ddr initialization in SPL.
This driver is based on FSBL
(https://github.com/sifive/freedom-u540-c000-bootloader.git)
Signed-off-by: Pragnesh Patel
---
drivers/ram/Kconfig | 7 +
drivers/ram/Makefile | 2 +
drivers/ram/sifive/Kconfig | 8 +
drivers/ram/sifive/Makefile | 6 +
drivers/ram/sifive/sdram_fu540.c | 295 +++
drivers/ram/sifive/sdram_fu540.h | 94 ++
6 files changed, 412 insertions(+)
create mode 100644 drivers/ram/sifive/Kconfig
create mode 100644 drivers/ram/sifive/Makefile
create mode 100644 drivers/ram/sifive/sdram_fu540.c
create mode 100644 drivers/ram/sifive/sdram_fu540.h
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 56fea7c94c..c60c63204c 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -73,5 +73,12 @@ config IMXRT_SDRAM
to support external memories like sdram, psram & nand.
This driver is for the sdram memory interface with the SEMC.
+config SIFIVE_DDR
+ bool "Enable SiFive DDR support"
+ depends on RAM
+ help
+ Enable support for the internal DDR Memory Controller of SiFive SoCs.
+
source "drivers/ram/rockchip/Kconfig"
source "drivers/ram/stm32mp1/Kconfig"
+source "drivers/ram/sifive/Kconfig"
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index 5c897410c6..12bf61510b 100644
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -17,3 +17,5 @@ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e/
obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
+
+obj-$(CONFIG_SIFIVE_DDR) += sifive/
diff --git a/drivers/ram/sifive/Kconfig b/drivers/ram/sifive/Kconfig
new file mode 100644
index 00..b754700db8
--- /dev/null
+++ b/drivers/ram/sifive/Kconfig
@@ -0,0 +1,8 @@
+config SIFIVE_FU540_DDR
+ bool "SiFive FU540 DDR driver"
+ depends on DM && OF_CONTROL
+ select RAM
+ select SPL_RAM if SPL
+ select SIFIVE_DDR
+ help
+ This enables DDR support for the platforms based on SiFive FU540 SoC.
diff --git a/drivers/ram/sifive/Makefile b/drivers/ram/sifive/Makefile
new file mode 100644
index 00..0187805199
--- /dev/null
+++ b/drivers/ram/sifive/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2020 SiFive, Inc
+#
+
+obj-$(CONFIG_SIFIVE_FU540_DDR) += sdram_fu540.o
diff --git a/drivers/ram/sifive/sdram_fu540.c b/drivers/ram/sifive/sdram_fu540.c
new file mode 100644
index 00..18926dbe15
--- /dev/null
+++ b/drivers/ram/sifive/sdram_fu540.c
@@ -0,0 +1,295 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * (C) Copyright 2020 SiFive, Inc.
+ *
+ * Authors:
+ * Pragnesh Patel
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "sdram_fu540.h"
+
+/* n: Unit bytes */
+void sdram_copy_to_reg(volatile u32 *dest, volatile u32 *src, u32 n)
+{
+ int i;
+
+ for (i = 0; i < n / sizeof(u32); i++) {
+ writel(*src, dest);
+ src++;
+ dest++;
+ }
+}
+
+static void ddr_setuprangeprotection(volatile u32 *ctl, u64 end_addr)
+{
+ writel(0x0, DENALI_CTL_209 + ctl);
+ u32 end_addr_16kblocks = ((end_addr >> 14) & 0x7F) - 1;
+
+ writel(end_addr_16kblocks, DENALI_CTL_210 + ctl);
+ writel(0x0, DENALI_CTL_212 + ctl);
+ writel(0x0, DENALI_CTL_214 + ctl);
+ writel(0x0, DENALI_CTL_216 + ctl);
+ setbits_le32(DENALI_CTL_224 + ctl,
+0x3 << AXI0_RANGE_PROT_BITS_0_OFFSET);
+ writel(0x, DENALI_CTL_225 + ctl);
+ setbits_le32(DENALI_CTL_208 + ctl, 0x1 << AXI0_ADDRESS_RANGE_ENABLE);
+ setbits_le32(DENALI_CTL_208 + ctl,
+0x1 << PORT_ADDR_PROTECTION_EN_OFFSET);
+}
+
+static void ddr_start(volatile u32 *ctl, u32 *physical_filter_ctrl, u64
ddr_end)
+{
+ setbits_le32(DENALI_CTL_0 + ctl, 0x1);
+ while ((readl(DENALI_CTL_132 + ctl) & (1 << MC_INIT_COMPLETE_OFFSET))
+ == 0) {
+ }
+
+ // Disable the BusBlocker in front of the controller AXI slave ports
+ volatile u64 *filterreg = (volatile u64 *)physical_filter_ctrl;
+
+ filterreg[0] = 0x0f00UL | (ddr_end >> 2);
+}
+
+static u64 ddr_phy_fixup(volatile u32 *ddrphyreg)
+{
+ // return bitmask of failed lanes
+
+ u64 fails = 0;
+ u32 slicebase = 0;
+ u32 dq= 0;
+
+ // check errata condition
+ for (u32 slice = 0; slice < 8; slice++) {
+ u32 regbase = slicebase + 34;
+
+ for (u32 reg = 0; reg < 4; reg++) {
+ u32 updownreg = readl(regbase + reg + ddrphyreg);
+
+ for (u32 bit = 0; bit < 2; bit++) {
+ u32 phy_rx_cal_dqn_0_offset;
+
+ if (bit == 0) {
+ phy_rx_cal_dqn_0_offset =
+
[PATCH v4 05/14] riscv: sifive: dts: fu540: Add board -u-boot.dtsi files
Devicetree files in FU540 platform is synced from Linux, like other
platforms does. Apart from these u-boot in FU540 would also require
some u-boot specific node like clint.
So, create board specific -u-boot.dtsi files. This would help of
maintain u-boot specific changes separately without touching Linux
dts(i) files which indeed easy for syncing from Linux between
releases.
Signed-off-by: Pragnesh Patel
Reviewed-by: Anup Patel
---
arch/riscv/dts/fu540-c000-u-boot.dtsi | 42 +++
.../dts/hifive-unleashed-a00-u-boot.dtsi | 16 +++
2 files changed, 58 insertions(+)
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi
b/arch/riscv/dts/fu540-c000-u-boot.dtsi
index 31fd113c7d..2d3d62801f 100644
--- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -4,11 +4,53 @@
*/
/ {
+ cpus {
+ u-boot,dm-spl;
+ cpu0: cpu@0 {
+ u-boot,dm-spl;
+ status = "okay";
+ cpu0_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ cpu1: cpu@1 {
+ u-boot,dm-spl;
+ };
+ cpu2: cpu@2 {
+ u-boot,dm-spl;
+ };
+ cpu3: cpu@3 {
+ u-boot,dm-spl;
+ };
+ cpu4: cpu@4 {
+ u-boot,dm-spl;
+ };
+ };
+
soc {
+ u-boot,dm-spl;
otp: otp@1007 {
compatible = "sifive,fu540-otp";
reg = <0x0 0x1007 0x0 0x0FFF>;
fuse-count = <0x1000>;
};
+ clint@200 {
+ compatible = "riscv,clint0";
+ interrupts-extended = <_intc 3 _intc 7 >;
+ reg = <0x0 0x200 0x0 0xc>;
+ u-boot,dm-spl;
+ };
};
};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
index bec0d19134..cce1bd943e 100644
--- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
+++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
@@ -4,3 +4,19 @@
*/
#include "fu540-c000-u-boot.dtsi"
+
+/ {
+ hfclk {
+ u-boot,dm-spl;
+ };
+
+ rtcclk {
+ u-boot,dm-spl;
+ };
+};
+
+ {
+ mmc@0 {
+ u-boot,dm-spl;
+ };
+};
--
2.17.1
[PATCH v4 08/14] clk: sifive: fu540-prci: Add clock enable and disable ops
Added clock enable and disable functions in prci ops
Signed-off-by: Pragnesh Patel
---
drivers/clk/sifive/fu540-prci.c | 75 +++--
1 file changed, 72 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
index 8847178001..c02c0466a8 100644
--- a/drivers/clk/sifive/fu540-prci.c
+++ b/drivers/clk/sifive/fu540-prci.c
@@ -68,6 +68,11 @@
#define PRCI_COREPLLCFG0_LOCK_SHIFT31
#define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT)
+/* COREPLLCFG1 */
+#define PRCI_COREPLLCFG1_OFFSET0x8
+#define PRCI_COREPLLCFG1_CKE_SHIFT 31
+#define PRCI_COREPLLCFG1_CKE_MASK (0x1 << PRCI_COREPLLCFG1_CKE_SHIFT)
+
/* DDRPLLCFG0 */
#define PRCI_DDRPLLCFG0_OFFSET 0xc
#define PRCI_DDRPLLCFG0_DIVR_SHIFT 0
@@ -87,7 +92,7 @@
/* DDRPLLCFG1 */
#define PRCI_DDRPLLCFG1_OFFSET 0x10
-#define PRCI_DDRPLLCFG1_CKE_SHIFT 24
+#define PRCI_DDRPLLCFG1_CKE_SHIFT 31
#define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT)
/* GEMGXLPLLCFG0 */
@@ -114,7 +119,7 @@
/* GEMGXLPLLCFG1 */
#define PRCI_GEMGXLPLLCFG1_OFFSET 0x20
-#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 24
+#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 31
#define PRCI_GEMGXLPLLCFG1_CKE_MASK(0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT)
/* CORECLKSEL */
@@ -142,7 +147,7 @@
(0x1 << PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT)
/* CLKMUXSTATUSREG */
-#define PRCI_CLKMUXSTATUSREG_OFFSET0x2c
+#define PRCI_CLKMUXSTATUSREG_OFFSET0x2c
#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1
#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \
(0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT)
@@ -170,6 +175,7 @@ struct __prci_data {
* @enable_bypass: fn ptr to code to bypass the WRPLL (if applicable; else
NULL)
* @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL)
* @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI base address
+ * @cfg1_offs: WRPLL CFG1 register offset (in bytes) from the PRCI base address
*
* @enable_bypass and @disable_bypass are used for WRPLL instances
* that contain a separate external glitchless clock mux downstream
@@ -180,6 +186,7 @@ struct __prci_wrpll_data {
void (*enable_bypass)(struct __prci_data *pd);
void (*disable_bypass)(struct __prci_data *pd);
u8 cfg0_offs;
+ u8 cfg1_offs;
};
struct __prci_clock;
@@ -194,6 +201,7 @@ struct __prci_clock_ops {
unsigned long *parent_rate);
unsigned long (*recalc_rate)(struct __prci_clock *pc,
unsigned long parent_rate);
+ int (*enable_clk)(struct __prci_clock *pc, bool enable);
};
/**
@@ -356,6 +364,13 @@ static void __prci_wrpll_write_cfg(struct __prci_data *pd,
memcpy(>c, c, sizeof(*c));
}
+static void __prci_wrpll_write_cfg1(struct __prci_data *pd,
+ struct __prci_wrpll_data *pwd,
+ u32 enable)
+{
+ __prci_writel(enable, pwd->cfg1_offs, pd);
+}
+
/* Core clock mux control */
/**
@@ -447,14 +462,35 @@ static int sifive_fu540_prci_wrpll_set_rate(struct
__prci_clock *pc,
return 0;
}
+static int sifive_fu540_prci_clock_enable(struct __prci_clock *pc, bool enable)
+{
+ struct __prci_wrpll_data *pwd = pc->pwd;
+ struct __prci_data *pd = pc->pd;
+
+ if (enable) {
+ __prci_wrpll_write_cfg1(pd, pwd, PRCI_COREPLLCFG1_CKE_MASK);
+ } else {
+ u32 r;
+
+ r = __prci_readl(pd, pwd->cfg1_offs);
+ r &= ~PRCI_COREPLLCFG1_CKE_MASK;
+
+ __prci_wrpll_write_cfg1(pd, pwd, r);
+ }
+
+ return 0;
+}
+
static const struct __prci_clock_ops sifive_fu540_prci_wrpll_clk_ops = {
.set_rate = sifive_fu540_prci_wrpll_set_rate,
.round_rate = sifive_fu540_prci_wrpll_round_rate,
.recalc_rate = sifive_fu540_prci_wrpll_recalc_rate,
+ .enable_clk = sifive_fu540_prci_clock_enable,
};
static const struct __prci_clock_ops sifive_fu540_prci_wrpll_ro_clk_ops = {
.recalc_rate = sifive_fu540_prci_wrpll_recalc_rate,
+ .enable_clk = sifive_fu540_prci_clock_enable,
};
/* TLCLKSEL clock integration */
@@ -484,16 +520,19 @@ static const struct __prci_clock_ops
sifive_fu540_prci_tlclksel_clk_ops = {
static struct __prci_wrpll_data __prci_corepll_data = {
.cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
+ .cfg1_offs = PRCI_COREPLLCFG1_OFFSET,
.enable_bypass = __prci_coreclksel_use_hfclk,
.disable_bypass = __prci_coreclksel_use_corepll,
};
static struct __prci_wrpll_data __prci_ddrpll_data = {
.cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
+ .cfg1_offs = PRCI_DDRPLLCFG1_OFFSET,
};
static struct __prci_wrpll_data __prci_gemgxlpll_data = {
.cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
[PATCH v4 04/14] lib: Makefile: build crc7.c when CONFIG_MMC_SPI
When build U-boot SPL, meet an issue of undefined reference to 'crc7' for drivers/mmc/mmc_spi.c, so let's compile crc7.c when CONFIG_MMC_SPI selected. Signed-off-by: Pragnesh Patel --- common/spl/Kconfig | 7 +++ lib/Makefile | 1 + 2 files changed, 8 insertions(+) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index b03a476b9f..f93f552f5e 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -401,6 +401,13 @@ config SPL_CRC32_SUPPORT for detected accidental image corruption. For secure applications you should consider SHA1 or SHA256. +config SPL_CRC7_SUPPORT + bool "Support CRC7" + default y if MMC_SPI + help + Enable CRC7 hashing for drivers which are using in SPL. + This is a 32-bit checksum value that can be used to verify images. + config SPL_MD5_SUPPORT bool "Support MD5" depends on SPL_FIT diff --git a/lib/Makefile b/lib/Makefile index 15259d0473..7a50aa56ef 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -78,6 +78,7 @@ endif ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16.o +obj-$(CONFIG_SPL_CRC7_SUPPORT) += crc7.o obj-$(CONFIG_$(SPL_TPL_)HASH_SUPPORT) += crc16.o obj-y += net_utils.o endif -- 2.17.1
[PATCH v4 01/14] misc: add driver for the SiFive otp controller
Added a misc driver to handle OTP memory in SiFive SoCs.
Signed-off-by: Pragnesh Patel
---
drivers/misc/Kconfig | 7 ++
drivers/misc/Makefile | 1 +
drivers/misc/sifive-otp.c | 241 ++
3 files changed, 249 insertions(+)
create mode 100644 drivers/misc/sifive-otp.c
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index f18aa8f7ba..fcb45c63d4 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -68,6 +68,13 @@ config ROCKCHIP_OTP
addressing and a length or through child-nodes that are generated
based on the e-fuse map retrieved from the DTS.
+config SIFIVE_OTP
+ bool "SiFive Ememory OTP driver"
+ depends on RISCV && MISC
+ help
+ Enable support for reading and writing the ememory OTP on the
+ SiFive SoCs.
+
config VEXPRESS_CONFIG
bool "Enable support for Arm Versatile Express config bus"
depends on MISC
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 2b843de93c..ee888631b6 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -58,6 +58,7 @@ obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o
obj-$(CONFIG_QFW) += qfw.o
obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o
obj-$(CONFIG_ROCKCHIP_OTP) += rockchip-otp.o
+obj-$(CONFIG_SIFIVE_OTP) += sifive-otp.o
obj-$(CONFIG_SANDBOX) += syscon_sandbox.o misc_sandbox.o
obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o
diff --git a/drivers/misc/sifive-otp.c b/drivers/misc/sifive-otp.c
new file mode 100644
index 00..6a39ec42df
--- /dev/null
+++ b/drivers/misc/sifive-otp.c
@@ -0,0 +1,241 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * This is a driver for the eMemory EG004K32TQ028XW01 NeoFuse
+ * One-Time-Programmable (OTP) memory used within the SiFive FU540.
+ * It is documented in the FU540 manual here:
+ * https://www.sifive.com/documentation/chips/freedom-u540-c000-manual/
+ *
+ * Copyright (C) 2018 Philipp Hug
+ * Copyright (C) 2018 Joey Hewitt
+ *
+ * Copyright (C) 2020 SiFive, Inc
+ */
+
+/*
+ * The FU540 stores 4096x32 bit (16KiB) values.
+ * Index 0x00-0xff are reserved for SiFive internal use. (first 1KiB)
+ * Right now first 1KB is used to store only serial number.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define BYTES_PER_FUSE 4
+
+#define PA_RESET_VAL 0x00
+#define PAS_RESET_VAL 0x00
+#define PAIO_RESET_VAL 0x00
+#define PDIN_RESET_VAL 0x00
+#define PTM_RESET_VAL 0x00
+
+#define PCLK_ENABLE_VALBIT(0)
+#define PCLK_DISABLE_VAL 0x00
+
+#define PWE_WRITE_ENABLE BIT(0)
+#define PWE_WRITE_DISABLE 0x00
+
+#define PTM_FUSE_PROGRAM_VAL BIT(1)
+
+#define PCE_ENABLE_INPUT BIT(0)
+#define PCE_DISABLE_INPUT 0x00
+
+#define PPROG_ENABLE_INPUT BIT(0)
+#define PPROG_DISABLE_INPUT0x00
+
+#define PTRIM_ENABLE_INPUT BIT(0)
+#define PTRIM_DISABLE_INPUT0x00
+
+#define PDSTB_DEEP_STANDBY_ENABLE BIT(0)
+#define PDSTB_DEEP_STANDBY_DISABLE 0x00
+
+struct sifive_otp_regs {
+ u32 pa; /* Address input */
+ u32 paio; /* Program address input */
+ u32 pas;/* Program redundancy cell selection input */
+ u32 pce;/* OTP Macro enable input */
+ u32 pclk; /* Clock input */
+ u32 pdin; /* Write data input */
+ u32 pdout; /* Read data output */
+ u32 pdstb; /* Deep standby mode enable input (active low) */
+ u32 pprog; /* Program mode enable input */
+ u32 ptc;/* Test column enable input */
+ u32 ptm;/* Test mode enable input */
+ u32 ptm_rep;/* Repair function test mode enable input */
+ u32 ptr;/* Test row enable input */
+ u32 ptrim; /* Repair function enable input */
+ u32 pwe;/* Write enable input (defines program cycle) */
+} __packed;
+
+struct sifive_otp_platdata {
+ struct sifive_otp_regs __iomem *regs;
+ u32 total_fuses;
+};
+
+/*
+ * offset and size are assumed aligned to the size of the fuses (32bit).
+ */
+static int sifive_otp_read(struct udevice *dev, int offset,
+ void *buf, int size)
+{
+ struct sifive_otp_platdata *plat = dev_get_platdata(dev);
+ struct sifive_otp_regs *regs = (struct sifive_otp_regs *)plat->regs;
+
+ int fuseidx = offset / BYTES_PER_FUSE;
+ int fusecount = size / BYTES_PER_FUSE;
+ u32 fusebuf[fusecount];
+
+ /* check bounds */
+ if (offset < 0 || size < 0)
+ return -EINVAL;
+ if (fuseidx >= plat->total_fuses)
+ return -EINVAL;
+ if ((fuseidx + fusecount) > plat->total_fuses)
+ return -EINVAL;
+
+ /* init OTP */
+ iowrite32(PDSTB_DEEP_STANDBY_ENABLE, >pdstb);
+ iowrite32(PTRIM_ENABLE_INPUT, >ptrim);
+ iowrite32(PCE_ENABLE_INPUT,
[PATCH v4 02/14] riscv: sifive: fu540: Use OTP DM driver for serial environment variable
Use the OTP DM driver to set the serial environment variable.
Signed-off-by: Pragnesh Patel
---
arch/riscv/dts/fu540-c000-u-boot.dtsi | 14 +++
.../dts/hifive-unleashed-a00-u-boot.dtsi | 6 +
board/sifive/fu540/Kconfig| 2 +
board/sifive/fu540/fu540.c| 113 +++---
4 files changed, 62 insertions(+), 73 deletions(-)
create mode 100644 arch/riscv/dts/fu540-c000-u-boot.dtsi
create mode 100644 arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi
b/arch/riscv/dts/fu540-c000-u-boot.dtsi
new file mode 100644
index 00..31fd113c7d
--- /dev/null
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 SiFive, Inc
+ */
+
+/ {
+ soc {
+ otp: otp@1007 {
+ compatible = "sifive,fu540-otp";
+ reg = <0x0 0x1007 0x0 0x0FFF>;
+ fuse-count = <0x1000>;
+ };
+ };
+};
diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
new file mode 100644
index 00..bec0d19134
--- /dev/null
+++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 SiFive, Inc
+ */
+
+#include "fu540-c000-u-boot.dtsi"
diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
index 5ca21474de..900197bbb2 100644
--- a/board/sifive/fu540/Kconfig
+++ b/board/sifive/fu540/Kconfig
@@ -48,5 +48,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply SIFIVE_GPIO
imply CMD_GPIO
imply SMP
+ imply MISC
+ imply SIFIVE_OTP
endif
diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
index 47a2090251..409471effc 100644
--- a/board/sifive/fu540/fu540.c
+++ b/board/sifive/fu540/fu540.c
@@ -10,94 +10,61 @@
#include
#include
#include
+#include
-#ifdef CONFIG_MISC_INIT_R
-
-#define FU540_OTP_BASE_ADDR0x1007
-
-struct fu540_otp_regs {
- u32 pa; /* Address input */
- u32 paio; /* Program address input */
- u32 pas;/* Program redundancy cell selection input */
- u32 pce;/* OTP Macro enable input */
- u32 pclk; /* Clock input */
- u32 pdin; /* Write data input */
- u32 pdout; /* Read data output */
- u32 pdstb; /* Deep standby mode enable input (active low) */
- u32 pprog; /* Program mode enable input */
- u32 ptc;/* Test column enable input */
- u32 ptm;/* Test mode enable input */
- u32 ptm_rep;/* Repair function test mode enable input */
- u32 ptr;/* Test row enable input */
- u32 ptrim; /* Repair function enable input */
- u32 pwe;/* Write enable input (defines program cycle) */
-} __packed;
-
-#define BYTES_PER_FUSE 4
-#define NUM_FUSES 0x1000
-
-static int fu540_otp_read(int offset, void *buf, int size)
-{
- struct fu540_otp_regs *regs = (void __iomem *)FU540_OTP_BASE_ADDR;
- unsigned int i;
- int fuseidx = offset / BYTES_PER_FUSE;
- int fusecount = size / BYTES_PER_FUSE;
- u32 fusebuf[fusecount];
-
- /* check bounds */
- if (offset < 0 || size < 0)
- return -EINVAL;
- if (fuseidx >= NUM_FUSES)
- return -EINVAL;
- if ((fuseidx + fusecount) > NUM_FUSES)
- return -EINVAL;
-
- /* init OTP */
- writel(0x01, >pdstb); /* wake up from stand-by */
- writel(0x01, >ptrim); /* enable repair function */
- writel(0x01, >pce); /* enable input */
-
- /* read all requested fuses */
- for (i = 0; i < fusecount; i++, fuseidx++) {
- writel(fuseidx, >pa);
-
- /* cycle clock to read */
- writel(0x01, >pclk);
- mdelay(1);
- writel(0x00, >pclk);
- mdelay(1);
-
- /* read the value */
- fusebuf[i] = readl(>pdout);
- }
-
- /* shut down */
- writel(0, >pce);
- writel(0, >ptrim);
- writel(0, >pdstb);
-
- /* copy out */
- memcpy(buf, fusebuf, size);
+/*
+ * This define is a value used for error/unknown serial.
+ * If we really care about distinguishing errors and 0 is
+ * valid, we'll need a different one.
+ */
+#define ERROR_READING_SERIAL_NUMBER 0
- return 0;
-}
+#ifdef CONFIG_MISC_INIT_R
-static u32 fu540_read_serialnum(void)
+#if CONFIG_IS_ENABLED(SIFIVE_OTP)
+static u32 otp_read_serialnum(struct udevice *dev)
{
int ret;
u32 serial[2] = {0};
for (int i = 0xfe * 4; i > 0; i -= 8) {
- ret = fu540_otp_read(i, serial, sizeof(serial));
+ ret = misc_read(dev, i, serial, sizeof(serial));
+
if (ret) {
-
[PATCH v4 00/14] RISC-V SiFive FU540 support SPL
This series add support for SPL to FU540.U-Boot SPL can boot from L2 LIM (0x0800_) and jump to OpenSBI(FW_DYNAMIC firmware) and U-Boot proper from MMC devices. How to test this patch: 1) Go to OpenSBI-dir : make PLATFORM=sifive/fu540 O=build_dir I=install_dir FW_DYNAMIC=y install 2) cp install_dir/platform/sifive/fu540/firmware/fw_dynamic.bin / 3) Change to u-boot-dir 4) make sifive_fu540_defconfig 5) make all 6) ZSBL loads the U-boot SPL(u-boot-spl.bin) from a partition with GUID type 5B193300-FC78-40CD-8002-E86C45580B47 sudo dd if=spl/u-boot-spl.bin of=/dev/sdc4 bs=1M 7) U-boot SPL expects a u-boot FIT image(u-boot.itb) from 1st partition(/dev/sdc1) of SD card irrespective of GUID sudo dd if=u-boot.itb of=/dev/sdc1 bs=1M Thanks to Yash Shah for testing the series. Changes in v4: - Split misc DM driver patch into multiple patches - Added new SPL_CRC7_SUPPORT Kconfig option - Added DM driver for DDR - Added clk_enable and clk_disable ops in SiFive PRCI driver - Added early clock initialization for SPL in SiFive PRCI driver - Added SPL config options in sifive_fu540_defconfig instead of creatiing a new config file for SPL - Update fu540.rst on how to build and flash U-boot SPL Changes in v3: - Remove arch-fu540 and arch-sifive from arch/riscv/include/asm/ - Split SPL patches into DDR and SPL and spl defconfig - Update fu540/MAINTAINERS file - Update fu540.rst on how to build and flash U-boot SPL Changes in v2: - Add DM driver Sifive OTP - Split SPL patches into multiple patches - Add a seprate patch for _image_binary_end and crc7.c - Add a seprate patch to add board -u-boot.dtsi files - Update FU540 RISC-V documentation Pragnesh Patel (14): misc: add driver for the SiFive otp controller riscv: sifive: fu540: Use OTP DM driver for serial environment variable riscv: Add _image_binary_end for SPL lib: Makefile: build crc7.c when CONFIG_MMC_SPI riscv: sifive: dts: fu540: Add board -u-boot.dtsi files sifive: fu540: add ddr driver sifive: dts: fu540: Add DDR controller and phy register settings clk: sifive: fu540-prci: Add clock enable and disable ops clk: sifive: fu540-prci: Add clock initialization for SPL riscv: sifive: fu540: add SPL configuration configs: fu540: Add config options for U-boot SPL riscv: sifive: fu540: enable all cache ways from u-boot proper sifive: fix palmer's email address doc: update FU540 RISC-V documentation arch/riscv/cpu/u-boot-spl.lds |1 + arch/riscv/dts/fu540-c000-u-boot.dtsi | 63 + arch/riscv/dts/fu540-sdram-lpddr4.dtsi| 1489 + .../dts/hifive-unleashed-a00-u-boot.dtsi | 23 + board/sifive/fu540/Kconfig| 10 + board/sifive/fu540/MAINTAINERS|2 +- board/sifive/fu540/Makefile |5 + board/sifive/fu540/cache.c| 20 + board/sifive/fu540/cache.h| 13 + board/sifive/fu540/fu540-memory-map.h | 33 + board/sifive/fu540/fu540.c| 139 +- board/sifive/fu540/spl.c | 78 + board/sifive/fu540/ux00prci.h | 56 + common/spl/Kconfig|7 + configs/sifive_fu540_defconfig| 11 + doc/board/sifive/fu540.rst| 409 - drivers/clk/sifive/fu540-prci.c | 169 +- drivers/misc/Kconfig |7 + drivers/misc/Makefile |1 + drivers/misc/sifive-otp.c | 241 +++ drivers/ram/Kconfig |7 + drivers/ram/Makefile |2 + drivers/ram/sifive/Kconfig|8 + drivers/ram/sifive/Makefile |6 + drivers/ram/sifive/sdram_fu540.c | 295 drivers/ram/sifive/sdram_fu540.h | 94 ++ include/configs/sifive-fu540.h| 18 + lib/Makefile |1 + 28 files changed, 3107 insertions(+), 101 deletions(-) create mode 100644 arch/riscv/dts/fu540-c000-u-boot.dtsi create mode 100644 arch/riscv/dts/fu540-sdram-lpddr4.dtsi create mode 100644 arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi create mode 100644 board/sifive/fu540/cache.c create mode 100644 board/sifive/fu540/cache.h create mode 100644 board/sifive/fu540/fu540-memory-map.h create mode 100644 board/sifive/fu540/spl.c create mode 100644 board/sifive/fu540/ux00prci.h create mode 100644 drivers/misc/sifive-otp.c create mode 100644 drivers/ram/sifive/Kconfig create mode 100644 drivers/ram/sifive/Makefile create mode 100644 drivers/ram/sifive/sdram_fu540.c create mode 100644 drivers/ram/sifive/sdram_fu540.h -- 2.17.1
