[U-Boot] [PATCH] scripts: Add script to extract default environment

[Lukasz Majewski]

This script looks for env_common.o object file and extracts from it default
u-boot environment, which is afterwards printed on standard output.

Usage example:
get_default_envs.sh > u-boot-env-default.txt

The generated text file can be used as input for mkenvimage.

Signed-off-by: Lukasz Majewski 
---
 scripts/get_default_envs.sh | 33 +
 1 file changed, 33 insertions(+)
 create mode 100755 scripts/get_default_envs.sh

diff --git a/scripts/get_default_envs.sh b/scripts/get_default_envs.sh
new file mode 100755
index 000..5c5a78a
--- /dev/null
+++ b/scripts/get_default_envs.sh
@@ -0,0 +1,33 @@
+#! /bin/bash
+#
+# Copyright (C) 2016, Lukasz Majewski 
+#
+# SPDX-License-Identifier:  GPL-2.0+
+#
+
+# This file extracts default envs from built u-boot
+# usage: get_default_envs.sh > u-boot-env-default.txt
+set -ue
+
+ENV_OBJ_FILE="env_common.o"
+ENV_OBJ_FILE_COPY="copy_${ENV_OBJ_FILE}"
+
+echoerr() { echo "$@" 1>&2; }
+
+path=$(readlink -f $0)
+env_obj_file_path=$(find ${path%/scripts*} -name "${ENV_OBJ_FILE}")
+[ -z "${env_obj_file_path}" ] && \
+{ echoerr "File '${ENV_OBJ_FILE}' not found!"; exit 1; }
+
+cp ${env_obj_file_path} ${ENV_OBJ_FILE_COPY}
+
+# NOTE: objcopy saves its output to file passed in
+# (copy_env_common.o in this case)
+objcopy -O binary -j ".rodata.default_environment" ${ENV_OBJ_FILE_COPY}
+
+# Replace default '\0' with '\n'
+tr '\0' '\n' < ${ENV_OBJ_FILE_COPY}
+
+rm ${ENV_OBJ_FILE_COPY}
+
+exit 0
-- 
2.1.4

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[U-Boot] [PATCHv2] scripts: Add script to extract default environment

[Lukasz Majewski]

This script looks for env_common.o object file and extracts from it default
u-boot environment, which is afterwards printed on standard output.

Usage example:
get_default_envs.sh > u-boot-env-default.txt

The generated text file can be used as input for mkenvimage.

Signed-off-by: Lukasz Majewski 

---
Changes for v2:
- Sort uniquely entries
- Exclude env_common.o generated for SPL
---
 scripts/get_default_envs.sh | 34 ++
 1 file changed, 34 insertions(+)
 create mode 100755 scripts/get_default_envs.sh

diff --git a/scripts/get_default_envs.sh b/scripts/get_default_envs.sh
new file mode 100755
index 000..7955db6
--- /dev/null
+++ b/scripts/get_default_envs.sh
@@ -0,0 +1,34 @@
+#! /bin/bash
+#
+# Copyright (C) 2016, Lukasz Majewski 
+#
+# SPDX-License-Identifier:  GPL-2.0+
+#
+
+# This file extracts default envs from built u-boot
+# usage: get_default_envs.sh > u-boot-env-default.txt
+set -ue
+
+ENV_OBJ_FILE="env_common.o"
+ENV_OBJ_FILE_COPY="copy_${ENV_OBJ_FILE}"
+
+echoerr() { echo "$@" 1>&2; }
+
+path=$(readlink -f $0)
+env_obj_file_path=$(find ${path%/scripts*} -not -path "*/spl/*" \
+-name "${ENV_OBJ_FILE}")
+[ -z "${env_obj_file_path}" ] && \
+{ echoerr "File '${ENV_OBJ_FILE}' not found!"; exit 1; }
+
+cp ${env_obj_file_path} ${ENV_OBJ_FILE_COPY}
+
+# NOTE: objcopy saves its output to file passed in
+# (copy_env_common.o in this case)
+objcopy -O binary -j ".rodata.default_environment" ${ENV_OBJ_FILE_COPY}
+
+# Replace default '\0' with '\n' and sort entries
+tr '\0' '\n' < ${ENV_OBJ_FILE_COPY} | sort -u
+
+rm ${ENV_OBJ_FILE_COPY}
+
+exit 0
-- 
2.1.4

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Re: [U-Boot] [PATCH] Revert "image-fit: switch ENOLINK to ENOENT"

[Jonathan Gray]

On Fri, Sep 16, 2016 at 10:21:43PM +0100, Paul Burton wrote:
> Commit bac17b78dace ("image-fit: switch ENOLINK to ENOENT") changed
> fit_get_node_from_config to return -ENOENT when a property doesn't
> exist, but didn't change any of its callers which check return values.
> Notably it didn't change boot_get_ramdisk, which leads to U-Boot failing
> to boot FIT images which don't include ramdisks with the following
> message:
> 
>   Ramdisk image is corrupt or invalid
> 
> The offending commit seems to dislike ENOLINK due to it not existing on
> OpenBSD, but I'm not sure why that matters as we define it in
> include/asm-generic/errno.h anyway so simply revert the commit to fix
> FIT image handling.

That header is not used when building native tools.
So reverting it will break the build of u-boot on OpenBSD.

  WRAPtools/common/image-fit.c
  HOSTCC  tools/common/image-fit.o
In file included from tools/common/image-fit.c:1:
/usr/users/jsg/src/u-boot/tools/../common/image-fit.c: In function 
'fit_get_node_from_config':
/usr/users/jsg/src/u-boot/tools/../common/image-fit.c:1569: error: 'ENOLINK' 
undeclared (first use in this function)
/usr/users/jsg/src/u-boot/tools/../common/image-fit.c:1569: error: (Each 
undeclared identifier is reported only once
/usr/users/jsg/src/u-boot/tools/../common/image-fit.c:1569: error: for each 
function it appears in.)

> 
> This reverts commit bac17b78dace ("image-fit: switch ENOLINK to
> ENOENT").
> 
> Signed-off-by: Paul Burton 
> Cc: Jonathan Gray 
> 
> ---
> 
>  common/image-fit.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/common/image-fit.c b/common/image-fit.c
> index 9ce68f1..f833fe3 100644
> --- a/common/image-fit.c
> +++ b/common/image-fit.c
> @@ -1566,7 +1566,7 @@ int fit_get_node_from_config(bootm_headers_t *images, 
> const char *prop_name,
>   noffset = fit_conf_get_prop_node(fit_hdr, cfg_noffset, prop_name);
>   if (noffset < 0) {
>   debug("*  %s: no '%s' in config\n", prop_name, prop_name);
> - return -ENOENT;
> + return -ENOLINK;
>   }
>  
>   return noffset;
> -- 
> 2.9.3
> 
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Re: [U-Boot] [PATCH 21/21] arm: imx: add i.MX6ULL 14x14 EVK board support

[Fabio Estevam]

On Thu, Sep 15, 2016 at 5:48 PM, Jagan Teki  wrote:

> OK, and I ran imx6 ddr calibration stress test[1] but observed data
> abort. the objdump doesn't show any of these address, can you please
> help me how can I proceed further?
>
> icorem6qdl> fatload mmc 0:1 0x1000 ddr-stress-test-mx6dq.bin
> reading ddr-stress-test-mx6dq.bin
> 87520 bytes read in 26 ms (3.2 MiB/s)
> icorem6qdl> go 0x1000

This is wrong. You cannot run this code from DDR. You should run from
internal RAM instead.

>From https://community.nxp.com/docs/DOC-105652:

"When download DDR Stress Tool by uboot, please copy the
ddr-test-uboot-jtag-mx???.bin to SD card and load it to IRAM by
'fatload' uboot command. For i.MX6, please load the binary to
0x00907000. For i.MX7D, please load the binary to 0x0091"
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[U-Boot] [PATCH 7/7] ext4: Revert rejection of 64bit enabled ext4 fs

[Stefan Brüns]

Enable mounting of ext4 fs with 64bit feature, as it is supported now.
These had been disabled in 6f94ab6656ceffb3f2a972c8de4c554502b6f2b7.

Signed-off-by: Stefan Brüns 
---
 fs/ext4/ext4_common.c | 9 -
 1 file changed, 9 deletions(-)

diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
index 61c4d19..bd81744 100644
--- a/fs/ext4/ext4_common.c
+++ b/fs/ext4/ext4_common.c
@@ -2337,15 +2337,6 @@ int ext4fs_mount(unsigned part_length)
if (le16_to_cpu(data->sblock.magic) != EXT2_MAGIC)
goto fail;
 
-   /*
-* The 64bit feature was enabled when metadata_csum was enabled
-* and we do not support metadata_csum (and cannot reliably find
-* files when it is set.  Refuse to mount.
-*/
-   if (le32_to_cpu(data->sblock.feature_incompat) & 
EXT4_FEATURE_INCOMPAT_64BIT) {
-   printf("Unsupported feature found (64bit, possibly 
metadata_csum), not mounting\n");
-   goto fail;
-   }
 
if (le32_to_cpu(data->sblock.revision_level) == 0) {
fs->inodesz = 128;
-- 
2.10.0

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[U-Boot] [PATCH 5/7] ext4: Use helper function to access group descriptor and its fields

[Stefan Brüns]

The descriptor size is variable, thus array indices are not generically
applicable. The larger group descriptors also contain e.g. high parts
of block numbers, which have to be read and written.

Signed-off-by: Stefan Brüns 
---
 fs/ext4/ext4_common.c | 125 --
 fs/ext4/ext4_write.c  | 165 +++---
 include/ext4fs.h  |   1 -
 3 files changed, 154 insertions(+), 137 deletions(-)

diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
index 24610ca..0c2ac47 100644
--- a/fs/ext4/ext4_common.c
+++ b/fs/ext4/ext4_common.c
@@ -391,7 +391,7 @@ uint16_t ext4fs_checksum_update(uint32_t i)
uint16_t crc = 0;
__le32 le32_i = cpu_to_le32(i);
 
-   desc = (struct ext2_block_group *)>bgd[i];
+   desc = ext4fs_get_group_descriptor(fs, i);
if (le32_to_cpu(fs->sb->feature_ro_compat) & 
EXT4_FEATURE_RO_COMPAT_GDT_CSUM) {
int offset = offsetof(struct ext2_block_group, bg_checksum);
 
@@ -931,39 +931,41 @@ uint32_t ext4fs_get_new_blk_no(void)
char *zero_buffer = zalloc(fs->blksz);
if (!journal_buffer || !zero_buffer)
goto fail;
-   struct ext2_block_group *bgd = (struct ext2_block_group *)fs->gdtable;
 
if (fs->first_pass_bbmap == 0) {
for (i = 0; i < fs->no_blkgrp; i++) {
-   if (le16_to_cpu(bgd[i].free_blocks)) {
-   if (le16_to_cpu(bgd[i].bg_flags) & 
EXT4_BG_BLOCK_UNINIT) {
-   uint16_t new_flags;
-   
put_ext4((uint64_t)le32_to_cpu(bgd[i].block_id) * fs->blksz,
-zero_buffer, fs->blksz);
-   new_flags = 
le16_to_cpu(bgd[i].bg_flags) & ~EXT4_BG_BLOCK_UNINIT;
-   bgd[i].bg_flags = 
cpu_to_le16(new_flags);
+   struct ext2_block_group *bgd = NULL;
+   bgd = ext4fs_get_group_descriptor(fs, i);
+   if (ext4fs_bg_get_free_blocks(bgd, fs)) {
+   uint16_t bg_flags = ext4fs_bg_get_flags(bgd);
+   uint64_t b_bitmap_blk =
+   ext4fs_bg_get_block_id(bgd, fs);
+   if (bg_flags & EXT4_BG_BLOCK_UNINIT) {
memcpy(fs->blk_bmaps[i], zero_buffer,
   fs->blksz);
+   put_ext4(b_bitmap_blk * fs->blksz,
+fs->blk_bmaps[i], fs->blksz);
+   bg_flags &= ~EXT4_BG_BLOCK_UNINIT;
+   ext4fs_bg_set_flags(bgd, bg_flags);
}
fs->curr_blkno =
_get_new_blk_no(fs->blk_bmaps[i]);
if (fs->curr_blkno == -1)
-   /* if block bitmap is completely fill */
+   /* block bitmap is completely filled */
continue;
fs->curr_blkno = fs->curr_blkno +
(i * fs->blksz * 8);
fs->first_pass_bbmap++;
-   ext4fs_bg_free_blocks_dec([i]);
+   ext4fs_bg_free_blocks_dec(bgd);
ext4fs_sb_free_blocks_dec(fs->sb);
-   status = ext4fs_devread(
-   
(lbaint_t)le32_to_cpu(bgd[i].block_id) *
-   fs->sect_perblk, 0,
-   fs->blksz,
+   status = ext4fs_devread(b_bitmap_blk *
+   fs->sect_perblk,
+   0, fs->blksz,
journal_buffer);
if (status == 0)
goto fail;
if (ext4fs_log_journal(journal_buffer,
-   
le32_to_cpu(bgd[i].block_id)))
+  b_bitmap_blk))
goto fail;
goto success;
} else {
@@ -990,7 +992,9 @@ restart:
if (bg_idx >= fs->no_blkgrp)
goto fail;
 
-   if (bgd[bg_idx].free_blocks == 0) {
+   struct ext2_block_group *bgd = NULL;
+   bgd = 

[U-Boot] [PATCH 1/7] ext4: Update ext2/3/4 superblock, group descriptor and inode structures

[Stefan Brüns]

Most importantly, the superblock provides the used group descriptor size,
which is required for the EXT4_FEATURE_INCOMPAT_64BIT.

Signed-off-by: Stefan Brüns 
---
 include/ext_common.h | 50 ++
 1 file changed, 46 insertions(+), 4 deletions(-)

diff --git a/include/ext_common.h b/include/ext_common.h
index 25216ca..07b61fa 100644
--- a/include/ext_common.h
+++ b/include/ext_common.h
@@ -99,6 +99,33 @@ struct ext2_sblock {
char volume_name[16];
char last_mounted_on[64];
__le32 compression_info;
+   uint8_t prealloc_blocks;
+   uint8_t prealloc_dir_blocks;
+   __le16 reserved_gdt_blocks;
+   uint8_t journal_uuid[16];
+   __le32 journal_inode;
+   __le32 journal_dev;
+   __le32 last_orphan;
+   __le32 hash_seed[4];
+   uint8_t default_hash_version;
+   uint8_t journal_backup_type;
+   __le16 descriptor_size;
+   __le32 default_mount_options;
+   __le32 first_meta_block_group;
+   __le32 mkfs_time;
+   __le32 journal_blocks[17];
+   __le32 total_blocks_high;
+   __le32 reserved_blocks_high;
+   __le32 free_blocks_high;
+   __le16 min_extra_inode_size;
+   __le16 want_extra_inode_size;
+   __le32 flags;
+   __le16 raid_stride;
+   __le16 mmp_interval;
+   __le64 mmp_block;
+   __le32 raid_stripe_width;
+   uint8_t log2_groups_per_flex;
+   uint8_t checksum_type;
 };
 
 struct ext2_block_group {
@@ -109,9 +136,23 @@ struct ext2_block_group {
__le16 free_inodes; /* Free inodes count */
__le16 used_dir_cnt;/* Directories count */
__le16 bg_flags;
-   __le32 bg_reserved[2];
+   __le32 bg_exclude_bitmap;
+   __le16 bg_block_id_csum;
+   __le16 bg_inode_id_csum;
__le16 bg_itable_unused; /* Unused inodes count */
-   __le16 bg_checksum; /* crc16(s_uuid+grouo_num+group_desc)*/
+   __le16 bg_checksum; /* crc16(s_uuid+group_num+group_desc)*/
+   /* following fields only exist if descriptor size is 64 */
+   __le32 block_id_high;
+   __le32 inode_id_high;
+   __le32 inode_table_id_high;
+   __le16 free_blocks_high;
+   __le16 free_inodes_high;
+   __le16 used_dir_cnt_high;
+   __le16 bg_itable_unused_high;
+   __le32 bg_exclude_bitmap_high;
+   __le16 bg_block_id_csum_high;
+   __le16 bg_inode_id_csum_high;
+   __le32 bg_reserved;
 };
 
 /* The ext2 inode. */
@@ -125,7 +166,7 @@ struct ext2_inode {
__le32 dtime;
__le16 gid;
__le16 nlinks;
-   __le32 blockcnt;/* Blocks of 512 bytes!! */
+   __le32 blockcnt;/* Blocks of either 512 or block_size bytes */
__le32 flags;
__le32 osd1;
union {
@@ -136,10 +177,11 @@ struct ext2_inode {
__le32 triple_indir_block;
} blocks;
char symlink[60];
+   char inline_data[60];
} b;
__le32 version;
__le32 acl;
-   __le32 dir_acl;
+   __le32 size_high;   /* previously dir_acl, but never used */
__le32 fragment_addr;
__le32 osd2[3];
 };
-- 
2.10.0

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[U-Boot] [PATCH 6/7] ext4: Respect group descriptor size when adjusting free counts

[Stefan Brüns]

Also adjust high 16/32 bits when free inode/block counts are modified.

Signed-off-by: Stefan Brüns 
---
 fs/ext4/ext4_common.c | 53 +++
 fs/ext4/ext4_write.c  | 40 ++
 2 files changed, 69 insertions(+), 24 deletions(-)

diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
index 0c2ac47..61c4d19 100644
--- a/fs/ext4/ext4_common.c
+++ b/fs/ext4/ext4_common.c
@@ -58,24 +58,53 @@ static inline void ext4fs_sb_free_inodes_dec(struct 
ext2_sblock *sb)
sb->free_inodes = cpu_to_le32(le32_to_cpu(sb->free_inodes) - 1);
 }
 
-static inline void ext4fs_bg_free_inodes_dec(struct ext2_block_group *bg)
+static inline void ext4fs_bg_free_inodes_dec
+   (struct ext2_block_group *bg, const struct ext_filesystem *fs)
 {
-   bg->free_inodes = cpu_to_le16(le16_to_cpu(bg->free_inodes) - 1);
+   uint32_t free_inodes = le16_to_cpu(bg->free_inodes);
+   if (fs->gdsize == 64)
+   free_inodes += le16_to_cpu(bg->free_inodes_high) << 16;
+   free_inodes--;
+
+   bg->free_inodes = cpu_to_le16(free_inodes & 0x);
+   if (fs->gdsize == 64)
+   bg->free_inodes_high = cpu_to_le16(free_inodes >> 16);
 }
 
-static inline void ext4fs_bg_free_blocks_dec(struct ext2_block_group *bg)
+static inline void ext4fs_bg_free_blocks_dec
+   (struct ext2_block_group *bg, const struct ext_filesystem *fs)
 {
-   bg->free_blocks = cpu_to_le16(le16_to_cpu(bg->free_blocks) - 1);
+   uint32_t free_blocks = le16_to_cpu(bg->free_blocks);
+   if (fs->gdsize == 64)
+   free_blocks += le16_to_cpu(bg->free_blocks_high) << 16;
+   free_blocks--;
+
+   bg->free_blocks = cpu_to_le16(free_blocks & 0x);
+   if (fs->gdsize == 64)
+   bg->free_blocks_high = cpu_to_le16(free_blocks >> 16);
 }
 
 static inline void ext4fs_sb_free_blocks_dec(struct ext2_sblock *sb)
 {
-   sb->free_blocks = cpu_to_le32(le32_to_cpu(sb->free_blocks) - 1);
+   uint64_t free_blocks = le32_to_cpu(sb->free_blocks);
+   free_blocks += (uint64_t)le32_to_cpu(sb->free_blocks_high) << 32;
+   free_blocks--;
+
+   sb->free_blocks = cpu_to_le32(free_blocks & 0x);
+   sb->free_blocks_high = cpu_to_le16(free_blocks >> 32);
 }
 
-static inline void ext4fs_bg_itable_unused_dec(struct ext2_block_group *bg)
+static inline void ext4fs_bg_itable_unused_dec
+   (struct ext2_block_group *bg, const struct ext_filesystem *fs)
 {
-   bg->bg_itable_unused = cpu_to_le16(le16_to_cpu(bg->bg_itable_unused) - 
1);
+   uint32_t free_inodes = le16_to_cpu(bg->bg_itable_unused);
+   if (fs->gdsize == 64)
+   free_inodes += le16_to_cpu(bg->bg_itable_unused_high) << 16;
+   free_inodes--;
+
+   bg->bg_itable_unused = cpu_to_le16(free_inodes & 0x);
+   if (fs->gdsize == 64)
+   bg->bg_itable_unused_high = cpu_to_le16(free_inodes >> 16);
 }
 
 uint64_t ext4fs_sb_get_free_blocks(const struct ext2_sblock *sb)
@@ -956,7 +985,7 @@ uint32_t ext4fs_get_new_blk_no(void)
fs->curr_blkno = fs->curr_blkno +
(i * fs->blksz * 8);
fs->first_pass_bbmap++;
-   ext4fs_bg_free_blocks_dec(bgd);
+   ext4fs_bg_free_blocks_dec(bgd, fs);
ext4fs_sb_free_blocks_dec(fs->sb);
status = ext4fs_devread(b_bitmap_blk *
fs->sect_perblk,
@@ -1031,7 +1060,7 @@ restart:
 
prev_bg_bitmap_index = bg_idx;
}
-   ext4fs_bg_free_blocks_dec(bgd);
+   ext4fs_bg_free_blocks_dec(bgd, fs);
ext4fs_sb_free_blocks_dec(fs->sb);
goto success;
}
@@ -1090,9 +1119,9 @@ int ext4fs_get_new_inode_no(void)
fs->curr_inode_no = fs->curr_inode_no +
(i * inodes_per_grp);
fs->first_pass_ibmap++;
-   ext4fs_bg_free_inodes_dec(bgd);
+   ext4fs_bg_free_inodes_dec(bgd, fs);
if (has_gdt_chksum)
-   ext4fs_bg_itable_unused_dec(bgd);
+   ext4fs_bg_itable_unused_dec(bgd, fs);
ext4fs_sb_free_inodes_dec(fs->sb);
status = ext4fs_devread(i_bitmap_blk *
fs->sect_perblk,
@@ -1146,7 +1175,7 @@ restart:
goto fail;
prev_inode_bitmap_index = ibmap_idx;
}
-   ext4fs_bg_free_inodes_dec(bgd);
+   

[U-Boot] [PATCH 3/7] ext4: Add helper functions for block group descriptor field access

[Stefan Brüns]

The helper functions encapsulate access of the block group descriptors,
independent of group descriptor size. The helpers also deal with the
endianess of the fields, and with split fields like free_blocks/
free_blocks_high.

Signed-off-by: Stefan Brüns 
---
 fs/ext4/ext4_common.c | 80 +++
 fs/ext4/ext4_common.h | 12 
 2 files changed, 92 insertions(+)

diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
index 416a9db..9e5bca0 100644
--- a/fs/ext4/ext4_common.c
+++ b/fs/ext4/ext4_common.c
@@ -47,6 +47,12 @@ struct ext2_inode *g_parent_inode;
 static int symlinknest;
 
 #if defined(CONFIG_EXT4_WRITE)
+struct ext2_block_group *ext4fs_get_group_descriptor
+   (const struct ext_filesystem *fs, uint32_t bg_idx)
+{
+   return (struct ext2_block_group *)(fs->gdtable + (bg_idx * fs->gdsize));
+}
+
 static inline void ext4fs_sb_free_inodes_dec(struct ext2_sblock *sb)
 {
sb->free_inodes = cpu_to_le32(le32_to_cpu(sb->free_inodes) - 1);
@@ -72,6 +78,80 @@ static inline void ext4fs_bg_itable_unused_dec(struct 
ext2_block_group *bg)
bg->bg_itable_unused = cpu_to_le16(le16_to_cpu(bg->bg_itable_unused) - 
1);
 }
 
+uint64_t ext4fs_sb_get_free_blocks(const struct ext2_sblock *sb)
+{
+   uint64_t free_blocks = le32_to_cpu(sb->free_blocks);
+   free_blocks += (uint64_t)le32_to_cpu(sb->free_blocks_high) << 32;
+   return free_blocks;
+}
+
+void ext4fs_sb_set_free_blocks(struct ext2_sblock *sb, uint64_t free_blocks)
+{
+   sb->free_blocks = cpu_to_le32(free_blocks & 0x);
+   sb->free_blocks_high = cpu_to_le16(free_blocks >> 32);
+}
+
+uint32_t ext4fs_bg_get_free_blocks(const struct ext2_block_group *bg,
+  const struct ext_filesystem *fs)
+{
+   uint32_t free_blocks = le16_to_cpu(bg->free_blocks);
+   if (fs->gdsize == 64)
+   free_blocks += le16_to_cpu(bg->free_blocks_high) << 16;
+   return free_blocks;
+}
+
+static inline
+uint32_t ext4fs_bg_get_free_inodes(const struct ext2_block_group *bg,
+  const struct ext_filesystem *fs)
+{
+   uint32_t free_inodes = le16_to_cpu(bg->free_inodes);
+   if (fs->gdsize == 64)
+   free_inodes += le16_to_cpu(bg->free_inodes_high) << 16;
+   return free_inodes;
+}
+
+static inline uint16_t ext4fs_bg_get_flags(const struct ext2_block_group *bg)
+{
+   return le16_to_cpu(bg->bg_flags);
+}
+
+static inline void ext4fs_bg_set_flags(struct ext2_block_group *bg,
+  uint16_t flags)
+{
+   bg->bg_flags = cpu_to_le16(flags);
+}
+
+/* Block number of the block bitmap */
+uint64_t ext4fs_bg_get_block_id(const struct ext2_block_group *bg,
+   const struct ext_filesystem *fs)
+{
+   uint64_t block_nr = le32_to_cpu(bg->block_id);
+   if (fs->gdsize == 64)
+   block_nr += (uint64_t)le32_to_cpu(bg->block_id_high) << 32;
+   return block_nr;
+}
+
+/* Block number of the inode bitmap */
+uint64_t ext4fs_bg_get_inode_id(const struct ext2_block_group *bg,
+   const struct ext_filesystem *fs)
+{
+   uint64_t block_nr = le32_to_cpu(bg->inode_id);
+   if (fs->gdsize == 64)
+   block_nr += (uint64_t)le32_to_cpu(bg->inode_id_high) << 32;
+   return block_nr;
+}
+
+/* Block number of the inode table */
+uint64_t ext4fs_bg_get_inode_table_id(const struct ext2_block_group *bg,
+ const struct ext_filesystem *fs)
+{
+   uint64_t block_nr = le32_to_cpu(bg->inode_table_id);
+   if (fs->gdsize == 64)
+   block_nr +=
+   (uint64_t)le32_to_cpu(bg->inode_table_id_high) << 32;
+   return block_nr;
+}
+
 uint32_t ext4fs_div_roundup(uint32_t size, uint32_t n)
 {
uint32_t res = size / n;
diff --git a/fs/ext4/ext4_common.h b/fs/ext4/ext4_common.h
index cc9d0c5..99d49e6 100644
--- a/fs/ext4/ext4_common.h
+++ b/fs/ext4/ext4_common.h
@@ -74,5 +74,17 @@ void ext4fs_allocate_blocks(struct ext2_inode *file_inode,
unsigned int total_remaining_blocks,
unsigned int *total_no_of_block);
 void put_ext4(uint64_t off, void *buf, uint32_t size);
+struct ext2_block_group *ext4fs_get_group_descriptor
+   (const struct ext_filesystem *fs, uint32_t bg_idx);
+uint64_t ext4fs_bg_get_block_id(const struct ext2_block_group *bg,
+   const struct ext_filesystem *fs);
+uint64_t ext4fs_bg_get_inode_id(const struct ext2_block_group *bg,
+   const struct ext_filesystem *fs);
+uint64_t ext4fs_bg_get_inode_table_id(const struct ext2_block_group *bg,
+   const struct ext_filesystem *fs);
+uint64_t ext4fs_sb_get_free_blocks(const struct ext2_sblock *sb);
+void ext4fs_sb_set_free_blocks(struct ext2_sblock *sb, uint64_t free_blocks);
+uint32_t ext4fs_bg_get_free_blocks(const struct ext2_block_group *bg,

[U-Boot] [PATCH 0/7] Add support for ext4 with enabled 64bit feature

[Stefan Brüns]

The EXT4_FEATURE_INCOMPAT_64BIT changes the on disk layout. Use the
correct structure sizes/offsets and respect split high/low free
inode/block counts.

Stefan Brüns (7):
  ext4: Update ext2/3/4 superblock, group descriptor and inode
structures
  ext4: determine group descriptor size for 64bit feature
  ext4: Add helper functions for block group descriptor field access
  ext4: Use correct descriptor size when reading the block group
descriptor
  ext4: Use helper function to access group descriptor and its fields
  ext4: Respect group descriptor size when adjusting free counts
  ext4: Revert rejection of 64bit enabled ext4 fs

 fs/ext4/ext4_common.c | 283 +++---
 fs/ext4/ext4_common.h |  12 +++
 fs/ext4/ext4_write.c  | 189 +++--
 include/ext4fs.h  |   3 +-
 include/ext_common.h  |  50 -
 5 files changed, 368 insertions(+), 169 deletions(-)

-- 
2.10.0

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[U-Boot] [PATCH 2/7] ext4: determine group descriptor size for 64bit feature

[Stefan Brüns]

If EXT4_FEATURE_INCOMPAT_64BIT is set, the descriptor can be read from
the superblocks, otherwise it defaults to 32.

Signed-off-by: Stefan Brüns 
---
 fs/ext4/ext4_common.c | 18 ++
 include/ext4fs.h  |  2 ++
 2 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
index a78b0b8..416a9db 100644
--- a/fs/ext4/ext4_common.c
+++ b/fs/ext4/ext4_common.c
@@ -2233,13 +2233,23 @@ int ext4fs_mount(unsigned part_length)
goto fail;
}
 
-   if (le32_to_cpu(data->sblock.revision_level) == 0)
+   if (le32_to_cpu(data->sblock.revision_level) == 0) {
fs->inodesz = 128;
-   else
+   } else {
+   debug("EXT4 features COMPAT: %08x INCOMPAT: %08x RO_COMPAT: 
%08x\n",
+ __le32_to_cpu(data->sblock.feature_compatibility),
+ __le32_to_cpu(data->sblock.feature_incompat),
+ __le32_to_cpu(data->sblock.feature_ro_compat));
+
fs->inodesz = le16_to_cpu(data->sblock.inode_size);
+   fs->gdsize = le32_to_cpu(data->sblock.feature_incompat) &
+   EXT4_FEATURE_INCOMPAT_64BIT ?
+   le16_to_cpu(data->sblock.descriptor_size) : 32;
+   }
 
-   debug("EXT2 rev %d, inode_size %d\n",
-  le32_to_cpu(data->sblock.revision_level), fs->inodesz);
+   debug("EXT2 rev %d, inode_size %d, descriptor size %d\n",
+ le32_to_cpu(data->sblock.revision_level),
+ fs->inodesz, fs->gdsize);
 
data->diropen.data = data;
data->diropen.ino = 2;
diff --git a/include/ext4fs.h b/include/ext4fs.h
index 6e31c73..7e1ee6c 100644
--- a/include/ext4fs.h
+++ b/include/ext4fs.h
@@ -87,6 +87,8 @@ struct ext_filesystem {
uint32_t inodesz;
/* Sectors per Block */
uint32_t sect_perblk;
+   /* Group Descriptor size */
+   uint16_t gdsize;
/* Group Descriptor Block Number */
uint32_t gdtable_blkno;
/* Total block groups of partition */
-- 
2.10.0

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[U-Boot] [PATCH 4/7] ext4: Use correct descriptor size when reading the block group descriptor

[Stefan Brüns]

The correct descriptor size must be used when calculating offsets, and
also to read the correct amount of data.

Signed-off-by: Stefan Brüns 
---
 fs/ext4/ext4_common.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
index 9e5bca0..24610ca 100644
--- a/fs/ext4/ext4_common.c
+++ b/fs/ext4/ext4_common.c
@@ -1525,20 +1525,20 @@ static int ext4fs_blockgroup
long int blkno;
unsigned int blkoff, desc_per_blk;
int log2blksz = get_fs()->dev_desc->log2blksz;
+   int desc_size = get_fs()->gdsize;
 
-   desc_per_blk = EXT2_BLOCK_SIZE(data) / sizeof(struct ext2_block_group);
+   desc_per_blk = EXT2_BLOCK_SIZE(data) / desc_size;
 
blkno = le32_to_cpu(data->sblock.first_data_block) + 1 +
group / desc_per_blk;
-   blkoff = (group % desc_per_blk) * sizeof(struct ext2_block_group);
+   blkoff = (group % desc_per_blk) * desc_size;
 
debug("ext4fs read %d group descriptor (blkno %ld blkoff %u)\n",
  group, blkno, blkoff);
 
return ext4fs_devread((lbaint_t)blkno <<
  (LOG2_BLOCK_SIZE(data) - log2blksz),
- blkoff, sizeof(struct ext2_block_group),
- (char *)blkgrp);
+ blkoff, desc_size, (char *)blkgrp);
 }
 
 int ext4fs_read_inode(struct ext2_data *data, int ino, struct ext2_inode 
*inode)
-- 
2.10.0

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[U-Boot] [PATCH] Revert "image-fit: switch ENOLINK to ENOENT"

[Paul Burton]

Commit bac17b78dace ("image-fit: switch ENOLINK to ENOENT") changed
fit_get_node_from_config to return -ENOENT when a property doesn't
exist, but didn't change any of its callers which check return values.
Notably it didn't change boot_get_ramdisk, which leads to U-Boot failing
to boot FIT images which don't include ramdisks with the following
message:

  Ramdisk image is corrupt or invalid

The offending commit seems to dislike ENOLINK due to it not existing on
OpenBSD, but I'm not sure why that matters as we define it in
include/asm-generic/errno.h anyway so simply revert the commit to fix
FIT image handling.

This reverts commit bac17b78dace ("image-fit: switch ENOLINK to
ENOENT").

Signed-off-by: Paul Burton 
Cc: Jonathan Gray 

---

 common/image-fit.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/image-fit.c b/common/image-fit.c
index 9ce68f1..f833fe3 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -1566,7 +1566,7 @@ int fit_get_node_from_config(bootm_headers_t *images, 
const char *prop_name,
noffset = fit_conf_get_prop_node(fit_hdr, cfg_noffset, prop_name);
if (noffset < 0) {
debug("*  %s: no '%s' in config\n", prop_name, prop_name);
-   return -ENOENT;
+   return -ENOLINK;
}
 
return noffset;
-- 
2.9.3

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[U-Boot] [PATCH v2 16/17] arm: dts: imx6q: Add pinctrl defines

[Jagan Teki]

Add imx6q pinctrl defines support from Linux.

Cc: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 arch/arm/dts/imx6q-pinfunc.h | 1047 ++
 1 file changed, 1047 insertions(+)
 create mode 100644 arch/arm/dts/imx6q-pinfunc.h

diff --git a/arch/arm/dts/imx6q-pinfunc.h b/arch/arm/dts/imx6q-pinfunc.h
new file mode 100644
index 000..9fc6120
--- /dev/null
+++ b/arch/arm/dts/imx6q-pinfunc.h
@@ -0,0 +1,1047 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX6Q_PINFUNC_H
+#define __DTS_IMX6Q_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * 
+ */
+#define MX6QDL_PAD_SD2_DAT1__SD2_DATA1  0x04c 0x360 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
+#define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B  0x04c 0x360 0x000 0x2 0x0
+#define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS  0x04c 0x360 0x7c8 0x3 0x0
+#define MX6QDL_PAD_SD2_DAT1__KEY_COL7   0x04c 0x360 0x8f0 0x4 0x0
+#define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_DAT2__SD2_DATA2  0x050 0x364 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
+#define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B  0x050 0x364 0x000 0x2 0x0
+#define MX6QDL_PAD_SD2_DAT2__AUD4_TXD   0x050 0x364 0x7b8 0x3 0x0
+#define MX6QDL_PAD_SD2_DAT2__KEY_ROW6   0x050 0x364 0x8f8 0x4 0x0
+#define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x050 0x364 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_DAT0__SD2_DATA0  0x054 0x368 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_DAT0__ECSPI5_MISO0x054 0x368 0x82c 0x1 0x0
+#define MX6QDL_PAD_SD2_DAT0__AUD4_RXD   0x054 0x368 0x7b4 0x3 0x0
+#define MX6QDL_PAD_SD2_DAT0__KEY_ROW7   0x054 0x368 0x8fc 0x4 0x0
+#define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x054 0x368 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT  0x054 0x368 0x000 0x6 0x0
+#define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA   0x058 0x36c 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x058 0x36c 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x058 0x36c 0x918 0x2 0x0
+#define MX6QDL_PAD_RGMII_TXC__GPIO6_IO190x058 0x36c 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M   0x058 0x36c 0x000 0x7 0x0
+#define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY  0x05c 0x370 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x05c 0x370 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TD0__GPIO6_IO200x05c 0x370 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG   0x060 0x374 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x060 0x374 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TD1__GPIO6_IO210x060 0x374 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA   0x064 0x378 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x064 0x378 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TD2__GPIO6_IO220x064 0x378 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE   0x068 0x37c 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x068 0x37c 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TD3__GPIO6_IO230x068 0x37c 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA0x06c 0x380 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x06c 0x380 0x858 0x1 0x0
+#define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x06c 0x380 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY  0x070 0x384 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x070 0x384 0x848 0x1 0x0
+#define MX6QDL_PAD_RGMII_RD0__GPIO6_IO250x070 0x384 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE  0x074 0x388 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x074 0x388 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x074 0x388 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK   0x074 0x388 0x83c 0x7 0x0
+#define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG   0x078 0x38c 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x078 0x38c 0x84c 0x1 0x0
+#define MX6QDL_PAD_RGMII_RD1__GPIO6_IO270x078 0x38c 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_RD2__HSI_TX_DATA   0x07c 0x390 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x07c 0x390 0x850 0x1 0x0
+#define 

[U-Boot] [PATCH v2 17/17] arm: imx6q: Add devicetree support for Engicam i.CoreM6 Quad/Dual

[Jagan Teki]

i.CoreM6 Quad/Dual modules are system on module solutions
manufactured by Engicam with following characteristics:
CPU   NXP i.MX6 DQ, 800MHz
RAM   1GB, 32, 64 bit, DDR3-800/1066
NAND  SLC,512MB
Power supply  Single 5V
MAX LCD RES   FULLHD

and more info at
http://www.engicam.com/en/products/embedded/som/sodimm/i-core-m6s-dl-d-q

Cc: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 arch/arm/dts/Makefile|  3 ++-
 arch/arm/dts/imx6q-icore.dts | 59 
 board/engicam/icorem6/README |  9 ++-
 3 files changed, 69 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/dts/imx6q-icore.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 39c1d2c..376fc58 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -274,7 +274,8 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
 dtb-$(CONFIG_MX7) += imx7-colibri.dtb
 
 dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
-   imx6dl-icore.dtb
+   imx6dl-icore.dtb \
+   imx6q-icore.dtb
 
 dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \
k2l-evm.dtb \
diff --git a/arch/arm/dts/imx6q-icore.dts b/arch/arm/dts/imx6q-icore.dts
new file mode 100644
index 000..025f543
--- /dev/null
+++ b/arch/arm/dts/imx6q-icore.dts
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-icore.dtsi"
+
+/ {
+   model = "Engicam i.CoreM6 Quad/Dual Starter Kit";
+   compatible = "engicam,imx6-icore", "fsl,imx6q";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
diff --git a/board/engicam/icorem6/README b/board/engicam/icorem6/README
index 6fe7a3c..9ee01ca 100644
--- a/board/engicam/icorem6/README
+++ b/board/engicam/icorem6/README
@@ -1,12 +1,19 @@
 How to use U-Boot on Engicam i.CoreM6 DualLite/Solo and Quad/Dual Starter Kit:
 -
 
-- Build U-Boot for Engicam i.CoreM6 QDL:
+- Configure U-Boot for Engicam i.CoreM6 QDL:
 
 $ make mrproper
 $ make icorem6qdl_defconfig
+
+- Build for i.CoreM6 DualLite/Solo
+
 $ make
 
+- Build for i.CoreM6 Quad/Dual
+
+$ make DEVICE_TREE=imx6q-icore
+
 This will generate the SPL image called SPL and the u-boot-dtb.img.
 
 - Flash the SPL image into the micro SD card:
-- 
2.7.4

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[U-Boot] [PATCH v2 13/17] imx6q: icorem6: Enable pinctrl driver

[Jagan Teki]

Enable imx6 pinctrl driver support for i.CoreM6.

Cc: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 configs/imx6qdl_icore_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/imx6qdl_icore_defconfig b/configs/imx6qdl_icore_defconfig
index 9fbe974..20a8289 100644
--- a/configs/imx6qdl_icore_defconfig
+++ b/configs/imx6qdl_icore_defconfig
@@ -28,3 +28,5 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_LIBFDT=y
 CONFIG_MXC_UART=y
 CONFIG_IMX_THERMAL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
-- 
2.7.4

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[U-Boot] [PATCH v2 14/17] engicam: icorem6: Add DM_GPIO, DM_MMC support

[Jagan Teki]

Add DM_GPIO, DM_MMC support for u-boot and disable for SPL.

Cc: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 arch/arm/cpu/armv7/mx6/Kconfig  |   2 +
 board/engicam/icorem6/icorem6.c | 142 
 include/configs/imx6qdl_icore.h |   4 ++
 3 files changed, 78 insertions(+), 70 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index e2431a8..762a581 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -100,6 +100,8 @@ config TARGET_MX6Q_ICORE
select MX6QDL
select OF_CONTROL
select DM
+   select DM_GPIO
+   select DM_MMC
select DM_THERMAL
select SUPPORT_SPL
 
diff --git a/board/engicam/icorem6/icorem6.c b/board/engicam/icorem6/icorem6.c
index 4331ad3..2aa8a4e 100644
--- a/board/engicam/icorem6/icorem6.c
+++ b/board/engicam/icorem6/icorem6.c
@@ -7,8 +7,6 @@
  */
 
 #include 
-#include 
-#include 
 #include 
 #include 
 
@@ -29,10 +27,6 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |   \
PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
-   PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |   \
-   PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
 #define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |\
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   | \
PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
@@ -55,70 +49,6 @@ static iomux_v3_cfg_t const enet_pads[] = {
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 };
 
-static iomux_v3_cfg_t const usdhc1_pads[] = {
-   IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-   IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-   IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-   IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-   IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-   IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-   IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
-};
-
-#ifdef CONFIG_FSL_ESDHC
-#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
-
-struct fsl_esdhc_cfg usdhc_cfg[1] = {
-   {USDHC1_BASE_ADDR, 0, 4},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-   struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-   int ret = 0;
-
-   switch (cfg->esdhc_base) {
-   case USDHC1_BASE_ADDR:
-   ret = !gpio_get_value(USDHC1_CD_GPIO);
-   break;
-   }
-
-   return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
-   int i, ret;
-
-   /*
-   * According to the board_mmc_init() the following map is done:
-   * (U-boot device node)(Physical Port)
-   * mmc0  USDHC1
-   */
-   for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
-   switch (i) {
-   case 0:
-   SETUP_IOMUX_PADS(usdhc1_pads);
-   gpio_direction_input(USDHC1_CD_GPIO);
-   usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-   break;
-   default:
-   printf("Warning - USDHC%d controller not supporting\n",
-  i + 1);
-   return 0;
-   }
-
-   ret = fsl_esdhc_initialize(bis, _cfg[i]);
-   if (ret) {
-   printf("Warning: failed to initialize mmc dev %d\n", i);
-   return ret;
-   }
-   }
-
-   return 0;
-}
-#endif
-
 #ifdef CONFIG_FEC_MXC
 #define ENET_PHY_RST   IMX_GPIO_NR(7, 12)
 static int setup_fec(void)
@@ -200,6 +130,78 @@ int dram_init(void)
 #include 
 #include 
 
+/* MMC board initialization is needed till adding DM support in SPL */
+#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
+#include 
+#include 
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+   PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |   \
+   PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+   IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+   IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+   IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+   IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+   IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+   IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ 

[U-Boot] [PATCH v2 12/17] arm: imx6q: Add devicetree support for Engicam i.CoreM6 DualLite/Solo

[Jagan Teki]

i.CoreM6 DualLite/Solo modules are system on module solutions
manufactured by Engicam with following characteristics:
CPU   NXP i.MX6 DL, 800MHz
RAM   1GB, 32, 64 bit, DDR3-800/1066
NAND  SLC,512MB
Power supply  Single 5V
MAX LCD RES   FULLHD

and more info at
http://www.engicam.com/en/products/embedded/som/sodimm/i-core-m6s-dl-d-q

Cc: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 arch/arm/cpu/armv7/mx6/Kconfig  |   1 +
 arch/arm/dts/Makefile   |   3 +-
 arch/arm/dts/imx6dl-icore.dts   |  59 ++
 arch/arm/dts/imx6qdl-icore.dtsi | 234 
 board/engicam/icorem6/README|   6 +-
 configs/imx6qdl_icore_defconfig |   1 +
 6 files changed, 300 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/dts/imx6dl-icore.dts
 create mode 100644 arch/arm/dts/imx6qdl-icore.dtsi

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 5d549bd..e2431a8 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -98,6 +98,7 @@ config TARGET_MX6QARM2
 config TARGET_MX6Q_ICORE
bool "Support Engicam i.Core"
select MX6QDL
+   select OF_CONTROL
select DM
select DM_THERMAL
select SUPPORT_SPL
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 74d6ed2..39c1d2c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -273,7 +273,8 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
 
 dtb-$(CONFIG_MX7) += imx7-colibri.dtb
 
-dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb
+dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
+   imx6dl-icore.dtb
 
 dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \
k2l-evm.dtb \
diff --git a/arch/arm/dts/imx6dl-icore.dts b/arch/arm/dts/imx6dl-icore.dts
new file mode 100644
index 000..aec332c
--- /dev/null
+++ b/arch/arm/dts/imx6dl-icore.dts
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-icore.dtsi"
+
+/ {
+   model = "Engicam i.CoreM6 DualLite/Solo Starter Kit";
+   compatible = "engicam,imx6-icore", "fsl,imx6dl";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
diff --git a/arch/arm/dts/imx6qdl-icore.dtsi b/arch/arm/dts/imx6qdl-icore.dtsi
new file mode 100644
index 000..4e79858
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-icore.dtsi
@@ -0,0 +1,234 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * 

[U-Boot] [PATCH v2 15/17] arm: dts: Add devicetree for i.MX6Q

[Jagan Teki]

Add i.MX6Q dtsi support from Linux.

Cc: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 arch/arm/dts/imx6q.dtsi | 300 
 1 file changed, 300 insertions(+)
 create mode 100644 arch/arm/dts/imx6q.dtsi

diff --git a/arch/arm/dts/imx6q.dtsi b/arch/arm/dts/imx6q.dtsi
new file mode 100644
index 000..c30c836
--- /dev/null
+++ b/arch/arm/dts/imx6q.dtsi
@@ -0,0 +1,300 @@
+
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include 
+#include "imx6q-pinfunc.h"
+#include "imx6qdl.dtsi"
+
+/ {
+   aliases {
+   ipu1 = 
+   spi4 = 
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu0: cpu@0 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <0>;
+   next-level-cache = <>;
+   operating-points = <
+   /* kHzuV */
+   120 1275000
+   996000  125
+   852000  125
+   792000  1175000
+   396000  975000
+   >;
+   fsl,soc-operating-points = <
+   /* ARM kHz  SOC-PU uV */
+   120 1275000
+   996000  125
+   852000  125
+   792000  1175000
+   396000  1175000
+   >;
+   clock-latency = <61036>; /* two CLK32 periods */
+   clocks = < IMX6QDL_CLK_ARM>,
+< IMX6QDL_CLK_PLL2_PFD2_396M>,
+< IMX6QDL_CLK_STEP>,
+< IMX6QDL_CLK_PLL1_SW>,
+< IMX6QDL_CLK_PLL1_SYS>;
+   clock-names = "arm", "pll2_pfd2_396m", "step",
+ "pll1_sw", "pll1_sys";
+   arm-supply = <_arm>;
+   pu-supply = <_pu>;
+   soc-supply = <_soc>;
+   };
+
+   cpu@1 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <1>;
+   next-level-cache = <>;
+   };
+
+   cpu@2 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <2>;
+   next-level-cache = <>;
+   };
+
+   cpu@3 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <3>;
+   next-level-cache = <>;
+   };
+   };
+
+   soc {
+   ocram: sram@0090 {
+   compatible = "mmio-sram";
+   reg = <0x0090 0x4>;
+   clocks = < IMX6QDL_CLK_OCRAM>;
+   };
+
+   aips-bus@0200 { /* AIPS1 */
+   spba-bus@0200 {
+   ecspi5: ecspi@02018000 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "fsl,imx6q-ecspi", 
"fsl,imx51-ecspi";
+   reg = <0x02018000 0x4000>;
+   interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
+   clocks = < IMX6Q_CLK_ECSPI5>,
+< IMX6Q_CLK_ECSPI5>;
+   clock-names = "ipg", "per";
+   dmas = < 11 7 1>, < 12 7 2>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   };
+   };
+
+   iomuxc: iomuxc@020e {
+   compatible = "fsl,imx6q-iomuxc";
+   };
+   };
+
+   sata: sata@0220 {
+   compatible = "fsl,imx6q-ahci";
+   reg = <0x0220 0x4000>;
+   interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
+ 

[U-Boot] [PATCH v2 11/17] dt-bindings: clock: imx6qdl: Add clock defines

[Jagan Teki]

Add imx6qdl clock header defines support from Linux.

Cc: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 include/dt-bindings/clock/imx6qdl-clock.h | 274 ++
 1 file changed, 274 insertions(+)
 create mode 100644 include/dt-bindings/clock/imx6qdl-clock.h

diff --git a/include/dt-bindings/clock/imx6qdl-clock.h 
b/include/dt-bindings/clock/imx6qdl-clock.h
new file mode 100644
index 000..2905033
--- /dev/null
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -0,0 +1,274 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX6QDL_H
+#define __DT_BINDINGS_CLOCK_IMX6QDL_H
+
+#define IMX6QDL_CLK_DUMMY  0
+#define IMX6QDL_CLK_CKIL   1
+#define IMX6QDL_CLK_CKIH   2
+#define IMX6QDL_CLK_OSC3
+#define IMX6QDL_CLK_PLL2_PFD0_352M 4
+#define IMX6QDL_CLK_PLL2_PFD1_594M 5
+#define IMX6QDL_CLK_PLL2_PFD2_396M 6
+#define IMX6QDL_CLK_PLL3_PFD0_720M 7
+#define IMX6QDL_CLK_PLL3_PFD1_540M 8
+#define IMX6QDL_CLK_PLL3_PFD2_508M 9
+#define IMX6QDL_CLK_PLL3_PFD3_454M 10
+#define IMX6QDL_CLK_PLL2_198M  11
+#define IMX6QDL_CLK_PLL3_120M  12
+#define IMX6QDL_CLK_PLL3_80M   13
+#define IMX6QDL_CLK_PLL3_60M   14
+#define IMX6QDL_CLK_TWD15
+#define IMX6QDL_CLK_STEP   16
+#define IMX6QDL_CLK_PLL1_SW17
+#define IMX6QDL_CLK_PERIPH_PRE 18
+#define IMX6QDL_CLK_PERIPH2_PRE19
+#define IMX6QDL_CLK_PERIPH_CLK2_SEL20
+#define IMX6QDL_CLK_PERIPH2_CLK2_SEL   21
+#define IMX6QDL_CLK_AXI_SEL22
+#define IMX6QDL_CLK_ESAI_SEL   23
+#define IMX6QDL_CLK_ASRC_SEL   24
+#define IMX6QDL_CLK_SPDIF_SEL  25
+#define IMX6QDL_CLK_GPU2D_AXI  26
+#define IMX6QDL_CLK_GPU3D_AXI  27
+#define IMX6QDL_CLK_GPU2D_CORE_SEL 28
+#define IMX6QDL_CLK_GPU3D_CORE_SEL 29
+#define IMX6QDL_CLK_GPU3D_SHADER_SEL   30
+#define IMX6QDL_CLK_IPU1_SEL   31
+#define IMX6QDL_CLK_IPU2_SEL   32
+#define IMX6QDL_CLK_LDB_DI0_SEL33
+#define IMX6QDL_CLK_LDB_DI1_SEL34
+#define IMX6QDL_CLK_IPU1_DI0_PRE_SEL   35
+#define IMX6QDL_CLK_IPU1_DI1_PRE_SEL   36
+#define IMX6QDL_CLK_IPU2_DI0_PRE_SEL   37
+#define IMX6QDL_CLK_IPU2_DI1_PRE_SEL   38
+#define IMX6QDL_CLK_IPU1_DI0_SEL   39
+#define IMX6QDL_CLK_IPU1_DI1_SEL   40
+#define IMX6QDL_CLK_IPU2_DI0_SEL   41
+#define IMX6QDL_CLK_IPU2_DI1_SEL   42
+#define IMX6QDL_CLK_HSI_TX_SEL 43
+#define IMX6QDL_CLK_PCIE_AXI_SEL   44
+#define IMX6QDL_CLK_SSI1_SEL   45
+#define IMX6QDL_CLK_SSI2_SEL   46
+#define IMX6QDL_CLK_SSI3_SEL   47
+#define IMX6QDL_CLK_USDHC1_SEL 48
+#define IMX6QDL_CLK_USDHC2_SEL 49
+#define IMX6QDL_CLK_USDHC3_SEL 50
+#define IMX6QDL_CLK_USDHC4_SEL 51
+#define IMX6QDL_CLK_ENFC_SEL   52
+#define IMX6QDL_CLK_EIM_SEL53
+#define IMX6QDL_CLK_EIM_SLOW_SEL   54
+#define IMX6QDL_CLK_VDO_AXI_SEL55
+#define IMX6QDL_CLK_VPU_AXI_SEL56
+#define IMX6QDL_CLK_CKO1_SEL   57
+#define IMX6QDL_CLK_PERIPH 58
+#define IMX6QDL_CLK_PERIPH259
+#define IMX6QDL_CLK_PERIPH_CLK260
+#define IMX6QDL_CLK_PERIPH2_CLK2   61
+#define IMX6QDL_CLK_IPG62
+#define IMX6QDL_CLK_IPG_PER63
+#define IMX6QDL_CLK_ESAI_PRED  64
+#define IMX6QDL_CLK_ESAI_PODF  65
+#define IMX6QDL_CLK_ASRC_PRED  66
+#define IMX6QDL_CLK_ASRC_PODF  67
+#define IMX6QDL_CLK_SPDIF_PRED 68
+#define IMX6QDL_CLK_SPDIF_PODF 69
+#define IMX6QDL_CLK_CAN_ROOT   70
+#define IMX6QDL_CLK_ECSPI_ROOT 71
+#define IMX6QDL_CLK_GPU2D_CORE_PODF72
+#define IMX6QDL_CLK_GPU3D_CORE_PODF73
+#define IMX6QDL_CLK_GPU3D_SHADER   74
+#define IMX6QDL_CLK_IPU1_PODF  75

[U-Boot] [PATCH v2 08/17] arm: dts: Add devicetree for i.MX6DL

[Jagan Teki]

Add i.MX6DL dtsi support from Linux.

Cc: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 arch/arm/dts/imx6dl.dtsi | 133 +++
 1 file changed, 133 insertions(+)
 create mode 100644 arch/arm/dts/imx6dl.dtsi

diff --git a/arch/arm/dts/imx6dl.dtsi b/arch/arm/dts/imx6dl.dtsi
new file mode 100644
index 000..9a4c22c
--- /dev/null
+++ b/arch/arm/dts/imx6dl.dtsi
@@ -0,0 +1,133 @@
+
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include 
+#include "imx6dl-pinfunc.h"
+#include "imx6qdl.dtsi"
+
+/ {
+   aliases {
+   i2c3 = 
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <0>;
+   next-level-cache = <>;
+   operating-points = <
+   /* kHzuV */
+   996000  125
+   792000  1175000
+   396000  115
+   >;
+   fsl,soc-operating-points = <
+   /* ARM kHz  SOC-PU uV */
+   996000  1175000
+   792000  1175000
+   396000  1175000
+   >;
+   clock-latency = <61036>; /* two CLK32 periods */
+   clocks = < IMX6QDL_CLK_ARM>,
+< IMX6QDL_CLK_PLL2_PFD2_396M>,
+< IMX6QDL_CLK_STEP>,
+< IMX6QDL_CLK_PLL1_SW>,
+< IMX6QDL_CLK_PLL1_SYS>;
+   clock-names = "arm", "pll2_pfd2_396m", "step",
+ "pll1_sw", "pll1_sys";
+   arm-supply = <_arm>;
+   pu-supply = <_pu>;
+   soc-supply = <_soc>;
+   };
+
+   cpu@1 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <1>;
+   next-level-cache = <>;
+   };
+   };
+
+   soc {
+   ocram: sram@0090 {
+   compatible = "mmio-sram";
+   reg = <0x0090 0x2>;
+   clocks = < IMX6QDL_CLK_OCRAM>;
+   };
+
+   aips1: aips-bus@0200 {
+   iomuxc: iomuxc@020e {
+   compatible = "fsl,imx6dl-iomuxc";
+   };
+
+   pxp: pxp@020f {
+   reg = <0x020f 0x4000>;
+   interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
+   };
+
+   epdc: epdc@020f4000 {
+   reg = <0x020f4000 0x4000>;
+   interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
+   };
+
+   lcdif: lcdif@020f8000 {
+   reg = <0x020f8000 0x4000>;
+   interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
+   };
+   };
+
+   aips2: aips-bus@0210 {
+   i2c4: i2c@021f8000 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
+   reg = <0x021f8000 0x4000>;
+   interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
+   clocks = < IMX6DL_CLK_I2C4>;
+   status = "disabled";
+   };
+   };
+   };
+
+   display-subsystem {
+   compatible = "fsl,imx-display-subsystem";
+   ports = <_di0>, <_di1>;
+   };
+
+   gpu-subsystem {
+   compatible = "fsl,imx-gpu-subsystem";
+   cores = <_2d>, <_3d>;
+   };
+};
+
+ {
+   compatible = "fsl,imx6dl-gpt";
+};
+
+ {
+   compatible = "fsl,imx6dl-hdmi";
+};
+
+ {
+   clocks = < IMX6QDL_CLK_LDB_DI0_SEL>, < 
IMX6QDL_CLK_LDB_DI1_SEL>,
+< IMX6QDL_CLK_IPU1_DI0_SEL>, < 
IMX6QDL_CLK_IPU1_DI1_SEL>,
+< IMX6QDL_CLK_LDB_DI0>, < IMX6QDL_CLK_LDB_DI1>;
+   clock-names = 

[U-Boot] [PATCH v2 10/17] arm: dts: imx6dl: Add pinctrl defines

[Jagan Teki]

Add imx6dl pinctrl defines support from Linux.

Cc: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 arch/arm/dts/imx6dl-pinfunc.h | 1091 +
 1 file changed, 1091 insertions(+)
 create mode 100644 arch/arm/dts/imx6dl-pinfunc.h

diff --git a/arch/arm/dts/imx6dl-pinfunc.h b/arch/arm/dts/imx6dl-pinfunc.h
new file mode 100644
index 000..0ead323
--- /dev/null
+++ b/arch/arm/dts/imx6dl-pinfunc.h
@@ -0,0 +1,1091 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX6DL_PINFUNC_H
+#define __DTS_IMX6DL_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * 
+ */
+#define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO  0x04c 0x360 0x7f8 0x2 0x0
+#define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA0x04c 0x360 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA0x04c 0x360 0x8fc 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28   0x04c 0x360 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07  0x04c 0x360 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS0x050 0x364 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0   0x050 0x364 0x800 0x2 0x0
+#define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA0x050 0x364 0x8fc 0x3 0x1
+#define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA0x050 0x364 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29   0x050 0x364 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08  0x050 0x364 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x054 0x368 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08   0x054 0x368 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA0x054 0x368 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA0x054 0x368 0x914 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30   0x054 0x368 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09  0x054 0x368 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x058 0x36c 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09   0x058 0x36c 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA0x058 0x36c 0x914 0x3 0x1
+#define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA0x058 0x36c 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31   0x058 0x36c 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10  0x058 0x36c 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x05c 0x370 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10   0x05c 0x370 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA0x05c 0x370 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA0x05c 0x370 0x91c 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00   0x05c 0x370 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11  0x05c 0x370 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x060 0x374 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11   0x060 0x374 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA0x060 0x374 0x91c 0x3 0x1
+#define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA0x060 0x374 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01   0x060 0x374 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12  0x060 0x374 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x064 0x378 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12   0x064 0x378 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B  0x064 0x378 0x910 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B  0x064 0x378 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02   0x064 0x378 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13  0x064 0x378 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x068 0x37c 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13   0x068 0x37c 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B  0x068 0x37c 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B  0x068 0x37c 0x910 0x3 0x1
+#define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03   0x068 0x37c 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14  0x068 0x37c 0x000 0x7 0x0

[U-Boot] [PATCH v2 09/17] arm: dts: Add devicetree for i.MX6DQL

[Jagan Teki]

Add i.MX6DQL dtsi support from Linux.

Cc: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 arch/arm/dts/imx6qdl.dtsi | 1281 +
 1 file changed, 1281 insertions(+)
 create mode 100644 arch/arm/dts/imx6qdl.dtsi

diff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi
new file mode 100644
index 000..b13b0b2
--- /dev/null
+++ b/arch/arm/dts/imx6qdl.dtsi
@@ -0,0 +1,1281 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include 
+#include 
+
+#include "skeleton.dtsi"
+
+/ {
+   aliases {
+   ethernet0 = 
+   can0 = 
+   can1 = 
+   gpio0 = 
+   gpio1 = 
+   gpio2 = 
+   gpio3 = 
+   gpio4 = 
+   gpio5 = 
+   gpio6 = 
+   i2c0 = 
+   i2c1 = 
+   i2c2 = 
+   ipu0 = 
+   mmc0 = 
+   mmc1 = 
+   mmc2 = 
+   mmc3 = 
+   serial0 = 
+   serial1 = 
+   serial2 = 
+   serial3 = 
+   serial4 = 
+   spi0 = 
+   spi1 = 
+   spi2 = 
+   spi3 = 
+   usbphy0 = 
+   usbphy1 = 
+   };
+
+   clocks {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ckil {
+   compatible = "fsl,imx-ckil", "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <32768>;
+   };
+
+   ckih1 {
+   compatible = "fsl,imx-ckih1", "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
+   };
+
+   osc {
+   compatible = "fsl,imx-osc", "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <2400>;
+   };
+   };
+
+   soc {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "simple-bus";
+   interrupt-parent = <>;
+   ranges;
+
+   dma_apbh: dma-apbh@0011 {
+   compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
+   reg = <0x0011 0x2000>;
+   interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
+<0 13 IRQ_TYPE_LEVEL_HIGH>,
+<0 13 IRQ_TYPE_LEVEL_HIGH>,
+<0 13 IRQ_TYPE_LEVEL_HIGH>;
+   interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
+   #dma-cells = <1>;
+   dma-channels = <4>;
+   clocks = < IMX6QDL_CLK_APBH_DMA>;
+   };
+
+   gpmi: gpmi-nand@00112000 {
+   compatible = "fsl,imx6q-gpmi-nand";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
+   reg-names = "gpmi-nand", "bch";
+   interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
+   interrupt-names = "bch";
+   clocks = < IMX6QDL_CLK_GPMI_IO>,
+< IMX6QDL_CLK_GPMI_APB>,
+< IMX6QDL_CLK_GPMI_BCH>,
+< IMX6QDL_CLK_GPMI_BCH_APB>,
+< IMX6QDL_CLK_PER1_BCH>;
+   clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
+ "gpmi_bch_apb", "per1_bch";
+   dmas = <_apbh 0>;
+   dma-names = "rx-tx";
+   status = "disabled";
+   };
+
+   hdmi: hdmi@012 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x0012 0x9000>;
+   interrupts = <0 115 0x04>;
+   gpr = <>;
+   clocks = < IMX6QDL_CLK_HDMI_IAHB>,
+< IMX6QDL_CLK_HDMI_ISFR>;
+   clock-names = "iahb", "isfr";
+   status = "disabled";
+
+   port@0 {
+ 

[U-Boot] [PATCH v2 06/17] imx6: icorem6: Add ENET support

[Jagan Teki]

Add enet support for engicam icorem6 qdl starter kit.
- Add pinmux settings
- Add board_eth_init

TFTP log:

Net:   FEC [PRIME]
Hit any key to stop autoboot:  0
icorem6qdl> tftpboot {fdt_addr} imx6dl-icore.dtb
Using FEC device
TFTP from server 192.168.2.96; our IP address is 192.168.2.75
Filename 'imx6dl-icore.dtb'.
Load address: 0x0
Loading: ##
 1.3 MiB/s
done
Bytes transferred = 28976 (7130 hex)
CACHE: Misaligned operation at range [, 7130]
icorem6qdl>

Cc: Joe Hershberger 
Cc: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 board/engicam/icorem6/icorem6.c | 72 +
 configs/imx6qdl_icore_defconfig |  2 ++
 include/configs/imx6qdl_icore.h | 12 +++
 3 files changed, 86 insertions(+)

diff --git a/board/engicam/icorem6/icorem6.c b/board/engicam/icorem6/icorem6.c
index b0595ef..4331ad3 100644
--- a/board/engicam/icorem6/icorem6.c
+++ b/board/engicam/icorem6/icorem6.c
@@ -9,12 +9,15 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 #include 
 #include 
 #include 
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -30,11 +33,28 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |   \
PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
+#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |\
+   PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   | \
+   PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+
 static iomux_v3_cfg_t const uart4_pads[] = {
IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 };
 
+static iomux_v3_cfg_t const enet_pads[] = {
+   IOMUX_PADS(PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+   IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL | 
PAD_CTL_SRE_FAST)),
+   IOMUX_PADS(PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+   IOMUX_PADS(PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+   IOMUX_PADS(PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+   IOMUX_PADS(PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+   IOMUX_PADS(PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+   IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+   IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+   IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
 static iomux_v3_cfg_t const usdhc1_pads[] = {
IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
@@ -99,6 +119,58 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+#ifdef CONFIG_FEC_MXC
+#define ENET_PHY_RST   IMX_GPIO_NR(7, 12)
+static int setup_fec(void)
+{
+   struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+   struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+   s32 timeout = 10;
+   u32 reg = 0;
+   int ret;
+
+   /* Enable fec clock */
+   setbits_le32(>CCGR1, MXC_CCM_CCGR1_ENET_MASK);
+
+   /* use 50MHz */
+   ret = enable_fec_anatop_clock(0, ENET_50MHZ);
+   if (ret)
+   return ret;
+
+   /* Enable PLLs */
+   reg = readl(>pll_enet);
+   reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
+   writel(reg, >pll_enet);
+   reg = readl(>pll_enet);
+   reg |= BM_ANADIG_PLL_SYS_ENABLE;
+   while (timeout--) {
+   if (readl(>pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
+   break;
+   }
+   if (timeout <= 0)
+   return -EIO;
+   reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
+   writel(reg, >pll_enet);
+
+   /* reset the phy */
+   gpio_direction_output(ENET_PHY_RST, 0);
+   udelay(1);
+   gpio_set_value(ENET_PHY_RST, 1);
+
+   return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+   int ret;
+
+   SETUP_IOMUX_PADS(enet_pads);
+   setup_fec();
+
+   return ret = cpu_eth_init(bis);
+}
+#endif
+
 int board_early_init_f(void)
 {
SETUP_IOMUX_PADS(uart4_pads);
diff --git a/configs/imx6qdl_icore_defconfig b/configs/imx6qdl_icore_defconfig
index a658f4b..bdaf6dc 100644
--- a/configs/imx6qdl_icore_defconfig
+++ b/configs/imx6qdl_icore_defconfig
@@ -14,6 +14,8 @@ CONFIG_SYS_MAXARGS=32
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_CACHE=y
diff --git a/include/configs/imx6qdl_icore.h b/include/configs/imx6qdl_icore.h
index e12e772..b5ad865 100644
--- a/include/configs/imx6qdl_icore.h
+++ 

[U-Boot] [PATCH v2 07/17] imx: s/docs\/README.imximage/doc\/README.imximage/g

[Jagan Teki]

Fixed typo for doc/README.imximage on respective imximage.cfg files.

Cc: Tom Rini 
Cc: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Signed-off-by: Jagan Teki 
---
 board/barco/titanium/imximage.cfg   | 2 +-
 board/ccv/xpress/imximage.cfg   | 2 +-
 board/denx/m53evk/imximage.cfg  | 2 +-
 board/freescale/mx6sabresd/mx6dlsabresd.cfg | 2 +-
 board/freescale/mx6slevk/imximage.cfg   | 2 +-
 board/freescale/mx6ullevk/imximage.cfg  | 2 +-
 board/freescale/mx7dsabresd/imximage.cfg| 2 +-
 board/freescale/s32v234evb/s32v234evb.cfg   | 2 +-
 board/freescale/vf610twr/imximage.cfg   | 2 +-
 board/phytec/pcm052/imximage.cfg| 2 +-
 board/technexion/pico-imx6ul/imximage.cfg   | 2 +-
 board/toradex/colibri_imx7/imximage.cfg | 2 +-
 board/toradex/colibri_vf/imximage.cfg   | 2 +-
 board/warp/imximage.cfg | 2 +-
 board/warp7/imximage.cfg| 2 +-
 15 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/board/barco/titanium/imximage.cfg 
b/board/barco/titanium/imximage.cfg
index 7219256..4fb6982 100644
--- a/board/barco/titanium/imximage.cfg
+++ b/board/barco/titanium/imximage.cfg
@@ -7,7 +7,7 @@
  *
  * SPDX-License-Identifier:GPL-2.0+
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/ccv/xpress/imximage.cfg b/board/ccv/xpress/imximage.cfg
index 92167c9..d98bc36 100644
--- a/board/ccv/xpress/imximage.cfg
+++ b/board/ccv/xpress/imximage.cfg
@@ -3,7 +3,7 @@
  *
  * SPDX-License-Identifier:GPL-2.0+
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/denx/m53evk/imximage.cfg b/board/denx/m53evk/imximage.cfg
index 4cd002c..c0e2602 100644
--- a/board/denx/m53evk/imximage.cfg
+++ b/board/denx/m53evk/imximage.cfg
@@ -4,7 +4,7 @@
  *
  * SPDX-License-Identifier:GPL-2.0+
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/mx6sabresd/mx6dlsabresd.cfg 
b/board/freescale/mx6sabresd/mx6dlsabresd.cfg
index f35f22e..be9f87f 100644
--- a/board/freescale/mx6sabresd/mx6dlsabresd.cfg
+++ b/board/freescale/mx6sabresd/mx6dlsabresd.cfg
@@ -3,7 +3,7 @@
  *
  * SPDX-License-Identifier:GPL-2.0+
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/mx6slevk/imximage.cfg 
b/board/freescale/mx6slevk/imximage.cfg
index c77bbde..024de9c 100644
--- a/board/freescale/mx6slevk/imximage.cfg
+++ b/board/freescale/mx6slevk/imximage.cfg
@@ -3,7 +3,7 @@
  *
  * SPDX-License-Identifier:GPL-2.0+
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/mx6ullevk/imximage.cfg 
b/board/freescale/mx6ullevk/imximage.cfg
index 4604b62..3ae4912 100644
--- a/board/freescale/mx6ullevk/imximage.cfg
+++ b/board/freescale/mx6ullevk/imximage.cfg
@@ -3,7 +3,7 @@
  *
  * SPDX-License-Identifier:GPL-2.0+
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/mx7dsabresd/imximage.cfg 
b/board/freescale/mx7dsabresd/imximage.cfg
index 76574ff..c2b3a8c 100644
--- a/board/freescale/mx7dsabresd/imximage.cfg
+++ b/board/freescale/mx7dsabresd/imximage.cfg
@@ -3,7 +3,7 @@
  *
  * SPDX-License-Identifier:GPL-2.0+
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/s32v234evb/s32v234evb.cfg 
b/board/freescale/s32v234evb/s32v234evb.cfg
index 6017a40..6449ef2 100644
--- a/board/freescale/s32v234evb/s32v234evb.cfg
+++ b/board/freescale/s32v234evb/s32v234evb.cfg
@@ -5,7 +5,7 @@
  */
 
 /*
- * Refer docs/README.imxmage for more details about 

[U-Boot] [PATCH v2 04/17] Kconfig: Add DEFAULT_FDT_FILE entry

[Jagan Teki]

Add kconfig entry for CONFIG_DEFAULT_FDT_FILE

Cc: Tom Rini 
Cc: Simon Glass 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 common/Kconfig | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/common/Kconfig b/common/Kconfig
index 46e7173..278e33b 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -198,6 +198,12 @@ config CONSOLE_RECORD_IN_SIZE
  The buffer is allocated immediately after the malloc() region is
  ready.
 
+config DEFAULT_FDT_FILE
+   string "Default fdt file"
+   default n
+   help
+ This option is used to set the default fdt file to boot OS.
+
 config SYS_NO_FLASH
bool "Disable support for parallel NOR flash"
default n
-- 
2.7.4

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[U-Boot] [PATCH v2 05/17] arm: imx: Add Engicam i.CoreM6 QDL Starter Kit initial support

[Jagan Teki]

Boot Log for i.CoreM6 DualLite/Solo Starter Kit:
---

U-Boot SPL 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46)
Trying to boot from MMC1

U-Boot 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46 +0530)

CPU:   Freescale i.MX6SOLO rev1.3 at 792MHz
CPU:   Industrial temperature grade (-40C to 105C) at 31C
Reset cause: POR
DRAM:  256 MiB
MMC:   FSL_SDHC: 0
*** Warning - bad CRC, using default environment

In:serial
Out:   serial
Err:   serial
Net:   CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot:  0
switch to partitions #0, OK
mmc0 is current device
switch to partitions #0, OK
mmc0 is current device
reading boot.scr
** Unable to read file boot.scr **
reading zImage
6741808 bytes read in 341 ms (18.9 MiB/s)
Booting from mmc ...
reading imx6dl-icore.dtb
30600 bytes read in 19 ms (1.5 MiB/s)
   Booting using the fdt blob at 0x1800
   Using Device Tree in place at 1800, end 1800a787

Starting kernel ...

[0.00] Booting Linux on physical CPU 0x0

Boot Log for i.CoreM6 Quad/Dual Starter Kit:


U-Boot SPL 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46)
Trying to boot from MMC1

U-Boot 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46 +0530)

CPU:   Freescale i.MX6Q rev1.2 at 792MHz
CPU:   Industrial temperature grade (-40C to 105C) at 28C
Reset cause: POR
DRAM:  512 MiB
MMC:   FSL_SDHC: 0
*** Warning - bad CRC, using default environment

In:serial
Out:   serial
Err:   serial
Net:   CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot:  0
icorem6qdl>

Cc: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 arch/arm/cpu/armv7/mx6/Kconfig|   8 +
 board/engicam/icorem6/Kconfig |  12 ++
 board/engicam/icorem6/MAINTAINERS |   6 +
 board/engicam/icorem6/Makefile|   6 +
 board/engicam/icorem6/README  |  31 +++
 board/engicam/icorem6/icorem6.c   | 400 ++
 configs/imx6qdl_icore_defconfig   |  27 +++
 include/configs/imx6qdl_icore.h   | 115 +++
 8 files changed, 605 insertions(+)
 create mode 100644 board/engicam/icorem6/Kconfig
 create mode 100644 board/engicam/icorem6/MAINTAINERS
 create mode 100644 board/engicam/icorem6/Makefile
 create mode 100644 board/engicam/icorem6/README
 create mode 100644 board/engicam/icorem6/icorem6.c
 create mode 100644 configs/imx6qdl_icore_defconfig
 create mode 100644 include/configs/imx6qdl_icore.h

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index d851b26..5d549bd 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -95,6 +95,13 @@ config TARGET_MX6CUBOXI
 config TARGET_MX6QARM2
bool "mx6qarm2"
 
+config TARGET_MX6Q_ICORE
+   bool "Support Engicam i.Core"
+   select MX6QDL
+   select DM
+   select DM_THERMAL
+   select SUPPORT_SPL
+
 config TARGET_MX6QSABREAUTO
bool "mx6qsabreauto"
select DM
@@ -225,6 +232,7 @@ source "board/compulab/cm_fx6/Kconfig"
 source "board/congatec/cgtqmx6eval/Kconfig"
 source "board/el/el6x/Kconfig"
 source "board/embest/mx6boards/Kconfig"
+source "board/engicam/icorem6/Kconfig"
 source "board/freescale/mx6qarm2/Kconfig"
 source "board/freescale/mx6qsabreauto/Kconfig"
 source "board/freescale/mx6sabresd/Kconfig"
diff --git a/board/engicam/icorem6/Kconfig b/board/engicam/icorem6/Kconfig
new file mode 100644
index 000..6d62f0e
--- /dev/null
+++ b/board/engicam/icorem6/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6Q_ICORE
+
+config SYS_BOARD
+   default "icorem6"
+
+config SYS_VENDOR
+   default "engicam"
+
+config SYS_CONFIG_NAME
+   default "imx6qdl_icore"
+
+endif
diff --git a/board/engicam/icorem6/MAINTAINERS 
b/board/engicam/icorem6/MAINTAINERS
new file mode 100644
index 000..3e06c6b
--- /dev/null
+++ b/board/engicam/icorem6/MAINTAINERS
@@ -0,0 +1,6 @@
+ICOREM6QDL BOARD
+M: Jagan Teki 
+S: Maintained
+F: board/engicam/icorem6
+F: include/configs/icorem6qdl.h
+F: configs/icorem6qdl_defconfig
diff --git a/board/engicam/icorem6/Makefile b/board/engicam/icorem6/Makefile
new file mode 100644
index 000..9ec9ecd
--- /dev/null
+++ b/board/engicam/icorem6/Makefile
@@ -0,0 +1,6 @@
+# Copyright (C) 2016 Amarula Solutions B.V.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  := icorem6.o
diff --git a/board/engicam/icorem6/README b/board/engicam/icorem6/README
new file mode 100644
index 000..e493d9c
--- /dev/null
+++ b/board/engicam/icorem6/README
@@ -0,0 +1,31 @@
+How to use U-Boot on Engicam i.CoreM6 DualLite/Solo and Quad/Dual Starter Kit:
+-
+
+- Build U-Boot for Engicam 

[U-Boot] [PATCH v2 02/17] serial: Kconfig: Add MXC_UART entry

[Jagan Teki]

Added kconfig for MXC_UART driver.

Cc: Simon Glass 
Cc: Fabio Estevam 
Cc: Stefano Babic 
Cc: Peng Fan 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 drivers/serial/Kconfig | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index ab5df70..9abf158 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -295,6 +295,13 @@ config FSL_LPUART
  Select this to enable a Low Power UART for Freescale VF610 and
  QorIQ Layerscape devices.
 
+config MXC_UART
+   bool "IMX serial port support"
+   depends on MX6
+   help
+ If you have a machine based on a Motorola IMX CPU you
+ can enable its onboard serial port by enabling this option.
+
 config PIC32_SERIAL
bool "Support for Microchip PIC32 on-chip UART"
depends on DM_SERIAL && MACH_PIC32
-- 
2.7.4

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[U-Boot] [PATCH v2 03/17] thermal: Kconfig: Add IMX_THERMAL entry

[Jagan Teki]

Added kconfig for IMX_THERMAL driver.

Cc: Simon Glass 
Cc: Fabio Estevam 
Cc: Stefano Babic 
Cc: Peng Fan 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 drivers/thermal/Kconfig | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 8e22ea7..f0ffbb3 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -5,3 +5,16 @@ config DM_THERMAL
  temperature sensors to permit warnings, speed throttling or even
  automatic power-off when the temperature gets too high or low. Other
  devices may be discrete but connected on a suitable bus.
+
+if DM_THERMAL
+
+config IMX_THERMAL
+   bool "Temperature sensor driver for Freescale i.MX SoCs"
+   depends on MX6
+   help
+ Support for Temperature Monitor (TEMPMON) found on Freescale i.MX 
SoCs.
+  It supports one critical trip point and one passive trip point.  The
+  cpufreq is used as the cooling device to throttle CPUs when the
+  passive trip is crossed.
+
+endif # if DM_THERMAL
-- 
2.7.4

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[U-Boot] [PATCH v2 01/17] imx: iomux-v3: Fix build error with snvs base

[Jagan Teki]

snvs base is added only for i.MX6ULL but the code is
added for common, so firing build error while compiling
other i.MX6 SOC's

Issue observed with the below patch
"imx: mx6ull: Update memory map address"
(sha1: e8eac1b5b3a98a06426bc4867c03c38329841e5c)

Build log:
  CC  arch/arm/imx-common/iomux-v3.o
arch/arm/imx-common/iomux-v3.c: In function 'imx_iomux_v3_setup_pad':
arch/arm/imx-common/iomux-v3.c:56:19: error: 'IOMUXC_SNVS_BASE_ADDR' undeclared 
(first use in this function)
base = (void *)IOMUXC_SNVS_BASE_ADDR;

Cc: Stefano Babic 
Cc: Peng Fan 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 arch/arm/imx-common/iomux-v3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
index 78f667e..efb884c 100644
--- a/arch/arm/imx-common/iomux-v3.c
+++ b/arch/arm/imx-common/iomux-v3.c
@@ -50,7 +50,7 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
if (sel_input_ofs)
sel_input_ofs += IOMUX_LPSR_SEL_INPUT_OFS;
}
-#else
+#elif defined(CONFIG_MX6ULL)
if (is_mx6ull()) {
if (lpsr == IOMUX_CONFIG_LPSR) {
base = (void *)IOMUXC_SNVS_BASE_ADDR;
-- 
2.7.4

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[U-Boot] [PATCH v2 00/17] imx6: Add Engicam i.CoreM6 QDL modules support

[Jagan Teki]

This series supports Engicam i.CoreM6 QDL modules on top of u-boot-imx.git/next
and test on the respective starter kits as well.

Changes for v2:
- Make static to local iomux structure in board file
- Corrected rowaddr in mx6_ddr3_cfg
- Used imx_ddr_size
- Add FEC support and tested the same
- Add DM_GPIO, DM_MMC support
- Add pinctrl support
- Add devicetree support

Jagan Teki (17):
  imx: iomux-v3: Fix build error with snvs base
  serial: Kconfig: Add MXC_UART entry
  thermal: Kconfig: Add IMX_THERMAL entry
  Kconfig: Add DEFAULT_FDT_FILE entry
  arm: imx: Add Engicam i.CoreM6 QDL Starter Kit initial support
  imx6: icorem6: Add ENET support
  imx: s/docs\/README.imximage/doc\/README.imximage/g
  arm: dts: Add devicetree for i.MX6DL
  arm: dts: Add devicetree for i.MX6DQL
  arm: dts: imx6dl: Add pinctrl defines
  dt-bindings: clock: imx6qdl: Add clock defines
  arm: imx6q: Add devicetree support for Engicam i.CoreM6 DualLite/Solo
  imx6q: icorem6: Enable pinctrl driver
  engicam: icorem6: Add DM_GPIO, DM_MMC support
  arm: dts: Add devicetree for i.MX6Q
  arm: dts: imx6q: Add pinctrl defines
  arm: imx6q: Add devicetree support for Engicam i.CoreM6 Quad/Dual

 arch/arm/cpu/armv7/mx6/Kconfig  |   11 +
 arch/arm/dts/Makefile   |4 +-
 arch/arm/dts/imx6dl-icore.dts   |   59 ++
 arch/arm/dts/imx6dl-pinfunc.h   | 1091 +++
 arch/arm/dts/imx6dl.dtsi|  133 +++
 arch/arm/dts/imx6q-icore.dts|   59 ++
 arch/arm/dts/imx6q-pinfunc.h| 1047 ++
 arch/arm/dts/imx6q.dtsi |  300 +++
 arch/arm/dts/imx6qdl-icore.dtsi |  234 +
 arch/arm/dts/imx6qdl.dtsi   | 1281 +++
 arch/arm/imx-common/iomux-v3.c  |2 +-
 board/barco/titanium/imximage.cfg   |2 +-
 board/ccv/xpress/imximage.cfg   |2 +-
 board/denx/m53evk/imximage.cfg  |2 +-
 board/engicam/icorem6/Kconfig   |   12 +
 board/engicam/icorem6/MAINTAINERS   |6 +
 board/engicam/icorem6/Makefile  |6 +
 board/engicam/icorem6/README|   38 +
 board/engicam/icorem6/icorem6.c |  474 ++
 board/freescale/mx6sabresd/mx6dlsabresd.cfg |2 +-
 board/freescale/mx6slevk/imximage.cfg   |2 +-
 board/freescale/mx6ullevk/imximage.cfg  |2 +-
 board/freescale/mx7dsabresd/imximage.cfg|2 +-
 board/freescale/s32v234evb/s32v234evb.cfg   |2 +-
 board/freescale/vf610twr/imximage.cfg   |2 +-
 board/phytec/pcm052/imximage.cfg|2 +-
 board/technexion/pico-imx6ul/imximage.cfg   |2 +-
 board/toradex/colibri_imx7/imximage.cfg |2 +-
 board/toradex/colibri_vf/imximage.cfg   |2 +-
 board/warp/imximage.cfg |2 +-
 board/warp7/imximage.cfg|2 +-
 common/Kconfig  |6 +
 configs/imx6qdl_icore_defconfig |   32 +
 drivers/serial/Kconfig  |7 +
 drivers/thermal/Kconfig |   13 +
 include/configs/imx6qdl_icore.h |  131 +++
 include/dt-bindings/clock/imx6qdl-clock.h   |  274 ++
 37 files changed, 5233 insertions(+), 17 deletions(-)
 create mode 100644 arch/arm/dts/imx6dl-icore.dts
 create mode 100644 arch/arm/dts/imx6dl-pinfunc.h
 create mode 100644 arch/arm/dts/imx6dl.dtsi
 create mode 100644 arch/arm/dts/imx6q-icore.dts
 create mode 100644 arch/arm/dts/imx6q-pinfunc.h
 create mode 100644 arch/arm/dts/imx6q.dtsi
 create mode 100644 arch/arm/dts/imx6qdl-icore.dtsi
 create mode 100644 arch/arm/dts/imx6qdl.dtsi
 create mode 100644 board/engicam/icorem6/Kconfig
 create mode 100644 board/engicam/icorem6/MAINTAINERS
 create mode 100644 board/engicam/icorem6/Makefile
 create mode 100644 board/engicam/icorem6/README
 create mode 100644 board/engicam/icorem6/icorem6.c
 create mode 100644 configs/imx6qdl_icore_defconfig
 create mode 100644 include/configs/imx6qdl_icore.h
 create mode 100644 include/dt-bindings/clock/imx6qdl-clock.h

-- 
2.7.4

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Re: [U-Boot] [PATCH v3 12/45] spear: Use upper case for CONFIG options

[Tom Rini]

On Mon, Sep 12, 2016 at 11:18:30PM -0600, Simon Glass wrote:

> There are a few options which use lower case. We should use upper case for
> all CONFIG options.
> 
> Signed-off-by: Simon Glass 

This is incomplete:
13: spear: Use upper case for CONFIG options
arm: (for 1/1 boards)  all -12877.0  bss -936.0  data -148.0  
rodata -1717.0  text -10076.0 
spear310_usbtty_nand:  all -12877  bss -936  data -148  rodata 
-1717  text -10076 

And all of the other spear boards have a problem as well.  I'm going to
see about fixing these up.

-- 
Tom


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Re: [U-Boot] [Patch v6 8/9] armv8: ls1046ardb: Add LS1046ARDB board support

[york sun]

On 09/07/2016 03:08 AM, Gong Qianyu wrote:
> From: Mingkai Hu 
>
> LS1046ARDB Specification:
> -
> Memory subsystem:
>  * 8GByte DDR4 SDRAM (64bit bus)
>  * 512 Mbyte NAND flash
>  * Two 64 Mbyte high-speed SPI flash
>  * SD connector to interface with the SD memory card
>  * On-board 4G eMMC
>
> Ethernet:
>  * Two XFI 10G ports
>  * Two SGMII ports
>  * Two RGMII ports
>
> PCIe:
>  * PCIe1 (SerDes2 Lane0) to miniPCIe slot
>  * PCIe2 (SerDes2 Lane1) to x2 PCIe slot
>  * PCIe3 (SerDes2 Lane2) to x4 PCIe slot

Why don't you enable PCIe in the config file?



> diff --git a/board/freescale/ls1046ardb/ddr.c 
> b/board/freescale/ls1046ardb/ddr.c
> new file mode 100644
> index 000..a9b7dbd
> --- /dev/null
> +++ b/board/freescale/ls1046ardb/ddr.c
> @@ -0,0 +1,140 @@
> +/*
> + * Copyright 2016 Freescale Semiconductor, Inc.
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include "ddr.h"
> +#ifdef CONFIG_FSL_DEEP_SLEEP
> +#include 
> +#endif
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +void fsl_ddr_board_options(memctl_options_t *popts,
> +dimm_params_t *pdimm,
> +unsigned int ctrl_num)
> +{
> + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
> + ulong ddr_freq;
> +
> + if (ctrl_num > 1) {
> + printf("Not supported controller number %d\n", ctrl_num);
> + return;
> + }
> + if (!pdimm->n_ranks)
> + return;
> +
> + pbsp = udimms[0];
> +
> + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
> +  * freqency and n_banks specified in board_specific_parameters table.
> +  */
> + ddr_freq = get_ddr_freq(0) / 100;
> + while (pbsp->datarate_mhz_high) {
> + if (pbsp->n_ranks == pdimm->n_ranks) {
> + if (ddr_freq <= pbsp->datarate_mhz_high) {
> + popts->clk_adjust = pbsp->clk_adjust;
> + popts->wrlvl_start = pbsp->wrlvl_start;
> + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
> + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
> + goto found;
> + }
> + pbsp_highest = pbsp;
> + }
> + pbsp++;
> + }
> +
> + if (pbsp_highest) {
> + printf("Error: board specific timing not found for %lu MT/s\n",
> +ddr_freq);
> + printf("Trying to use the highest speed (%u) parameters\n",
> +pbsp_highest->datarate_mhz_high);
> + popts->clk_adjust = pbsp_highest->clk_adjust;
> + popts->wrlvl_start = pbsp_highest->wrlvl_start;
> + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
> + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
> + } else {
> + panic("DIMM is not supported by this board");
> + }
> +found:
> + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
> +   pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
> +
> + popts->data_bus_width = 0;  /* 64-bit data bus */
> + popts->otf_burst_chop_en = 0;
> + popts->burst_length = DDR_BL8;

You don't need to set these options unless you specifically want to 
disable on the fly burst chop. Do you?

York
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[U-Boot] [PATCH 14/15] ARM: uniphier: add PLL init code for LD20 SoC

[Masahiro Yamada]

Initialize the DPLL (PLL for DRAM) in SPL, and others in U-Boot
proper.  Split the common code into pll-base-ld20.c for easier
re-use.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/board_init.c|   7 ++
 arch/arm/mach-uniphier/clk/Makefile|   6 +-
 arch/arm/mach-uniphier/clk/dpll-ld20.c |  22 ++
 arch/arm/mach-uniphier/clk/pll-base-ld20.c | 123 +
 arch/arm/mach-uniphier/clk/pll-ld20.c  |  40 ++
 arch/arm/mach-uniphier/clk/pll.h   |   8 ++
 arch/arm/mach-uniphier/init.h  |   5 ++
 arch/arm/mach-uniphier/init/init-ld20.c|   6 +-
 arch/arm/mach-uniphier/sc64-regs.h |  19 +
 9 files changed, 232 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/mach-uniphier/clk/dpll-ld20.c
 create mode 100644 arch/arm/mach-uniphier/clk/pll-base-ld20.c
 create mode 100644 arch/arm/mach-uniphier/clk/pll-ld20.c

diff --git a/arch/arm/mach-uniphier/board_init.c 
b/arch/arm/mach-uniphier/board_init.c
index a1c7541..b57a33f 100644
--- a/arch/arm/mach-uniphier/board_init.c
+++ b/arch/arm/mach-uniphier/board_init.c
@@ -58,8 +58,14 @@ static void uniphier_nand_pin_init(bool cs2)
 
 int board_init(void)
 {
+   const struct uniphier_board_data *bd;
+
led_puts("U0");
 
+   bd = uniphier_get_board_param();
+   if (!bd)
+   return -ENODEV;
+
switch (uniphier_get_soc_type()) {
 #if defined(CONFIG_ARCH_UNIPHIER_SLD3)
case SOC_UNIPHIER_SLD3:
@@ -133,6 +139,7 @@ int board_init(void)
sg_set_pinsel(153, 14, 8, 4);   /* XIRQ4-> XIRQ4 */
sg_set_iectrl(153);
led_puts("U1");
+   uniphier_ld20_pll_init(bd);
uniphier_ld20_clk_init();
cci500_init(2);
break;
diff --git a/arch/arm/mach-uniphier/clk/Makefile 
b/arch/arm/mach-uniphier/clk/Makefile
index 233e659..c8d59ea 100644
--- a/arch/arm/mach-uniphier/clk/Makefile
+++ b/arch/arm/mach-uniphier/clk/Makefile
@@ -12,7 +12,7 @@ obj-$(CONFIG_ARCH_UNIPHIER_PRO5)  += early-clk-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)   += early-clk-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)   += early-clk-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD11)   += early-clk-ld11.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD20)   += early-clk-ld20.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20)   += early-clk-ld20.o dpll-ld20.o
 
 else
 
@@ -24,6 +24,8 @@ obj-$(CONFIG_ARCH_UNIPHIER_PRO5)  += clk-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)   += clk-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)   += clk-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD11)   += clk-ld11.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD20)   += clk-ld20.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20)   += clk-ld20.o pll-ld20.o
 
 endif
+
+obj-$(CONFIG_ARCH_UNIPHIER_LD20)   += pll-base-ld20.o
diff --git a/arch/arm/mach-uniphier/clk/dpll-ld20.c 
b/arch/arm/mach-uniphier/clk/dpll-ld20.c
new file mode 100644
index 000..1132313
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/dpll-ld20.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include "../init.h"
+#include "../sc64-regs.h"
+#include "pll.h"
+
+int uniphier_ld20_dpll_init(const struct uniphier_board_data *bd)
+{
+   unsigned int dpll_ssc_rate = UNIPHIER_BD_DPLL_SSC_GET_RATE(bd->flags);
+   unsigned int dram_freq = bd->dram_freq;
+
+   uniphier_ld20_sscpll_init(SC_DPLL0CTRL, dram_freq, dpll_ssc_rate, 2);
+   uniphier_ld20_sscpll_init(SC_DPLL1CTRL, dram_freq, dpll_ssc_rate, 2);
+   uniphier_ld20_sscpll_init(SC_DPLL2CTRL, dram_freq, dpll_ssc_rate, 2);
+
+   return 0;
+}
diff --git a/arch/arm/mach-uniphier/clk/pll-base-ld20.c 
b/arch/arm/mach-uniphier/clk/pll-base-ld20.c
new file mode 100644
index 000..a5027d2
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/pll-base-ld20.c
@@ -0,0 +1,123 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include "pll.h"
+
+/* PLL type: SSC */
+#define SC_PLLCTRL_SSC_DK_MASK GENMASK(14, 0)
+#define SC_PLLCTRL_SSC_EN  BIT(31)
+#define SC_PLLCTRL2_NRSTDS BIT(28)
+#define SC_PLLCTRL2_SSC_JK_MASKGENMASK(26, 0)
+
+/* PLL type: VPLL27 */
+#define SC_VPLL27CTRL_WP   BIT(0)
+#define SC_VPLL27CTRL3_K_LDBIT(28)
+
+/* PLL type: DSPLL */
+#define SC_DSPLLCTRL2_K_LD BIT(28)
+
+int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
+ unsigned int ssc_rate, unsigned int divn)
+{
+   void __iomem *base;
+   u32 tmp;
+
+   base = ioremap(reg_base, SZ_16);
+   if (!base)
+   return -ENOMEM;
+
+   if (freq != UNIPHIER_PLL_FREQ_DEFAULT) {
+   

[U-Boot] [PATCH 13/15] ARM: uniphier: collect clock/PLL init code into a single directory

[Masahiro Yamada]

Now PLLs for DRAM controller are initialized in SPL, and the others
in U-Boot proper.  Setting up all of them in a single directory will
be helpful when we want to share code between SPL and U-Boot proper.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/Makefile  |  5 ++---
 arch/arm/mach-uniphier/clk/Makefile  | 16 
 .../mach-uniphier/{pll/pll-init-ld4.c => clk/dpll-ld4.c} |  0
 .../{pll/pll-init-pro4.c => clk/dpll-pro4.c} |  0
 .../{pll/pll-init-sld3.c => clk/dpll-sld3.c} |  0
 .../{pll/pll-init-sld8.c => clk/dpll-sld8.c} |  0
 .../mach-uniphier/{early-clk => clk}/early-clk-ld11.c|  0
 .../mach-uniphier/{early-clk => clk}/early-clk-ld20.c|  0
 .../arm/mach-uniphier/{early-clk => clk}/early-clk-ld4.c |  0
 .../mach-uniphier/{early-clk => clk}/early-clk-pro5.c|  0
 .../mach-uniphier/{early-clk => clk}/early-clk-pxs2.c|  0
 arch/arm/mach-uniphier/early-clk/Makefile| 13 -
 arch/arm/mach-uniphier/pll/Makefile  |  8 
 13 files changed, 18 insertions(+), 24 deletions(-)
 rename arch/arm/mach-uniphier/{pll/pll-init-ld4.c => clk/dpll-ld4.c} (100%)
 rename arch/arm/mach-uniphier/{pll/pll-init-pro4.c => clk/dpll-pro4.c} (100%)
 rename arch/arm/mach-uniphier/{pll/pll-init-sld3.c => clk/dpll-sld3.c} (100%)
 rename arch/arm/mach-uniphier/{pll/pll-init-sld8.c => clk/dpll-sld8.c} (100%)
 rename arch/arm/mach-uniphier/{early-clk => clk}/early-clk-ld11.c (100%)
 rename arch/arm/mach-uniphier/{early-clk => clk}/early-clk-ld20.c (100%)
 rename arch/arm/mach-uniphier/{early-clk => clk}/early-clk-ld4.c (100%)
 rename arch/arm/mach-uniphier/{early-clk => clk}/early-clk-pro5.c (100%)
 rename arch/arm/mach-uniphier/{early-clk => clk}/early-clk-pxs2.c (100%)
 delete mode 100644 arch/arm/mach-uniphier/early-clk/Makefile
 delete mode 100644 arch/arm/mach-uniphier/pll/Makefile

diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile
index 548cfe7..ae78548 100644
--- a/arch/arm/mach-uniphier/Makefile
+++ b/arch/arm/mach-uniphier/Makefile
@@ -4,7 +4,7 @@
 
 ifdef CONFIG_SPL_BUILD
 
-obj-y += init/ bcu/ memconf/ pll/ early-clk/
+obj-y += init/ bcu/ memconf/
 obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/
 
 else
@@ -15,13 +15,12 @@ obj-y += board_init.o
 obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o
 obj-y += reset.o
 
-obj-y += clk/
-
 endif
 
 obj-y += boards.o
 obj-y += soc_info.o
 obj-y += boot-mode/
+obj-y += clk/
 obj-y += dram/
 obj-y += pinctrl-glue.o
 
diff --git a/arch/arm/mach-uniphier/clk/Makefile 
b/arch/arm/mach-uniphier/clk/Makefile
index b722781..233e659 100644
--- a/arch/arm/mach-uniphier/clk/Makefile
+++ b/arch/arm/mach-uniphier/clk/Makefile
@@ -2,6 +2,20 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
+ifdef CONFIG_SPL_BUILD
+
+obj-$(CONFIG_ARCH_UNIPHIER_SLD3)   += early-clk-ld4.o dpll-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD4)+= early-clk-ld4.o dpll-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO4)   += early-clk-ld4.o dpll-pro4.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD8)   += early-clk-ld4.o dpll-sld8.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO5)   += early-clk-pro5.o
+obj-$(CONFIG_ARCH_UNIPHIER_PXS2)   += early-clk-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD6B)   += early-clk-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11)   += early-clk-ld11.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20)   += early-clk-ld20.o
+
+else
+
 obj-$(CONFIG_ARCH_UNIPHIER_SLD3)   += clk-ld4.o pll-sld3.o dpll-tail.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD4)+= clk-ld4.o pll-ld4.o 
dpll-tail.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO4)   += clk-pro4.o pll-pro4.o dpll-tail.o
@@ -11,3 +25,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_PXS2)  += clk-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)   += clk-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD11)   += clk-ld11.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD20)   += clk-ld20.o
+
+endif
diff --git a/arch/arm/mach-uniphier/pll/pll-init-ld4.c 
b/arch/arm/mach-uniphier/clk/dpll-ld4.c
similarity index 100%
rename from arch/arm/mach-uniphier/pll/pll-init-ld4.c
rename to arch/arm/mach-uniphier/clk/dpll-ld4.c
diff --git a/arch/arm/mach-uniphier/pll/pll-init-pro4.c 
b/arch/arm/mach-uniphier/clk/dpll-pro4.c
similarity index 100%
rename from arch/arm/mach-uniphier/pll/pll-init-pro4.c
rename to arch/arm/mach-uniphier/clk/dpll-pro4.c
diff --git a/arch/arm/mach-uniphier/pll/pll-init-sld3.c 
b/arch/arm/mach-uniphier/clk/dpll-sld3.c
similarity index 100%
rename from arch/arm/mach-uniphier/pll/pll-init-sld3.c
rename to arch/arm/mach-uniphier/clk/dpll-sld3.c
diff --git a/arch/arm/mach-uniphier/pll/pll-init-sld8.c 
b/arch/arm/mach-uniphier/clk/dpll-sld8.c
similarity index 100%
rename from arch/arm/mach-uniphier/pll/pll-init-sld8.c
rename to arch/arm/mach-uniphier/clk/dpll-sld8.c
diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ld11.c 
b/arch/arm/mach-uniphier/clk/early-clk-ld11.c
similarity index 

[U-Boot] [PATCH 15/15] ARM: uniphier: update DRAM init code for LD20 SoC

[Masahiro Yamada]

Import the latest version from the Diag software.

  - Support LD21 SoC (including DDR chips in the package)
  - Per-board granule adjustment for both reference and TV boards
  - Misc cleanups

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h |  76 +++--
 arch/arm/mach-uniphier/dram/umc-ld20.c | 431 +++--
 2 files changed, 445 insertions(+), 62 deletions(-)

diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h 
b/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h
index b1b4cb0..b385a15 100644
--- a/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h
+++ b/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h
@@ -5,37 +5,49 @@
 #ifndef _DDRPHY_LD20_REGS_H
 #define _DDRPHY_LD20_REGS_H
 
-#define PHY_SCL_DATA_0 0x0104
-#define PHY_SCL_DATA_1 0x0108
-#define PHY_SCL_LATENCY0x010C
-#define PHY_SCL_START  0x0100
-#define PHY_SCL_CONFIG_1   0x0118
-#define PHY_SCL_CONFIG_2   0x011C
-#define PHY_PAD_CTRL   0x0120
-#define PHY_DLL_RECALIB0x0124
-#define PHY_DLL_ADRCTRL0x0128
-#define PHY_LANE_SEL   0x012C
-#define PHY_DLL_TRIM_1 0x0130
-#define PHY_DLL_TRIM_2 0x0134
-#define PHY_DLL_TRIM_3 0x0138
-#define PHY_SCL_MAIN_CLK_DELTA 0x0140
-#define PHY_WRLVL_AUTOINC_TRIM 0x014C
-#define PHY_WRLVL_DYN_ODT  0x0150
-#define PHY_WRLVL_ON_OFF   0x0154
-#define PHY_UNQ_ANALOG_DLL_1   0x015C
-#define PHY_DLL_INCR_TRIM_10x0164
-#define PHY_DLL_INCR_TRIM_30x0168
-#define PHY_SCL_CONFIG_3   0x016C
-#define PHY_UNIQUIFY_TSMC_IO_1 0x0170
-#define PHY_SCL_START_ADDR 0x0188
-#define PHY_DSCL_CNT   0x019C
-#define PHY_DLL_TRIM_CLK   0x01A4
-#define PHY_DYNAMIC_BIT_LVL0x01AC
-#define PHY_SCL_WINDOW_TRIM0x01B4
-#define PHY_DISABLE_GATING_FOR_SCL 0x01B8
-#define PHY_SCL_CONFIG_4   0x01BC
-#define PHY_DYNAMIC_WRITE_BIT_LVL  0x01C0
-#define PHY_VREF_TRAINING  0x01C8
-#define PHY_SCL_GATE_TIMING0x01E0
+#define PHY_REG_SHIFT  2
+
+#define PHY_SCL_START  (0x40 << (PHY_REG_SHIFT))
+#define PHY_SCL_DATA_0 (0x41 << (PHY_REG_SHIFT))
+#define PHY_SCL_DATA_1 (0x42 << (PHY_REG_SHIFT))
+#define PHY_SCL_LATENCY(0x43 << (PHY_REG_SHIFT))
+#define PHY_SCL_CONFIG_1   (0x46 << (PHY_REG_SHIFT))
+#define PHY_SCL_CONFIG_2   (0x47 << (PHY_REG_SHIFT))
+#define PHY_PAD_CTRL   (0x48 << (PHY_REG_SHIFT))
+#define PHY_DLL_RECALIB(0x49 << (PHY_REG_SHIFT))
+#define PHY_DLL_ADRCTRL(0x4A << (PHY_REG_SHIFT))
+#define PHY_LANE_SEL   (0x4B << (PHY_REG_SHIFT))
+#define PHY_DLL_TRIM_1 (0x4C << (PHY_REG_SHIFT))
+#define PHY_DLL_TRIM_2 (0x4D << (PHY_REG_SHIFT))
+#define PHY_DLL_TRIM_3 (0x4E << (PHY_REG_SHIFT))
+#define PHY_SCL_MAIN_CLK_DELTA (0x50 << (PHY_REG_SHIFT))
+#define PHY_WRLVL_AUTOINC_TRIM (0x53 << (PHY_REG_SHIFT))
+#define PHY_WRLVL_DYN_ODT  (0x54 << (PHY_REG_SHIFT))
+#define PHY_WRLVL_ON_OFF   (0x55 << (PHY_REG_SHIFT))
+#define PHY_UNQ_ANALOG_DLL_1   (0x57 << (PHY_REG_SHIFT))
+#define PHY_UNQ_ANALOG_DLL_2   (0x58 << (PHY_REG_SHIFT))
+#define PHY_DLL_INCR_TRIM_1(0x59 << (PHY_REG_SHIFT))
+#define PHY_DLL_INCR_TRIM_3(0x5A << (PHY_REG_SHIFT))
+#define PHY_SCL_CONFIG_3   (0x5B << (PHY_REG_SHIFT))
+#define PHY_UNIQUIFY_TSMC_IO_1 (0x5C << (PHY_REG_SHIFT))
+#define PHY_SCL_START_ADDR (0x62 << (PHY_REG_SHIFT))
+#define PHY_IP_DQ_DQS_BITWISE_TRIM (0x65 << (PHY_REG_SHIFT))
+#define PHY_DSCL_CNT   (0x67 << (PHY_REG_SHIFT))
+#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM  (0x68 << (PHY_REG_SHIFT))
+#define PHY_DLL_TRIM_CLK   (0x69 << (PHY_REG_SHIFT))
+#define PHY_DYNAMIC_BIT_LVL(0x6B << (PHY_REG_SHIFT))
+#define PHY_SCL_WINDOW_TRIM(0x6D << (PHY_REG_SHIFT))
+#define PHY_DISABLE_GATING_FOR_SCL (0x6E << (PHY_REG_SHIFT))
+#define PHY_SCL_CONFIG_4   (0x6F << (PHY_REG_SHIFT))
+#define PHY_DYNAMIC_WRITE_BIT_LVL  (0x70 << (PHY_REG_SHIFT))
+#define PHY_VREF_TRAINING  (0x72 << (PHY_REG_SHIFT))
+#define PHY_SCL_GATE_TIMING(0x78 << (PHY_REG_SHIFT))
+
+/* MASK */
+#define MSK_OP_DQ_DM_DQS_BITWISE_TRIM  0x007F
+#define MSK_IP_DQ_DQS_BITWISE_TRIM 0x007F
+#define MSK_OVERRIDE   0x0080
+
+#define 

[U-Boot] [PATCH 07/15] ARM: uniphier: consolidate NAND pin-mux settings

[Masahiro Yamada]

The NAND subsystem has not supported the Driver Model yet, but the
NAND pin-mux data are already in the pinctrl drivers.  Use them by
calling pinctrl_generic_set_state() directly.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/Makefile   |  1 +
 arch/arm/mach-uniphier/board_init.c   | 24 -
 arch/arm/mach-uniphier/init.h |  8 +-
 arch/arm/mach-uniphier/pinctrl-glue.c | 32 +++
 arch/arm/mach-uniphier/pinctrl/Makefile   |  7 -
 arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c | 19 --
 arch/arm/mach-uniphier/pinctrl/pinctrl-ld4.c  | 35 -
 arch/arm/mach-uniphier/pinctrl/pinctrl-ld6b.c | 35 -
 arch/arm/mach-uniphier/pinctrl/pinctrl-pro4.c | 37 ---
 arch/arm/mach-uniphier/pinctrl/pinctrl-pro5.c | 37 ---
 arch/arm/mach-uniphier/pinctrl/pinctrl-pxs2.c | 35 -
 arch/arm/mach-uniphier/pinctrl/pinctrl-sld3.c | 20 ---
 arch/arm/mach-uniphier/pinctrl/pinctrl-sld8.c | 35 -
 13 files changed, 51 insertions(+), 274 deletions(-)
 create mode 100644 arch/arm/mach-uniphier/pinctrl-glue.c
 delete mode 100644 arch/arm/mach-uniphier/pinctrl/pinctrl-ld4.c
 delete mode 100644 arch/arm/mach-uniphier/pinctrl/pinctrl-ld6b.c
 delete mode 100644 arch/arm/mach-uniphier/pinctrl/pinctrl-pro4.c
 delete mode 100644 arch/arm/mach-uniphier/pinctrl/pinctrl-pro5.c
 delete mode 100644 arch/arm/mach-uniphier/pinctrl/pinctrl-pxs2.c
 delete mode 100644 arch/arm/mach-uniphier/pinctrl/pinctrl-sld3.c
 delete mode 100644 arch/arm/mach-uniphier/pinctrl/pinctrl-sld8.c

diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile
index 1fe5199..af56d6f 100644
--- a/arch/arm/mach-uniphier/Makefile
+++ b/arch/arm/mach-uniphier/Makefile
@@ -23,6 +23,7 @@ obj-y += boards.o
 obj-y += soc_info.o
 obj-y += boot-mode/
 obj-y += dram/
+obj-y += pinctrl-glue.o
 
 obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o
 obj-$(CONFIG_DEBUG_UART_UNIPHIER) += debug-uart/
diff --git a/arch/arm/mach-uniphier/board_init.c 
b/arch/arm/mach-uniphier/board_init.c
index 6bf35ee..228092c 100644
--- a/arch/arm/mach-uniphier/board_init.c
+++ b/arch/arm/mach-uniphier/board_init.c
@@ -47,6 +47,14 @@ static void uniphier_setup_xirq(void)
writel(tmp, 0x5590);
 }
 
+static void uniphier_nand_pin_init(bool cs2)
+{
+#ifdef CONFIG_NAND_DENALI
+   if (uniphier_pin_init(cs2 ? "nand2cs_grp" : "nand_grp"))
+   pr_err("failed to init NAND pins\n");
+#endif
+}
+
 int board_init(void)
 {
led_puts("U0");
@@ -54,55 +62,56 @@ int board_init(void)
switch (uniphier_get_soc_type()) {
 #if defined(CONFIG_ARCH_UNIPHIER_SLD3)
case SOC_UNIPHIER_SLD3:
-   uniphier_sld3_pin_init();
+   uniphier_nand_pin_init(true);
led_puts("U1");
uniphier_ld4_clk_init();
break;
 #endif
 #if defined(CONFIG_ARCH_UNIPHIER_LD4)
case SOC_UNIPHIER_LD4:
-   uniphier_ld4_pin_init();
+   uniphier_nand_pin_init(true);
led_puts("U1");
uniphier_ld4_clk_init();
break;
 #endif
 #if defined(CONFIG_ARCH_UNIPHIER_PRO4)
case SOC_UNIPHIER_PRO4:
-   uniphier_pro4_pin_init();
+   uniphier_nand_pin_init(false);
led_puts("U1");
uniphier_pro4_clk_init();
break;
 #endif
 #if defined(CONFIG_ARCH_UNIPHIER_SLD8)
case SOC_UNIPHIER_SLD8:
-   uniphier_sld8_pin_init();
+   uniphier_nand_pin_init(true);
led_puts("U1");
uniphier_ld4_clk_init();
break;
 #endif
 #if defined(CONFIG_ARCH_UNIPHIER_PRO5)
case SOC_UNIPHIER_PRO5:
-   uniphier_pro5_pin_init();
+   uniphier_nand_pin_init(true);
led_puts("U1");
uniphier_pro5_clk_init();
break;
 #endif
 #if defined(CONFIG_ARCH_UNIPHIER_PXS2)
case SOC_UNIPHIER_PXS2:
-   uniphier_pxs2_pin_init();
+   uniphier_nand_pin_init(true);
led_puts("U1");
uniphier_pxs2_clk_init();
break;
 #endif
 #if defined(CONFIG_ARCH_UNIPHIER_LD6B)
case SOC_UNIPHIER_LD6B:
-   uniphier_ld6b_pin_init();
+   uniphier_nand_pin_init(true);
led_puts("U1");
uniphier_pxs2_clk_init();
break;
 #endif
 #if defined(CONFIG_ARCH_UNIPHIER_LD11)
case SOC_UNIPHIER_LD11:
+   uniphier_nand_pin_init(false);
uniphier_ld20_pin_init();
led_puts("U1");
uniphier_ld11_clk_init();
@@ -110,6 +119,7 @@ int board_init(void)
 #endif
 #if defined(CONFIG_ARCH_UNIPHIER_LD20)
case 

[U-Boot] [PATCH 05/15] ARM: uniphier: remove redundant pin-muxing for EA24 pin of sLD3 SoC

[Masahiro Yamada]

This is enabled by default for all the supported boot modes.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-sld3.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-sld3.c 
b/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-sld3.c
index 6c5d58f..22c07fb 100644
--- a/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-sld3.c
+++ b/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-sld3.c
@@ -22,7 +22,5 @@ int uniphier_sld3_early_pin_init(const struct 
uniphier_board_data *bd)
sg_set_pinsel(102, 2, 4, 4);/* TXD2 */
 #endif
 
-   sg_set_pinsel(99, 1, 4, 4); /* GPIO26 -> EA24 */
-
return 0;
 }
-- 
1.9.1

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[U-Boot] [PATCH 10/15] ARM: uniphier: move XIRQ pin-mux settings of LD11/LD20

[Masahiro Yamada]

This is the last code in the mach-uniphier/pinctrl/ directory.
Push the remaining code out to delete the directory entirely.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/Makefile   |  2 +-
 arch/arm/mach-uniphier/board_init.c   | 11 +--
 arch/arm/mach-uniphier/init.h |  2 --
 arch/arm/mach-uniphier/pinctrl/Makefile   |  6 --
 arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c | 20 
 5 files changed, 10 insertions(+), 31 deletions(-)
 delete mode 100644 arch/arm/mach-uniphier/pinctrl/Makefile
 delete mode 100644 arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c

diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile
index df6888f..548cfe7 100644
--- a/arch/arm/mach-uniphier/Makefile
+++ b/arch/arm/mach-uniphier/Makefile
@@ -15,7 +15,7 @@ obj-y += board_init.o
 obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o
 obj-y += reset.o
 
-obj-y += pinctrl/ clk/
+obj-y += clk/
 
 endif
 
diff --git a/arch/arm/mach-uniphier/board_init.c 
b/arch/arm/mach-uniphier/board_init.c
index 228092c..c9d3f28 100644
--- a/arch/arm/mach-uniphier/board_init.c
+++ b/arch/arm/mach-uniphier/board_init.c
@@ -12,6 +12,7 @@
 
 #include "init.h"
 #include "micro-support-card.h"
+#include "sg-regs.h"
 #include "soc-info.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -112,7 +113,10 @@ int board_init(void)
 #if defined(CONFIG_ARCH_UNIPHIER_LD11)
case SOC_UNIPHIER_LD11:
uniphier_nand_pin_init(false);
-   uniphier_ld20_pin_init();
+   sg_set_pinsel(149, 14, 8, 4);   /* XIRQ0-> XIRQ0 */
+   sg_set_iectrl(149);
+   sg_set_pinsel(153, 14, 8, 4);   /* XIRQ4-> XIRQ4 */
+   sg_set_iectrl(153);
led_puts("U1");
uniphier_ld11_clk_init();
break;
@@ -120,7 +124,10 @@ int board_init(void)
 #if defined(CONFIG_ARCH_UNIPHIER_LD20)
case SOC_UNIPHIER_LD20:
uniphier_nand_pin_init(false);
-   uniphier_ld20_pin_init();
+   sg_set_pinsel(149, 14, 8, 4);   /* XIRQ0-> XIRQ0 */
+   sg_set_iectrl(149);
+   sg_set_pinsel(153, 14, 8, 4);   /* XIRQ4-> XIRQ4 */
+   sg_set_iectrl(153);
led_puts("U1");
uniphier_ld20_clk_init();
cci500_init(2);
diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h
index bc524a1..1dc53d5 100644
--- a/arch/arm/mach-uniphier/init.h
+++ b/arch/arm/mach-uniphier/init.h
@@ -101,8 +101,6 @@ int uniphier_pxs2_umc_init(const struct uniphier_board_data 
*bd);
 int uniphier_ld20_umc_init(const struct uniphier_board_data *bd);
 int uniphier_ld11_umc_init(const struct uniphier_board_data *bd);
 
-void uniphier_ld20_pin_init(void);
-
 void uniphier_ld4_clk_init(void);
 void uniphier_pro4_clk_init(void);
 void uniphier_pro5_clk_init(void);
diff --git a/arch/arm/mach-uniphier/pinctrl/Makefile 
b/arch/arm/mach-uniphier/pinctrl/Makefile
deleted file mode 100644
index 4ee9553..000
--- a/arch/arm/mach-uniphier/pinctrl/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-$(CONFIG_ARCH_UNIPHIER_LD11)   += pinctrl-ld20.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD20)   += pinctrl-ld20.o
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c 
b/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c
deleted file mode 100644
index e1cb90a..000
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * Copyright (C) 2016 Masahiro Yamada 
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#include 
-
-#include "../init.h"
-#include "../sg-regs.h"
-
-void uniphier_ld20_pin_init(void)
-{
-   /* Comment format:PAD Name -> Function Name */
-
-   sg_set_pinsel(149, 14, 8, 4);   /* XIRQ0-> XIRQ0 */
-   sg_set_iectrl(149);
-   sg_set_pinsel(153, 14, 8, 4);   /* XIRQ4-> XIRQ4 */
-   sg_set_iectrl(153);
-}
-- 
1.9.1

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[U-Boot] [PATCH 08/15] ARM: dts: uniphier: include System Bus pin group node in SPL DT

[Masahiro Yamada]

This will be needed for setting up the System Bus pin-mux via the
LD11/LD20 pinctrl driver.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/dts/uniphier-ph1-ld11-ref.dts | 4 
 arch/arm/dts/uniphier-ph1-ld20-ref.dts | 4 
 2 files changed, 8 insertions(+)

diff --git a/arch/arm/dts/uniphier-ph1-ld11-ref.dts 
b/arch/arm/dts/uniphier-ph1-ld11-ref.dts
index 4eb7664..ca31026 100644
--- a/arch/arm/dts/uniphier-ph1-ld11-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-ld11-ref.dts
@@ -70,3 +70,7 @@
 _uart0 {
u-boot,dm-pre-reloc;
 };
+
+_system_bus {
+   u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/uniphier-ph1-ld20-ref.dts 
b/arch/arm/dts/uniphier-ph1-ld20-ref.dts
index 90c8705..e4e8d76 100644
--- a/arch/arm/dts/uniphier-ph1-ld20-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-ld20-ref.dts
@@ -58,3 +58,7 @@
 _uart0 {
u-boot,dm-pre-reloc;
 };
+
+_system_bus {
+   u-boot,dm-pre-reloc;
+};
-- 
1.9.1

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[U-Boot] [PATCH 06/15] ARM: uniphier: remove ad-hoc pin-mux code for sLD3

[Masahiro Yamada]

These settings are nicely cared by the pinctrl driver now.  Remove.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/early-pinctrl/Makefile  |  1 -
 .../early-pinctrl/early-pinctrl-sld3.c | 26 
 arch/arm/mach-uniphier/init.h  |  1 -
 arch/arm/mach-uniphier/init/init-sld3.c|  2 --
 arch/arm/mach-uniphier/pinctrl/pinctrl-sld3.c  | 28 --
 5 files changed, 58 deletions(-)
 delete mode 100644 arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-sld3.c

diff --git a/arch/arm/mach-uniphier/early-pinctrl/Makefile 
b/arch/arm/mach-uniphier/early-pinctrl/Makefile
index 7177a8c..84040c6 100644
--- a/arch/arm/mach-uniphier/early-pinctrl/Makefile
+++ b/arch/arm/mach-uniphier/early-pinctrl/Makefile
@@ -2,6 +2,5 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-$(CONFIG_ARCH_UNIPHIER_SLD3)   += early-pinctrl-sld3.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD11)   += early-pinctrl-ld20.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD20)   += early-pinctrl-ld20.o
diff --git a/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-sld3.c 
b/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-sld3.c
deleted file mode 100644
index 22c07fb..000
--- a/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-sld3.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada 
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#include "../init.h"
-#include "../sg-regs.h"
-
-int uniphier_sld3_early_pin_init(const struct uniphier_board_data *bd)
-{
-   /* Comment format:PAD Name -> Function Name */
-
-#ifdef CONFIG_UNIPHIER_SERIAL
-   sg_set_pinsel(63, 0, 4, 4); /* RXD0 */
-   sg_set_pinsel(64, 1, 4, 4); /* TXD0 */
-
-   sg_set_pinsel(65, 0, 4, 4); /* RXD1 */
-   sg_set_pinsel(66, 1, 4, 4); /* TXD1 */
-
-   sg_set_pinsel(96, 2, 4, 4); /* RXD2 */
-   sg_set_pinsel(102, 2, 4, 4);/* TXD2 */
-#endif
-
-   return 0;
-}
diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h
index 406d5d0..6b20784 100644
--- a/arch/arm/mach-uniphier/init.h
+++ b/arch/arm/mach-uniphier/init.h
@@ -94,7 +94,6 @@ int uniphier_pxs2_early_clk_init(const struct 
uniphier_board_data *bd);
 int uniphier_ld11_early_clk_init(const struct uniphier_board_data *bd);
 int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd);
 
-int uniphier_sld3_early_pin_init(const struct uniphier_board_data *bd);
 int uniphier_ld20_early_pin_init(const struct uniphier_board_data *bd);
 
 int uniphier_ld4_umc_init(const struct uniphier_board_data *bd);
diff --git a/arch/arm/mach-uniphier/init/init-sld3.c 
b/arch/arm/mach-uniphier/init/init-sld3.c
index 50fcbb0..1ee57ec 100644
--- a/arch/arm/mach-uniphier/init/init-sld3.c
+++ b/arch/arm/mach-uniphier/init/init-sld3.c
@@ -16,8 +16,6 @@ int uniphier_sld3_init(const struct uniphier_board_data *bd)
 
uniphier_sbc_init_admulti(bd);
 
-   uniphier_sld3_early_pin_init(bd);
-
support_card_reset();
 
uniphier_sld3_pll_init(bd);
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-sld3.c 
b/arch/arm/mach-uniphier/pinctrl/pinctrl-sld3.c
index 62edc49..16563f9 100644
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-sld3.c
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-sld3.c
@@ -9,20 +9,6 @@
 
 void uniphier_sld3_pin_init(void)
 {
-#ifdef CONFIG_USB_EHCI
-   sg_set_pinsel(13, 0, 4, 4); /* USB0OC */
-   sg_set_pinsel(14, 1, 4, 4); /* USB0VBUS */
-
-   sg_set_pinsel(15, 0, 4, 4); /* USB1OC */
-   sg_set_pinsel(16, 1, 4, 4); /* USB1VBUS */
-
-   sg_set_pinsel(17, 0, 4, 4); /* USB2OC */
-   sg_set_pinsel(18, 1, 4, 4); /* USB2VBUS */
-
-   sg_set_pinsel(19, 0, 4, 4); /* USB3OC */
-   sg_set_pinsel(20, 1, 4, 4); /* USB3VBUS */
-#endif
-
 #ifdef CONFIG_NAND_DENALI
sg_set_pinsel(38, 1, 4, 4); /* NFALE_GB, NFCLE_GB */
sg_set_pinsel(39, 1, 4, 4); /* XNFRYBY0_GB */
@@ -31,18 +17,4 @@ void uniphier_sld3_pin_init(void)
sg_set_pinsel(58, 1, 4, 4); /* NFD[0-3]_GB */
sg_set_pinsel(59, 1, 4, 4); /* NFD[4-7]_GB */
 #endif
-
-#ifdef CONFIG_MMC_UNIPHIER
-   /* eMMC */
-   sg_set_pinsel(55, 1, 4, 4); /* XERST */
-   sg_set_pinsel(56, 1, 4, 4); /* MMCDAT[0-3] */
-   sg_set_pinsel(57, 1, 4, 4); /* MMCDAT[4-7] */
-   sg_set_pinsel(60, 1, 4, 4); /* MMCCLK, MMCCMD */
-
-   /* SD card */
-   sg_set_pinsel(42, 1, 4, 4); /* SD1CLK, SD1CMD, SD1DAT[0-3] */
-   sg_set_pinsel(43, 1, 4, 4); /* SD1CD */
-   sg_set_pinsel(44, 1, 4, 4); /* SD1WP */
-   sg_set_pinsel(45, 1, 4, 4); /* SDVTCG */
-#endif
 }
-- 
1.9.1

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[U-Boot] [PATCH 09/15] ARM: uniphier: consolidate System Bus pin-mux settings for LD11/LD20

[Masahiro Yamada]

Use the pin-mux data in the pinctrl drivers by directly calling
pinctrl_generic_set_state().

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/Makefile|  2 +-
 arch/arm/mach-uniphier/early-pinctrl/Makefile  |  6 
 .../early-pinctrl/early-pinctrl-ld20.c | 32 --
 arch/arm/mach-uniphier/init.h  |  2 --
 arch/arm/mach-uniphier/init/init-ld11.c|  2 +-
 arch/arm/mach-uniphier/init/init-ld20.c|  2 +-
 6 files changed, 3 insertions(+), 43 deletions(-)
 delete mode 100644 arch/arm/mach-uniphier/early-pinctrl/Makefile
 delete mode 100644 arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ld20.c

diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile
index af56d6f..df6888f 100644
--- a/arch/arm/mach-uniphier/Makefile
+++ b/arch/arm/mach-uniphier/Makefile
@@ -4,7 +4,7 @@
 
 ifdef CONFIG_SPL_BUILD
 
-obj-y += init/ bcu/ memconf/ pll/ early-clk/ early-pinctrl/
+obj-y += init/ bcu/ memconf/ pll/ early-clk/
 obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/
 
 else
diff --git a/arch/arm/mach-uniphier/early-pinctrl/Makefile 
b/arch/arm/mach-uniphier/early-pinctrl/Makefile
deleted file mode 100644
index 84040c6..000
--- a/arch/arm/mach-uniphier/early-pinctrl/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-$(CONFIG_ARCH_UNIPHIER_LD11)   += early-pinctrl-ld20.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD20)   += early-pinctrl-ld20.o
diff --git a/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ld20.c 
b/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ld20.c
deleted file mode 100644
index 537deaf..000
--- a/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ld20.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright (C) 2016 Masahiro Yamada 
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#include "../init.h"
-#include "../sg-regs.h"
-
-int uniphier_ld20_early_pin_init(const struct uniphier_board_data *bd)
-{
-   /* Comment format:PAD Name -> Function Name */
-   sg_set_pinsel(0, 0, 8, 4);  /* XECS1  -> XECS1 */
-   sg_set_pinsel(1, 0, 8, 4);  /* ERXW   -> ERXW  */
-   sg_set_pinsel(2, 0, 8, 4);  /* XERWE1 -> XERWE1 */
-   sg_set_pinsel(6, 2, 8, 4);  /* XNFRE  -> XERWE0 */
-   sg_set_pinsel(7, 2, 8, 4);  /* XNFWE  -> ES0 */
-   sg_set_pinsel(8, 2, 8, 4);  /* NFALE  -> ES1 */
-   sg_set_pinsel(9, 2, 8, 4);  /* NFCLE  -> ES2 */
-   sg_set_pinsel(10, 2, 8, 4); /* NFD0   -> ED0 */
-   sg_set_pinsel(11, 2, 8, 4); /* NFD1   -> ED1 */
-   sg_set_pinsel(12, 2, 8, 4); /* NFD2   -> ED2 */
-   sg_set_pinsel(13, 2, 8, 4); /* NFD3   -> ED3 */
-   sg_set_pinsel(14, 2, 8, 4); /* NFD4   -> ED4 */
-   sg_set_pinsel(15, 2, 8, 4); /* NFD5   -> ED5 */
-   sg_set_pinsel(16, 2, 8, 4); /* NFD6   -> ED6 */
-   sg_set_pinsel(17, 2, 8, 4); /* NFD7   -> ED7 */
-   sg_set_iectrl_range(0, 2);
-   sg_set_iectrl_range(6, 17);
-
-   return 0;
-}
diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h
index 27b9a38..bc524a1 100644
--- a/arch/arm/mach-uniphier/init.h
+++ b/arch/arm/mach-uniphier/init.h
@@ -94,8 +94,6 @@ int uniphier_pxs2_early_clk_init(const struct 
uniphier_board_data *bd);
 int uniphier_ld11_early_clk_init(const struct uniphier_board_data *bd);
 int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd);
 
-int uniphier_ld20_early_pin_init(const struct uniphier_board_data *bd);
-
 int uniphier_ld4_umc_init(const struct uniphier_board_data *bd);
 int uniphier_pro4_umc_init(const struct uniphier_board_data *bd);
 int uniphier_sld8_umc_init(const struct uniphier_board_data *bd);
diff --git a/arch/arm/mach-uniphier/init/init-ld11.c 
b/arch/arm/mach-uniphier/init/init-ld11.c
index de2dc62..758df8d 100644
--- a/arch/arm/mach-uniphier/init/init-ld11.c
+++ b/arch/arm/mach-uniphier/init/init-ld11.c
@@ -15,7 +15,7 @@ int uniphier_ld11_init(const struct uniphier_board_data *bd)
 {
uniphier_sbc_init_savepin(bd);
uniphier_pxs2_sbc_init(bd);
-   uniphier_ld20_early_pin_init(bd);
+   uniphier_pin_init("system_bus_grp");
 
support_card_reset();
 
diff --git a/arch/arm/mach-uniphier/init/init-ld20.c 
b/arch/arm/mach-uniphier/init/init-ld20.c
index 7f66053..f23ca09 100644
--- a/arch/arm/mach-uniphier/init/init-ld20.c
+++ b/arch/arm/mach-uniphier/init/init-ld20.c
@@ -14,7 +14,7 @@ int uniphier_ld20_init(const struct uniphier_board_data *bd)
 {
uniphier_sbc_init_savepin(bd);
uniphier_pxs2_sbc_init(bd);
-   uniphier_ld20_early_pin_init(bd);
+   uniphier_pin_init("system_bus_grp");
 
support_card_reset();
 
-- 
1.9.1

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[U-Boot] [PATCH 03/15] ARM: dts: uniphier: add pinctrl device node and pinctrl properties

[Masahiro Yamada]

DT-side updates to make pinctrl on sLD3 SoC really available.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/dts/uniphier-ph1-sld3-ref.dts |  8 
 arch/arm/dts/uniphier-ph1-sld3.dtsi| 35 ++
 2 files changed, 43 insertions(+)

diff --git a/arch/arm/dts/uniphier-ph1-sld3-ref.dts 
b/arch/arm/dts/uniphier-ph1-sld3-ref.dts
index 0863588..f3e76b3 100644
--- a/arch/arm/dts/uniphier-ph1-sld3-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-sld3-ref.dts
@@ -93,3 +93,11 @@
  {
u-boot,dm-pre-reloc;
 };
+
+_uart0 {
+   u-boot,dm-pre-reloc;
+};
+
+_emmc {
+   u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi 
b/arch/arm/dts/uniphier-ph1-sld3.dtsi
index 6a95541..d8c44b7 100644
--- a/arch/arm/dts/uniphier-ph1-sld3.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi
@@ -90,6 +90,8 @@
status = "disabled";
reg = <0x54006800 0x40>;
interrupts = <0 33 4>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_uart0>;
clocks = <_clk>;
clock-frequency = <36864000>;
};
@@ -99,6 +101,8 @@
status = "disabled";
reg = <0x54006900 0x40>;
interrupts = <0 35 4>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_uart1>;
clocks = <_clk>;
clock-frequency = <36864000>;
};
@@ -108,6 +112,8 @@
status = "disabled";
reg = <0x54006a00 0x40>;
interrupts = <0 37 4>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_uart2>;
clocks = <_clk>;
clock-frequency = <36864000>;
};
@@ -231,6 +237,8 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 41 1>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_i2c0>;
clocks = <_clk>;
clock-frequency = <10>;
};
@@ -304,6 +312,9 @@
status = "disabled";
reg = <0x5a40 0x200>;
interrupts = <0 78 4>;
+   pinctrl-names = "default", "1.8v";
+   pinctrl-0 = <_emmc>;
+   pinctrl-1 = <_emmc_1v8>;
clocks = < 1>;
bus-width = <8>;
non-removable;
@@ -314,6 +325,9 @@
status = "disabled";
reg = <0x5a50 0x200>;
interrupts = <0 76 4>;
+   pinctrl-names = "default", "1.8v";
+   pinctrl-0 = <_sd>;
+   pinctrl-1 = <_sd_1v8>;
clocks = < 0>;
bus-width = <4>;
};
@@ -323,6 +337,8 @@
status = "disabled";
reg = <0x5a800100 0x100>;
interrupts = <0 80 4>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_usb0>;
clocks = < 3>, < 6>;
};
 
@@ -331,6 +347,8 @@
status = "disabled";
reg = <0x5a810100 0x100>;
interrupts = <0 81 4>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_usb1>;
clocks = < 4>, < 6>;
};
 
@@ -339,6 +357,8 @@
status = "disabled";
reg = <0x5a820100 0x100>;
interrupts = <0 82 4>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_usb2>;
clocks = < 5>, < 6>;
};
 
@@ -347,9 +367,22 @@
status = "disabled";
reg = <0x5a830100 0x100>;
interrupts = <0 83 4>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_usb3>;
clocks = < 7>, < 6>;
};
 
+   soc-glue@5f80 {
+   compatible = "simple-mfd", "syscon";
+   reg = <0x5f80 0x2000>;
+   u-boot,dm-pre-reloc;
+
+   pinctrl: pinctrl {
+   compatible = "socionext,uniphier-sld3-pinctrl";
+   u-boot,dm-pre-reloc;
+   };
+   };
+
aidet@f183 {
compatible = "simple-mfd", "syscon";
  

[U-Boot] [PATCH 12/15] ARM: uniphier: move PLL init code to U-Boot proper where possible

[Masahiro Yamada]

The PLL for the DRAM interface must be initialized in SPL, but the
others can be delayed until U-Boot proper.  Move them from SPL to
U-Boot proper to save the precious SPL memory footprint.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/board_init.c|   4 +
 arch/arm/mach-uniphier/clk/Makefile|   8 +-
 .../{pll/pll-spectrum-ld4.c => clk/dpll-tail.c}|   6 +-
 arch/arm/mach-uniphier/clk/pll-ld4.c   | 152 
 arch/arm/mach-uniphier/clk/pll-pro4.c  | 109 ++
 arch/arm/mach-uniphier/clk/pll-sld3.c  |  14 ++
 arch/arm/mach-uniphier/clk/pll.h   |  13 ++
 arch/arm/mach-uniphier/init.h  |  15 +-
 arch/arm/mach-uniphier/init/init-ld4.c |   6 +-
 arch/arm/mach-uniphier/init/init-pro4.c|   6 +-
 arch/arm/mach-uniphier/init/init-sld3.c|   6 +-
 arch/arm/mach-uniphier/init/init-sld8.c|   6 +-
 arch/arm/mach-uniphier/pll/Makefile|   8 +-
 arch/arm/mach-uniphier/pll/pll-init-ld4.c  | 157 +
 arch/arm/mach-uniphier/pll/pll-init-pro4.c | 113 +--
 arch/arm/mach-uniphier/pll/pll-init-sld3.c |   2 +-
 arch/arm/mach-uniphier/pll/pll-init-sld8.c | 150 +---
 arch/arm/mach-uniphier/pll/pll-spectrum-sld3.c |  22 ---
 18 files changed, 326 insertions(+), 471 deletions(-)
 rename arch/arm/mach-uniphier/{pll/pll-spectrum-ld4.c => clk/dpll-tail.c} (72%)
 create mode 100644 arch/arm/mach-uniphier/clk/pll-ld4.c
 create mode 100644 arch/arm/mach-uniphier/clk/pll-pro4.c
 create mode 100644 arch/arm/mach-uniphier/clk/pll-sld3.c
 create mode 100644 arch/arm/mach-uniphier/clk/pll.h
 delete mode 100644 arch/arm/mach-uniphier/pll/pll-spectrum-sld3.c

diff --git a/arch/arm/mach-uniphier/board_init.c 
b/arch/arm/mach-uniphier/board_init.c
index c9d3f28..a1c7541 100644
--- a/arch/arm/mach-uniphier/board_init.c
+++ b/arch/arm/mach-uniphier/board_init.c
@@ -65,6 +65,7 @@ int board_init(void)
case SOC_UNIPHIER_SLD3:
uniphier_nand_pin_init(true);
led_puts("U1");
+   uniphier_sld3_pll_init();
uniphier_ld4_clk_init();
break;
 #endif
@@ -72,6 +73,7 @@ int board_init(void)
case SOC_UNIPHIER_LD4:
uniphier_nand_pin_init(true);
led_puts("U1");
+   uniphier_ld4_pll_init();
uniphier_ld4_clk_init();
break;
 #endif
@@ -79,6 +81,7 @@ int board_init(void)
case SOC_UNIPHIER_PRO4:
uniphier_nand_pin_init(false);
led_puts("U1");
+   uniphier_pro4_pll_init();
uniphier_pro4_clk_init();
break;
 #endif
@@ -86,6 +89,7 @@ int board_init(void)
case SOC_UNIPHIER_SLD8:
uniphier_nand_pin_init(true);
led_puts("U1");
+   uniphier_ld4_pll_init();
uniphier_ld4_clk_init();
break;
 #endif
diff --git a/arch/arm/mach-uniphier/clk/Makefile 
b/arch/arm/mach-uniphier/clk/Makefile
index 1428e0c..b722781 100644
--- a/arch/arm/mach-uniphier/clk/Makefile
+++ b/arch/arm/mach-uniphier/clk/Makefile
@@ -2,10 +2,10 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-$(CONFIG_ARCH_UNIPHIER_SLD3)   += clk-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD4)+= clk-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PRO4)   += clk-pro4.o
-obj-$(CONFIG_ARCH_UNIPHIER_SLD8)   += clk-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD3)   += clk-ld4.o pll-sld3.o dpll-tail.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD4)+= clk-ld4.o pll-ld4.o 
dpll-tail.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO4)   += clk-pro4.o pll-pro4.o dpll-tail.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD8)   += clk-ld4.o pll-ld4.o dpll-tail.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)   += clk-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)   += clk-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)   += clk-pxs2.o
diff --git a/arch/arm/mach-uniphier/pll/pll-spectrum-ld4.c 
b/arch/arm/mach-uniphier/clk/dpll-tail.c
similarity index 72%
rename from arch/arm/mach-uniphier/pll/pll-spectrum-ld4.c
rename to arch/arm/mach-uniphier/clk/dpll-tail.c
index dc97697..49db555 100644
--- a/arch/arm/mach-uniphier/pll/pll-spectrum-ld4.c
+++ b/arch/arm/mach-uniphier/clk/dpll-tail.c
@@ -6,16 +6,14 @@
 
 #include 
 
-#include "../init.h"
 #include "../sc-regs.h"
+#include "pll.h"
 
-int uniphier_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd)
+void uniphier_ld4_dpll_ssc_en(void)
 {
u32 tmp;
 
tmp = readl(SC_DPLLCTRL);
tmp |= SC_DPLLCTRL_SSC_EN;
writel(tmp, SC_DPLLCTRL);
-
-   return 0;
 }
diff --git a/arch/arm/mach-uniphier/clk/pll-ld4.c 
b/arch/arm/mach-uniphier/clk/pll-ld4.c
new file mode 100644
index 000..b436e7a
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/pll-ld4.c
@@ -0,0 

[U-Boot] [PATCH 00/15] ARM: uniphier: more updates for UniPhier SoC family for v2016.11-rc1

[Masahiro Yamada]

 - Add pinctrl driver for sLD3 SoC
 - Do away with legacy pin-mux code
 - refactoring of clock/PLL init code
 - Add PLL init code for LD20 SoC
 - Improvement of DRAM init code for LD20 SoC
 - Misc cleanups



Masahiro Yamada (15):
  pinctrl: uniphier: support 4bit-width pin-mux register capability
  pinctrl: uniphier: add UniPhier sLD3 pinctrl driver
  ARM: dts: uniphier: add pinctrl device node and pinctrl properties
  ARM: uniphier: select PINCTRL and SPL_PINCTRL
  ARM: uniphier: remove redundant pin-muxing for EA24 pin of sLD3 SoC
  ARM: uniphier: remove ad-hoc pin-mux code for sLD3
  ARM: uniphier: consolidate NAND pin-mux settings
  ARM: dts: uniphier: include System Bus pin group node in SPL DT
  ARM: uniphier: consolidate System Bus pin-mux settings for LD11/LD20
  ARM: uniphier: move XIRQ pin-mux settings of LD11/LD20
  ARM: uniphier: rename CONFIG_DPLL_SSC_RATE_1PER
  ARM: uniphier: move PLL init code to U-Boot proper where possible
  ARM: uniphier: collect clock/PLL init code into a single directory
  ARM: uniphier: add PLL init code for LD20 SoC
  ARM: uniphier: update DRAM init code for LD20 SoC

 arch/arm/Kconfig   |   2 +
 arch/arm/dts/uniphier-ph1-ld11-ref.dts |   4 +
 arch/arm/dts/uniphier-ph1-ld20-ref.dts |   4 +
 arch/arm/dts/uniphier-ph1-sld3-ref.dts |   8 +
 arch/arm/dts/uniphier-ph1-sld3.dtsi|  35 ++
 arch/arm/mach-uniphier/Makefile|   6 +-
 arch/arm/mach-uniphier/board_init.c|  46 ++-
 arch/arm/mach-uniphier/clk/Makefile|  28 +-
 arch/arm/mach-uniphier/clk/dpll-ld20.c |  22 ++
 arch/arm/mach-uniphier/clk/dpll-ld4.c  |  55 +++
 arch/arm/mach-uniphier/clk/dpll-pro4.c |  59 +++
 .../{pll/pll-init-sld3.c => clk/dpll-sld3.c}   |   2 +-
 arch/arm/mach-uniphier/clk/dpll-sld8.c |  61 +++
 .../{pll/pll-spectrum-ld4.c => clk/dpll-tail.c}|   6 +-
 .../{early-clk => clk}/early-clk-ld11.c|   0
 .../{early-clk => clk}/early-clk-ld20.c|   0
 .../{early-clk => clk}/early-clk-ld4.c |   0
 .../{early-clk => clk}/early-clk-pro5.c|   0
 .../{early-clk => clk}/early-clk-pxs2.c|   0
 arch/arm/mach-uniphier/clk/pll-base-ld20.c | 123 ++
 arch/arm/mach-uniphier/clk/pll-ld20.c  |  40 ++
 .../{pll/pll-init-ld4.c => clk/pll-ld4.c}  |  58 +--
 .../{pll/pll-init-pro4.c => clk/pll-pro4.c}|  61 +--
 arch/arm/mach-uniphier/clk/pll-sld3.c  |  14 +
 arch/arm/mach-uniphier/clk/pll.h   |  21 +
 arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h |  76 ++--
 arch/arm/mach-uniphier/dram/umc-ld20.c | 431 +++--
 arch/arm/mach-uniphier/early-clk/Makefile  |  13 -
 arch/arm/mach-uniphier/early-pinctrl/Makefile  |   7 -
 .../early-pinctrl/early-pinctrl-ld20.c |  32 --
 .../early-pinctrl/early-pinctrl-sld3.c |  28 --
 arch/arm/mach-uniphier/init.h  |  31 +-
 arch/arm/mach-uniphier/init/init-ld11.c|   2 +-
 arch/arm/mach-uniphier/init/init-ld20.c|   8 +-
 arch/arm/mach-uniphier/init/init-ld4.c |   6 +-
 arch/arm/mach-uniphier/init/init-pro4.c|   6 +-
 arch/arm/mach-uniphier/init/init-sld3.c|   8 +-
 arch/arm/mach-uniphier/init/init-sld8.c|   6 +-
 arch/arm/mach-uniphier/pinctrl-glue.c  |  32 ++
 arch/arm/mach-uniphier/pinctrl/Makefile|  13 -
 arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c  |  39 --
 arch/arm/mach-uniphier/pinctrl/pinctrl-ld4.c   |  35 --
 arch/arm/mach-uniphier/pinctrl/pinctrl-ld6b.c  |  35 --
 arch/arm/mach-uniphier/pinctrl/pinctrl-pro4.c  |  37 --
 arch/arm/mach-uniphier/pinctrl/pinctrl-pro5.c  |  37 --
 arch/arm/mach-uniphier/pinctrl/pinctrl-pxs2.c  |  35 --
 arch/arm/mach-uniphier/pinctrl/pinctrl-sld3.c  |  48 ---
 arch/arm/mach-uniphier/pinctrl/pinctrl-sld8.c  |  35 --
 arch/arm/mach-uniphier/pll/Makefile|   8 -
 arch/arm/mach-uniphier/pll/pll-init-sld8.c | 205 --
 arch/arm/mach-uniphier/pll/pll-spectrum-sld3.c |  22 --
 arch/arm/mach-uniphier/sc64-regs.h |  19 +
 configs/uniphier_ld11_defconfig|   2 -
 configs/uniphier_ld20_defconfig|   2 -
 configs/uniphier_ld4_sld8_defconfig|   2 -
 configs/uniphier_pro4_defconfig|   2 -
 configs/uniphier_pxs2_ld6b_defconfig   |   2 -
 drivers/pinctrl/uniphier/Kconfig   |   6 +
 drivers/pinctrl/uniphier/Makefile  |   1 +
 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c   |  20 +-
 drivers/pinctrl/uniphier/pinctrl-uniphier-sld3.c   | 128 ++
 drivers/pinctrl/uniphier/pinctrl-uniphier.h|   5 +-
 62 files changed, 1185 insertions(+), 894 deletions(-)
 create mode 100644 

[U-Boot] [PATCH 04/15] ARM: uniphier: select PINCTRL and SPL_PINCTRL

[Masahiro Yamada]

Now all UniPhier SoCs support a pinctrl driver.  Select (SPL_)PINCTRL
since it is mandatory even for base use.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/Kconfig | 2 ++
 configs/uniphier_ld11_defconfig  | 2 --
 configs/uniphier_ld20_defconfig  | 2 --
 configs/uniphier_ld4_sld8_defconfig  | 2 --
 configs/uniphier_pro4_defconfig  | 2 --
 configs/uniphier_pxs2_ld6b_defconfig | 2 --
 6 files changed, 2 insertions(+), 10 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 498658d..a311215 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -865,9 +865,11 @@ config ARCH_UNIPHIER
select DM_USB
select OF_CONTROL
select OF_LIBFDT
+   select PINCTRL
select SPL
select SPL_DM
select SPL_OF_CONTROL
+   select SPL_PINCTRL
select SUPPORT_SPL
help
  Support for UniPhier SoC family developed by Socionext Inc.
diff --git a/configs/uniphier_ld11_defconfig b/configs/uniphier_ld11_defconfig
index 703d871..e848d08 100644
--- a/configs/uniphier_ld11_defconfig
+++ b/configs/uniphier_ld11_defconfig
@@ -23,8 +23,6 @@ CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_GPIO_UNIPHIER=y
 CONFIG_MISC=y
 CONFIG_I2C_EEPROM=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/uniphier_ld20_defconfig b/configs/uniphier_ld20_defconfig
index c4a8547..d0e4bf0 100644
--- a/configs/uniphier_ld20_defconfig
+++ b/configs/uniphier_ld20_defconfig
@@ -24,8 +24,6 @@ CONFIG_GPIO_UNIPHIER=y
 CONFIG_MISC=y
 CONFIG_I2C_EEPROM=y
 CONFIG_MMC_UNIPHIER=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_STORAGE=y
diff --git a/configs/uniphier_ld4_sld8_defconfig 
b/configs/uniphier_ld4_sld8_defconfig
index 89d3de4..f9b6eb2 100644
--- a/configs/uniphier_ld4_sld8_defconfig
+++ b/configs/uniphier_ld4_sld8_defconfig
@@ -29,8 +29,6 @@ CONFIG_NAND_DENALI=y
 CONFIG_SYS_NAND_DENALI_64BIT=y
 CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
 CONFIG_SPL_NAND_DENALI=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
diff --git a/configs/uniphier_pro4_defconfig b/configs/uniphier_pro4_defconfig
index ddc582d..e76513a 100644
--- a/configs/uniphier_pro4_defconfig
+++ b/configs/uniphier_pro4_defconfig
@@ -28,8 +28,6 @@ CONFIG_NAND_DENALI=y
 CONFIG_SYS_NAND_DENALI_64BIT=y
 CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
 CONFIG_SPL_NAND_DENALI=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/uniphier_pxs2_ld6b_defconfig 
b/configs/uniphier_pxs2_ld6b_defconfig
index 131c416..6bc592e 100644
--- a/configs/uniphier_pxs2_ld6b_defconfig
+++ b/configs/uniphier_pxs2_ld6b_defconfig
@@ -29,8 +29,6 @@ CONFIG_NAND_DENALI=y
 CONFIG_SYS_NAND_DENALI_64BIT=y
 CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
 CONFIG_SPL_NAND_DENALI=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_STORAGE=y
-- 
1.9.1

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[U-Boot] [PATCH 11/15] ARM: uniphier: rename CONFIG_DPLL_SSC_RATE_1PER

[Masahiro Yamada]

Basically, this should not be configured by users.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/pll/pll-init-sld8.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-uniphier/pll/pll-init-sld8.c 
b/arch/arm/mach-uniphier/pll/pll-init-sld8.c
index b26106e..8b6a67c 100644
--- a/arch/arm/mach-uniphier/pll/pll-init-sld8.c
+++ b/arch/arm/mach-uniphier/pll/pll-init-sld8.c
@@ -36,7 +36,7 @@ static void dpll_init(void)
 */
tmp = readl(SC_DPLLCTRL);
tmp &= ~0x3ff07fff;
-#ifdef CONFIG_DPLL_SSC_RATE_1PER
+#ifdef DPLL_SSC_RATE_1PER
tmp |= 0x084018bf;
 #else
tmp |= 0x084031a6;
-- 
1.9.1

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[U-Boot] [PATCH 01/15] pinctrl: uniphier: support 4bit-width pin-mux register capability

[Masahiro Yamada]

On LD4 SoC or later, the pin-mux registers are 8bit wide, while 4bit
wide on sLD3 SoC.  Support it for the sLD3 pinctrl driver.

Signed-off-by: Masahiro Yamada 
---

 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 20 
 drivers/pinctrl/uniphier/pinctrl-uniphier.h  |  5 +++--
 2 files changed, 11 insertions(+), 14 deletions(-)

diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c 
b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
index f2fe313..51144b8 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
@@ -105,8 +105,10 @@ static void uniphier_pinmux_set_one(struct udevice *dev, 
unsigned pin,
int muxval)
 {
struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
-   unsigned mux_bits, reg_stride, reg, reg_end, shift, mask;
-   bool load_pinctrl;
+   unsigned reg, reg_end, shift, mask;
+   unsigned mux_bits = 8;
+   unsigned reg_stride = 4;
+   bool load_pinctrl = false;
u32 tmp;
 
/* some pins need input-enabling */
@@ -115,24 +117,18 @@ static void uniphier_pinmux_set_one(struct udevice *dev, 
unsigned pin,
if (muxval < 0)
return; /* dedicated pin; nothing to do for pin-mux */
 
+   if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_MUX_4BIT)
+   mux_bits = 4;
+
if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE) {
/*
 *  Mode   offsetbit
 *  Normal 4 * n shift+3:shift
 *  Debug  4 * n shift+7:shift+4
 */
-   mux_bits = 4;
+   mux_bits /= 2;
reg_stride = 8;
load_pinctrl = true;
-   } else {
-   /*
-*  Mode   offset   bit
-*  Normal 8 * nshift+3:shift
-*  Debug  8 * n + 4shift+3:shift
-*/
-   mux_bits = 8;
-   reg_stride = 4;
-   load_pinctrl = false;
}
 
reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride;
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier.h 
b/drivers/pinctrl/uniphier/pinctrl-uniphier.h
index 76ea1be..5c3db2a 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier.h
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier.h
@@ -67,8 +67,9 @@ struct uniphier_pinctrl_socdata {
const char * const *functions;
int functions_count;
unsigned caps;
-#define UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRLBIT(1)
-#define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE  BIT(0)
+#define UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRLBIT(2)
+#define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE  BIT(1)
+#define UNIPHIER_PINCTRL_CAPS_MUX_4BIT BIT(0)
 };
 
 #define UNIPHIER_PINCTRL_PIN(a, b) \
-- 
1.9.1

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[U-Boot] [PATCH 02/15] pinctrl: uniphier: add UniPhier sLD3 pinctrl driver

[Masahiro Yamada]

Add pin-mux support for UniPhier sLD3 SoC.

Signed-off-by: Masahiro Yamada 
---

 drivers/pinctrl/uniphier/Kconfig |   6 ++
 drivers/pinctrl/uniphier/Makefile|   1 +
 drivers/pinctrl/uniphier/pinctrl-uniphier-sld3.c | 128 +++
 3 files changed, 135 insertions(+)
 create mode 100644 drivers/pinctrl/uniphier/pinctrl-uniphier-sld3.c

diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig
index 7febea2..689e576 100644
--- a/drivers/pinctrl/uniphier/Kconfig
+++ b/drivers/pinctrl/uniphier/Kconfig
@@ -3,6 +3,12 @@ if ARCH_UNIPHIER
 config PINCTRL_UNIPHIER
bool
 
+config PINCTRL_UNIPHIER_SLD3
+   bool "UniPhier PH1-sLD3 SoC pinctrl driver"
+   depends on ARCH_UNIPHIER_SLD3
+   default y
+   select PINCTRL_UNIPHIER
+
 config PINCTRL_UNIPHIER_LD4
bool "UniPhier PH1-LD4 SoC pinctrl driver"
depends on ARCH_UNIPHIER_LD4
diff --git a/drivers/pinctrl/uniphier/Makefile 
b/drivers/pinctrl/uniphier/Makefile
index 4de251b..fd003ad 100644
--- a/drivers/pinctrl/uniphier/Makefile
+++ b/drivers/pinctrl/uniphier/Makefile
@@ -4,6 +4,7 @@
 
 obj-y  += pinctrl-uniphier-core.o
 
+obj-$(CONFIG_PINCTRL_UNIPHIER_SLD3)+= pinctrl-uniphier-sld3.o
 obj-$(CONFIG_PINCTRL_UNIPHIER_LD4) += pinctrl-uniphier-ld4.o
 obj-$(CONFIG_PINCTRL_UNIPHIER_PRO4)+= pinctrl-uniphier-pro4.o
 obj-$(CONFIG_PINCTRL_UNIPHIER_SLD8)+= pinctrl-uniphier-sld8.o
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld3.c 
b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld3.c
new file mode 100644
index 000..d3a507e
--- /dev/null
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld3.c
@@ -0,0 +1,128 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+
+#include "pinctrl-uniphier.h"
+
+static const unsigned emmc_pins[] = {55, 56, 60};
+static const int emmc_muxvals[] = {1, 1, 1};
+static const unsigned emmc_dat8_pins[] = {57};
+static const int emmc_dat8_muxvals[] = {1};
+static const unsigned ether_mii_pins[] = {35, 107, 108, 109, 110, 111, 112,
+ 113};
+static const int ether_mii_muxvals[] = {1, 2, 2, 2, 2, 2, 2, 2};
+static const unsigned ether_rmii_pins[] = {35};
+static const int ether_rmii_muxvals[] = {1};
+static const unsigned i2c0_pins[] = {36};
+static const int i2c0_muxvals[] = {0};
+static const unsigned nand_pins[] = {38, 39, 40, 58, 59};
+static const int nand_muxvals[] = {1, 1, 1, 1, 1};
+static const unsigned nand_cs1_pins[] = {41};
+static const int nand_cs1_muxvals[] = {1};
+static const unsigned sd_pins[] = {42, 43, 44, 45};
+static const int sd_muxvals[] = {1, 1, 1, 1};
+static const unsigned system_bus_pins[] = {46, 50, 51, 53, 54, 73, 74, 75, 76,
+  77, 78, 79, 80, 88, 89, 91, 92, 99};
+static const int system_bus_muxvals[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+1, 1, 1, 1, 1};
+static const unsigned system_bus_cs0_pins[] = {93};
+static const int system_bus_cs0_muxvals[] = {1};
+static const unsigned system_bus_cs1_pins[] = {94};
+static const int system_bus_cs1_muxvals[] = {1};
+static const unsigned system_bus_cs2_pins[] = {95};
+static const int system_bus_cs2_muxvals[] = {1};
+static const unsigned system_bus_cs3_pins[] = {96};
+static const int system_bus_cs3_muxvals[] = {1};
+static const unsigned system_bus_cs4_pins[] = {81};
+static const int system_bus_cs4_muxvals[] = {1};
+static const unsigned system_bus_cs5_pins[] = {82};
+static const int system_bus_cs5_muxvals[] = {1};
+static const unsigned uart0_pins[] = {63, 64};
+static const int uart0_muxvals[] = {0, 1};
+static const unsigned uart1_pins[] = {65, 66};
+static const int uart1_muxvals[] = {0, 1};
+static const unsigned uart2_pins[] = {96, 102};
+static const int uart2_muxvals[] = {2, 2};
+static const unsigned usb0_pins[] = {13, 14};
+static const int usb0_muxvals[] = {0, 1};
+static const unsigned usb1_pins[] = {15, 16};
+static const int usb1_muxvals[] = {0, 1};
+static const unsigned usb2_pins[] = {17, 18};
+static const int usb2_muxvals[] = {0, 1};
+static const unsigned usb3_pins[] = {19, 20};
+static const int usb3_muxvals[] = {0, 1};
+
+static const struct uniphier_pinctrl_group uniphier_sld3_groups[] = {
+   UNIPHIER_PINCTRL_GROUP_SPL(emmc),
+   UNIPHIER_PINCTRL_GROUP_SPL(emmc_dat8),
+   UNIPHIER_PINCTRL_GROUP(ether_mii),
+   UNIPHIER_PINCTRL_GROUP(ether_rmii),
+   UNIPHIER_PINCTRL_GROUP(i2c0),
+   UNIPHIER_PINCTRL_GROUP(nand),
+   UNIPHIER_PINCTRL_GROUP(nand_cs1),
+   UNIPHIER_PINCTRL_GROUP(sd),
+   UNIPHIER_PINCTRL_GROUP(system_bus),
+   UNIPHIER_PINCTRL_GROUP(system_bus_cs0),
+   UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
+   UNIPHIER_PINCTRL_GROUP(system_bus_cs2),
+   

Re: [U-Boot] [PATCH 04/15] net: mvneta: Add support for Armada 3700 SoC

[Joe Hershberger]

On Fri, Sep 16, 2016 at 8:09 AM, Stefan Roese  wrote:
> This patch adds support for the Armada 3700 SoC to the Marvell mvneta
> network driver.
>
> Not like A380, in Armada3700, there are two layers of decode windows for GBE:
> First layer is:  GbE Address window that resides inside the GBE unit,
> Second layer is: Fabric address window which is located in the NIC400
>  (South Fabric).
> To simplify the address decode configuration for Armada3700, we bypass the
> first layer of GBE decode window by setting the first window to 4GB.
>
> Signed-off-by: Stefan Roese 
> Cc: Nadav Haklai 
> Cc: Kostya Porotchkin 
> Cc: Wilson Ding 
> Cc: Victor Gu 
> Cc: Hua Jing 
> Cc: Terry Zhou 
> Cc: Hanna Hawa 
> Cc: Haim Boot 
> Cc: Joe Hershberger 
> ---
>  drivers/net/mvneta.c | 39 ++-
>  1 file changed, 38 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c
> index 433e186..2b98a92 100644
> --- a/drivers/net/mvneta.c
> +++ b/drivers/net/mvneta.c
> @@ -91,7 +91,10 @@ DECLARE_GLOBAL_DATA_PTR;
>  #define MVNETA_WIN_BASE(w)  (0x2200 + ((w) << 3))
>  #define MVNETA_WIN_SIZE(w)  (0x2204 + ((w) << 3))
>  #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
> +#define MVNETA_WIN_SIZE_MASK   (0x)
>  #define MVNETA_BASE_ADDR_ENABLE 0x2290
> +#define MVNETA_PORT_ACCESS_PROTECT  0x2294
> +#define  MVNETA_PORT_ACCESS_PROTECT_WIN0_RW0x3
>  #define MVNETA_PORT_CONFIG  0x2400
>  #define  MVNETA_UNI_PROMISC_MODEBIT(0)
>  #define  MVNETA_DEF_RXQ(q)  ((q) << 1)
> @@ -1241,6 +1244,36 @@ static int mvneta_init2(struct mvneta_port *pp)
>  }
>
>  /* platform glue : initialize decoding windows */
> +
> +/*
> + * Not like A380, in Armada3700, there are two layers of decode windows for 
> GBE:
> + * First layer is:  GbE Address window that resides inside the GBE unit,
> + * Second layer is: Fabric address window which is located in the NIC400
> + *  (South Fabric).
> + * To simplify the address decode configuration for Armada3700, we bypass the
> + * first layer of GBE decode window by setting the first window to 4GB.
> + */
> +static void mvneta_bypass_mbus_windows(struct mvneta_port *pp)
> +{
> +   u32 tmp_value;
> +
> +   /*
> +* Set window size to 4GB, to bypass GBE address decode, leave the
> +* work to MBUS decode window
> +*/
> +   mvreg_write(pp, MVNETA_WIN_SIZE(0), MVNETA_WIN_SIZE_MASK);
> +
> +   /* Enable GBE address decode window 0 by set bit 0 to 0 */
> +   tmp_value = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE);
> +   tmp_value = tmp_value & ~(1);

It would be good to have a defined name for this bitfield above like the others.

Also, you could use:

#define MVNETA_BASE_ADDR_ENABLE_BIT 0
clear_bit(MVNETA_BASE_ADDR_ENABLE_BIT, pp->base + MVNETA_BASE_ADDR_ENABLE);

> +   mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, tmp_value);
> +
> +   /* Set GBE address decode window 0 to full Access (read or write) */
> +   tmp_value = mvreg_read(pp, MVNETA_PORT_ACCESS_PROTECT);
> +   tmp_value = tmp_value | MVNETA_PORT_ACCESS_PROTECT_WIN0_RW;
> +   mvreg_write(pp, MVNETA_PORT_ACCESS_PROTECT, tmp_value);

Or:

setbits_le32(pp->base + MVNETA_PORT_ACCESS_PROTECT,
MVNETA_PORT_ACCESS_PROTECT_WIN0_RW)

> +}
> +
>  static void mvneta_conf_mbus_windows(struct mvneta_port *pp)
>  {
> const struct mbus_dram_target_info *dram;
> @@ -1609,7 +1642,10 @@ static int mvneta_probe(struct udevice *dev)
> pp->base = (void __iomem *)pdata->iobase;
>
> /* Configure MBUS address windows */
> -   mvneta_conf_mbus_windows(pp);
> +   if (of_device_is_compatible(dev, "marvell,armada-3700-neta"))
> +   mvneta_bypass_mbus_windows(pp);
> +   else
> +   mvneta_conf_mbus_windows(pp);
>
> /* PHY interface is already decoded in mvneta_ofdata_to_platdata() */
> pp->phy_interface = pdata->phy_interface;
> @@ -1672,6 +1708,7 @@ static int mvneta_ofdata_to_platdata(struct udevice 
> *dev)
>  static const struct udevice_id mvneta_ids[] = {
> { .compatible = "marvell,armada-370-neta" },
> { .compatible = "marvell,armada-xp-neta" },
> +   { .compatible = "marvell,armada-3700-neta" },
> { }
>  };
>
> --
> 2.9.3
>
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Re: [U-Boot] [PATCH 03/15] net: mvneta: Make driver 64bit safe

[Joe Hershberger]

On Fri, Sep 16, 2016 at 8:09 AM, Stefan Roese  wrote:
> The mvneta driver is also used on the ARMv8 64bit Armada 3700 SoC. This
> patch fixes the compilation warnings seen on this 64bit platform.
>
> Signed-off-by: Stefan Roese 
> Cc: Nadav Haklai 
> Cc: Kostya Porotchkin 
> Cc: Wilson Ding 
> Cc: Victor Gu 
> Cc: Hua Jing 
> Cc: Terry Zhou 
> Cc: Hanna Hawa 
> Cc: Haim Boot 
> Cc: Joe Hershberger 

Acked-by: Joe Hershberger 
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[U-Boot] [PATCH v5 4/5] colibri_t20: fix display configuration

[Marcel Ziswiler]

Without this patch the following error will be shown:

stdio_add_devices: Video device failed (ret=-22)

As commit ec5507707a1d1e84056a6c864338f95f6118d3ca (video: tegra: Move
to using simple-panel and pwm-backlight) states the Colibri T20 needs
updating too which this patch finally attempts doing.

Signed-off-by: Marcel Ziswiler 
Acked-by: Stephen Warren 

---

Changes in v5: None
Changes in v4:
- Add Stephen's ack.

Changes in v3:
- Get rid of dummy N/C GPIO work around now as the fixed regulator
  properly honours optionality of enable GPIO.

Changes in v2:
- Rename dummy regulator to reg_3v3 as suggested by Stephen.
- Keep dummy N/C GPIO to work around bug in U-Boot regulator driver
  requiring such node despite its binding claiming it being optional.

 arch/arm/dts/tegra20-colibri.dts | 71 +---
 1 file changed, 51 insertions(+), 20 deletions(-)

diff --git a/arch/arm/dts/tegra20-colibri.dts b/arch/arm/dts/tegra20-colibri.dts
index 2cf24d3..5b803d9 100644
--- a/arch/arm/dts/tegra20-colibri.dts
+++ b/arch/arm/dts/tegra20-colibri.dts
@@ -21,12 +21,24 @@
};
 
host1x@5000 {
-   status = "okay";
dc@5420 {
-   status = "okay";
rgb {
status = "okay";
nvidia,panel = <_panel>;
+   display-timings {
+   timing@0 {
+   /* VESA VGA */
+   clock-frequency = <25175000>;
+   hactive = <640>;
+   vactive = <480>;
+   hback-porch = <48>;
+   hfront-porch = <16>;
+   hsync-len = <96>;
+   vback-porch = <31>;
+   vfront-porch = <11>;
+   vsync-len = <2>;
+   };
+   };
};
};
};
@@ -60,6 +72,10 @@
};
};
 
+   pwm@7000a000 {
+   status = "okay";
+   };
+
/*
 * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
 * board)
@@ -91,6 +107,18 @@
cd-gpios = < TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
};
 
+   backlight: backlight {
+   compatible = "pwm-backlight";
+
+   brightness-levels = <255 128 64 32 16 8 4 0>;
+   default-brightness-level = <6>;
+   /* BL_ON */
+   enable-gpios = < TEGRA_GPIO(T, 4) GPIO_ACTIVE_HIGH>;
+   power-supply = <_3v3>;
+   /* PWM */
+   pwms = < 0 500>;
+   };
+
clocks {
compatible = "simple-bus";
#address-cells = <1>;
@@ -104,25 +132,28 @@
};
};
 
-   pwm: pwm@7000a000 {
-   status = "okay";
+   lcd_panel: panel {
+   /*
+* edt,et057090dhu: EDT 5.7" LCD TFT
+* edt,et070080dh6: EDT 7.0" LCD TFT
+*/
+   compatible = "edt,et057090dhu", "simple-panel";
+
+   backlight = <>;
};
 
-   lcd_panel: panel {
-   clock = <25175000>;
-   xres = <640>;
-   yres = <480>;
-   left-margin = <48>; /* horizontal back porch */
-   right-margin = <16>;/* horizontal front porch */
-   hsync-len = <96>;
-   lower-margin = <11>;/* vertical front porch */
-   upper-margin = <31>;/* vertical back porch */
-   vsync-len = <2>;
-   hsync-active-high;
-   vsync-active-high;
-   nvidia,bits-per-pixel = <16>;
-   nvidia,pwm = < 0 0>;
-   nvidia,backlight-enable-gpios = < TEGRA_GPIO(T, 4) 
GPIO_ACTIVE_HIGH>;
-   nvidia,panel-timings = <0 0 0 0>;
+   regulators {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   reg_3v3: regulator@0 {
+   compatible = "regulator-fixed";
+   reg = <0>;
+   regulator-name = "+V3.3";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-always-on;
+   };
};
 };
-- 
2.5.5

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[U-Boot] [PATCH v5 5/5] colibri_t20: fix usb operation and controller order

[Marcel Ziswiler]

Without this patch the following error will be shown:

Colibri T20 # usb start
starting USB...
No controllers found

This patch fixes USB operation and also the controller order as the
CI UDC driver may only be instantiated on the first aka OTG port.

Signed-off-by: Marcel Ziswiler 
Acked-by: Stephen Warren 

---

Changes in v5: None
Changes in v4: None
Changes in v3:
- Add Stephen's ack.

Changes in v2:
- As suggested by Stephen remove last patch 5/5 colibri_t20: enable dfu
  also for nand.

 arch/arm/dts/tegra20-colibri.dts | 45 +---
 1 file changed, 24 insertions(+), 21 deletions(-)

diff --git a/arch/arm/dts/tegra20-colibri.dts b/arch/arm/dts/tegra20-colibri.dts
index 5b803d9..6bc8c49 100644
--- a/arch/arm/dts/tegra20-colibri.dts
+++ b/arch/arm/dts/tegra20-colibri.dts
@@ -14,10 +14,10 @@
i2c0 = "/i2c@7000d000";
i2c1 = "/i2c@7000c000";
i2c2 = "/i2c@7000c400";
-   usb0 = "/usb@c5008000";
-   usb1 = "/usb@c500";
-   usb2 = "/usb@c5004000";
sdhci0 = "/sdhci@c8000600";
+   usb0 = "/usb@c500";
+   usb1 = "/usb@c5004000"; /* on-module only, for ASIX */
+   usb2 = "/usb@c5008000";
};
 
host1x@5000 {
@@ -43,24 +43,6 @@
};
};
 
-   usb@c500 {
-   statuc = "okay";
-   dr_mode = "otg";
-   };
-
-   usb@c5004000 {
-   statuc = "okay";
-   /* VBUS_LAN */
-   nvidia,phy-reset-gpio = < TEGRA_GPIO(V, 1) 
GPIO_ACTIVE_HIGH>;
-   nvidia,vbus-gpio = < TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
-   };
-
-   usb@c5008000 {
-   statuc = "okay";
-   /* USBH_PEN */
-   nvidia,vbus-gpio = < TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
-   };
-
nand-controller@70008000 {
nvidia,wp-gpios = < TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
nvidia,width = <8>;
@@ -101,6 +83,27 @@
clock-frequency = <10>;
};
 
+   /* EHCI instance 0: USB1_DP/N -> USBC_P/N */
+   usb@c500 {
+   status = "okay";
+   dr_mode = "otg";
+   };
+
+   /* EHCI instance 1: ULPI -> USB3340 -> AX88772B */
+   usb@c5004000 {
+   status = "okay";
+   /* VBUS_LAN */
+   nvidia,phy-reset-gpio = < TEGRA_GPIO(V, 1) 
GPIO_ACTIVE_HIGH>;
+   nvidia,vbus-gpio = < TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
+   };
+
+   /* EHCI instance 2: USB3_DP/N -> USBH_P/N */
+   usb@c5008000 {
+   status = "okay";
+   /* USBH_PEN */
+   nvidia,vbus-gpio = < TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
+   };
+
sdhci@c8000600 {
status = "okay";
bus-width = <4>;
-- 
2.5.5

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[U-Boot] [PATCH v5 0/5] various fixes mainly for colibri_t20

[Marcel Ziswiler]

This series addresses various issues as seen on Colibri T20. Please
note that for successful Ethernet operation not only on Colibri T20
but also on Colibri T30 the following patch will still be required
already waiting in Marek's usb tree:

[PATCH v2] net: asix: Fix ASIX 88772B with driver model

https://www.mail-archive.com/u-boot@lists.denx.de/msg224349.html

Changes in v5:
- Remove DEBUG define.
- Put the " - not found! Error" back into the debug message as
  suggested by Stephen.
- Add Stephen's ack.

Changes in v4:
- Use full regulator rather than reg wording again in debug message as
  suggested by Przemyslaw.
- Tighten up error handling as suggested by John.
- Fix set_enable() as suggested by Stephen.
- Add Stephen's ack.

Changes in v3:
- Add Stephen's ack.
- Introduce new patch to honour optionality of fixed regulator enable
  GPIO.
- Get rid of dummy N/C GPIO work around now as the fixed regulator
  properly honours optionality of enable GPIO.
- Add Stephen's ack.

Changes in v2:
- As suggested by Stephen gating the CONFIG_CI_UDC_HAS_HOSTPC define
  with CONFIG_TEGRA20 rather than duplicating the same into all other
  SoC type specific header files.
- Add Anatolij's ack.
- Rename dummy regulator to reg_3v3 as suggested by Stephen.
- Keep dummy N/C GPIO to work around bug in U-Boot regulator driver
  requiring such node despite its binding claiming it being optional.
- As suggested by Stephen remove last patch 5/5 colibri_t20: enable dfu
  also for nand.

Marcel Ziswiler (5):
  tegra: usb gadget: fix ci udc operation if not hostpc capable
  simple panel: fix spelling of debug message
  regulator: fixed: honour optionality of enable gpio
  colibri_t20: fix display configuration
  colibri_t20: fix usb operation and controller order

 arch/arm/dts/tegra20-colibri.dts  | 116 +++---
 drivers/power/regulator/fixed.c   |  21 --
 drivers/video/simple_panel.c  |   2 +-
 include/configs/tegra-common-usb-gadget.h |   2 +
 4 files changed, 93 insertions(+), 48 deletions(-)

-- 
2.5.5

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[U-Boot] [PATCH v5 3/5] regulator: fixed: honour optionality of enable gpio

[Marcel Ziswiler]

According to the binding documentation the fixed regulator enable GPIO
is optional. However so far registration thereof failed if no enable
GPIO was specified. Fix this by making it entirely optional whether an
enable GPIO is used.

Signed-off-by: Marcel Ziswiler 
Acked-by: Stephen Warren 

---

Changes in v5:
- Remove DEBUG define.
- Put the " - not found! Error" back into the debug message as
  suggested by Stephen.
- Add Stephen's ack.

Changes in v4:
- Use full regulator rather than reg wording again in debug message as
  suggested by Przemyslaw.
- Tighten up error handling as suggested by John.
- Fix set_enable() as suggested by Stephen.

Changes in v3:
- Introduce new patch to honour optionality of fixed regulator enable
  GPIO.

Changes in v2: None

 drivers/power/regulator/fixed.c | 21 +++--
 1 file changed, 15 insertions(+), 6 deletions(-)

diff --git a/drivers/power/regulator/fixed.c b/drivers/power/regulator/fixed.c
index 37b8400..62dc47f 100644
--- a/drivers/power/regulator/fixed.c
+++ b/drivers/power/regulator/fixed.c
@@ -37,11 +37,15 @@ static int fixed_regulator_ofdata_to_platdata(struct 
udevice *dev)
/* Set type to fixed */
uc_pdata->type = REGULATOR_TYPE_FIXED;
 
-   /* Get fixed regulator gpio desc */
+   /* Get fixed regulator optional enable GPIO desc */
gpio = _pdata->gpio;
ret = gpio_request_by_name(dev, "gpio", 0, gpio, GPIOD_IS_OUT);
-   if (ret)
-   debug("Fixed regulator gpio - not found! Error: %d", ret);
+   if (ret) {
+   debug("Fixed regulator optional enable GPIO - not found! Error: 
%d\n",
+ ret);
+   if (ret != -ENOENT)
+   return ret;
+   }
 
/* Get optional ramp up delay */
dev_pdata->startup_delay_us = fdtdec_get_uint(gd->fdt_blob,
@@ -87,8 +91,9 @@ static bool fixed_regulator_get_enable(struct udevice *dev)
 {
struct fixed_regulator_platdata *dev_pdata = dev_get_platdata(dev);
 
+   /* Enable GPIO is optional */
if (!dev_pdata->gpio.dev)
-   return false;
+   return true;
 
return dm_gpio_get_value(_pdata->gpio);
 }
@@ -98,8 +103,12 @@ static int fixed_regulator_set_enable(struct udevice *dev, 
bool enable)
struct fixed_regulator_platdata *dev_pdata = dev_get_platdata(dev);
int ret;
 
-   if (!dev_pdata->gpio.dev)
-   return -ENOSYS;
+   /* Enable GPIO is optional */
+   if (!dev_pdata->gpio.dev) {
+   if (!enable)
+   return -ENOSYS;
+   return 0;
+   }
 
ret = dm_gpio_set_value(_pdata->gpio, enable);
if (ret) {
-- 
2.5.5

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[U-Boot] [PATCH v5 1/5] tegra: usb gadget: fix ci udc operation if not hostpc capable

[Marcel Ziswiler]

The Tegra 2 aka T20 is not host PC capable. Therefore gate the define
CONFIG_CI_UDC_HAS_HOSTPC in tegra-common-usb-gadget.h in case of
CONFIG_TEGRA20.

Signed-off-by: Marcel Ziswiler 
Acked-by: Stephen Warren 

---

Changes in v5: None
Changes in v4: None
Changes in v3:
- Add Stephen's ack.

Changes in v2:
- As suggested by Stephen gating the CONFIG_CI_UDC_HAS_HOSTPC define
  with CONFIG_TEGRA20 rather than duplicating the same into all other
  SoC type specific header files.

 include/configs/tegra-common-usb-gadget.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/configs/tegra-common-usb-gadget.h 
b/include/configs/tegra-common-usb-gadget.h
index 3e3eeea..2e492c1 100644
--- a/include/configs/tegra-common-usb-gadget.h
+++ b/include/configs/tegra-common-usb-gadget.h
@@ -10,7 +10,9 @@
 
 #ifndef CONFIG_SPL_BUILD
 /* USB gadget mode support*/
+#ifndef CONFIG_TEGRA20
 #define CONFIG_CI_UDC_HAS_HOSTPC
+#endif
 /* USB mass storage protocol */
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 /* DFU protocol */
-- 
2.5.5

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[U-Boot] [PATCH v5 2/5] simple panel: fix spelling of debug message

[Marcel Ziswiler]

Fix spelling of debug message from cnnot to cannot.

Signed-off-by: Marcel Ziswiler 
Acked-by: Anatolij Gustschin 

---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Add Anatolij's ack.

 drivers/video/simple_panel.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/video/simple_panel.c b/drivers/video/simple_panel.c
index b2fe345..baa95f6 100644
--- a/drivers/video/simple_panel.c
+++ b/drivers/video/simple_panel.c
@@ -42,7 +42,7 @@ static int simple_panel_ofdata_to_platdata(struct udevice 
*dev)
ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
   "power-supply", >reg);
if (ret) {
-   debug("%s: Warning: cnnot get power supply: ret=%d\n",
+   debug("%s: Warning: cannot get power supply: ret=%d\n",
  __func__, ret);
if (ret != -ENOENT)
return ret;
-- 
2.5.5

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[U-Boot] [PATCH 3/5] toradex: config block handling

[Marcel Ziswiler]

Add Toradex factory configuration block handling. The config block is a
data structure which gets stored to flash during production testing. The
structure holds such information as board resp. hardware revision,
product ID and serial number which is used as the NIC part of the
Ethernet MAC address as well. The config block will be read upon boot by
the checkboard() function, displayed as part of the board information
and passed to Linux via device tree or ATAGs.

Signed-off-by: Marcel Ziswiler 
---

 arch/arm/Kconfig   |   1 +
 board/toradex/common/Kconfig   |  73 +
 board/toradex/common/Makefile  |   4 +
 board/toradex/common/common.c  | 179 
 board/toradex/common/common.h  |  13 +
 board/toradex/common/common.mk |   8 +
 board/toradex/common/configblock.c | 545 +
 board/toradex/common/configblock.h |  68 +
 8 files changed, 891 insertions(+)
 create mode 100644 board/toradex/common/Kconfig
 create mode 100644 board/toradex/common/Makefile
 create mode 100644 board/toradex/common/common.c
 create mode 100644 board/toradex/common/common.h
 create mode 100644 board/toradex/common/common.mk
 create mode 100644 board/toradex/common/configblock.c
 create mode 100644 board/toradex/common/configblock.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e63309a..b868830 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1035,6 +1035,7 @@ source "board/ti/ti816x/Kconfig"
 source "board/timll/devkit3250/Kconfig"
 source "board/toradex/colibri_pxa270/Kconfig"
 source "board/toradex/colibri_vf/Kconfig"
+source "board/toradex/common/Kconfig"
 source "board/technologic/ts4800/Kconfig"
 source "board/vscom/baltos/Kconfig"
 source "board/woodburn/Kconfig"
diff --git a/board/toradex/common/Kconfig b/board/toradex/common/Kconfig
new file mode 100644
index 000..363ccad
--- /dev/null
+++ b/board/toradex/common/Kconfig
@@ -0,0 +1,73 @@
+menuconfig TRDX_CFG_BLOCK
+   bool "Enable Toradex config block support"
+   select OF_BOARD_SETUP
+   help
+ The Toradex config block stored production data on the on-module
+ flash device (NAND, NOR or eMMC). The area is normally preserved by
+ software and contains the serial number (out of which the MAC
+ address is generated) and the exact module type.
+
+# Helper config to determine the correct default location of the cfg block
+config TRDX_HAVE_MMC
+   bool
+
+config TRDX_HAVE_NAND
+   bool
+
+config TRDX_HAVE_NOR
+   bool
+
+if TRDX_CFG_BLOCK
+
+choice
+   prompt "Toradex config block location"
+   depends on TRDX_CFG_BLOCK
+   default TRDX_CFG_BLOCK_IS_IN_MMC if TRDX_HAVE_MMC
+   default TRDX_CFG_BLOCK_IS_IN_NAND if TRDX_HAVE_NAND
+   default TRDX_CFG_BLOCK_IS_IN_NOR if TRDX_HAVE_NOR
+   help
+ Configure the location of the Toradex config block. By default, the
+ factory version of the Toradex config block is on the NAND, NOR or
+ eMMC flash device on the module.
+
+config TRDX_CFG_BLOCK_IS_IN_MMC
+   bool "Location of the config block is in eMMC"
+
+config TRDX_CFG_BLOCK_IS_IN_NAND
+   bool "Location of the config block is in NAND"
+
+config TRDX_CFG_BLOCK_IS_IN_NOR
+   bool "Location of the config block is in NOR"
+
+endchoice
+
+config TRDX_CFG_BLOCK_DEV
+   int "Toradex config block eMMC device ID"
+   depends on TRDX_CFG_BLOCK_IS_IN_MMC
+
+config TRDX_CFG_BLOCK_PART
+   int "Toradex config block eMMC partition ID"
+   depends on TRDX_CFG_BLOCK_IS_IN_MMC
+
+config TRDX_CFG_BLOCK_OFFSET
+   int "Toradex config block offset"
+   help
+ Specify the byte offset of the Toradex config block within the flash
+ device the config block is stored on.
+
+config TRDX_CFG_BLOCK_OFFSET2
+   int "Toradex config block offset, second instance"
+   default 0
+   help
+ Specify the byte offset of the 2nd instance of the Toradex config 
block
+ within the flash device the config block is stored on.
+ Set to 0 on modules which have no 2nd instance.
+
+config TRDX_CFG_BLOCK_2ND_ETHADDR
+   bool "Set the second Ethernet address"
+   help
+ For each serial number two Ethernet addresses are available for dual
+ Ethernet carrier boards. This options enables the code to set the
+ second Ethernet address as environment variable (eth1addr).
+
+endif
diff --git a/board/toradex/common/Makefile b/board/toradex/common/Makefile
new file mode 100644
index 000..e3b2651
--- /dev/null
+++ b/board/toradex/common/Makefile
@@ -0,0 +1,4 @@
+# Copyright (c) 2011 The Chromium OS Authors.
+# SPDX-License-Identifier: GPL-2.0+
+
+include $(src)/common.mk
diff --git a/board/toradex/common/common.c b/board/toradex/common/common.c
new file mode 100644
index 000..e2361c4
--- /dev/null
+++ b/board/toradex/common/common.c
@@ -0,0 +1,179 @@
+/*
+ * Copyright (c) 2016 

[U-Boot] [PATCH 4/5] apalis/colibri_imx7/pxa270/t20/t30/vf: integrate config block handling

[Marcel Ziswiler]

With our common code in place actually make use of it across all our
modules.

Signed-off-by: Marcel Ziswiler 
---

 board/toradex/apalis_t30/Kconfig  | 16 
 board/toradex/apalis_t30/apalis_t30.c | 12 +++-
 board/toradex/colibri_imx7/Kconfig| 14 ++
 board/toradex/colibri_pxa270/Kconfig  |  9 +
 board/toradex/colibri_pxa270/colibri_pxa270.c |  8 
 board/toradex/colibri_t20/Kconfig |  9 +
 board/toradex/colibri_t20/colibri_t20.c   | 13 +
 board/toradex/colibri_t30/Kconfig | 16 
 board/toradex/colibri_t30/colibri_t30.c   |  9 -
 board/toradex/colibri_vf/Kconfig  | 12 
 include/configs/apalis_t30.h  |  5 +++--
 include/configs/colibri_imx7.h|  6 +-
 include/configs/colibri_pxa270.h  |  7 +--
 include/configs/colibri_t20.h |  3 ++-
 include/configs/colibri_t30.h |  5 +++--
 include/configs/colibri_vf.h  |  8 +---
 16 files changed, 139 insertions(+), 13 deletions(-)

diff --git a/board/toradex/apalis_t30/Kconfig b/board/toradex/apalis_t30/Kconfig
index f1dcda5..1abcdf2 100644
--- a/board/toradex/apalis_t30/Kconfig
+++ b/board/toradex/apalis_t30/Kconfig
@@ -9,4 +9,20 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
default "apalis_t30"
 
+config TRDX_CFG_BLOCK
+   default y
+
+config TRDX_HAVE_MMC
+   default y
+
+config TRDX_CFG_BLOCK_DEV
+   default "0"
+
+config TRDX_CFG_BLOCK_PART
+   default "1"
+
+# Toradex Configblock in eMMC, at the end of 1st "boot sector"
+config TRDX_CFG_BLOCK_OFFSET
+   default "-512"
+
 endif
diff --git a/board/toradex/apalis_t30/apalis_t30.c 
b/board/toradex/apalis_t30/apalis_t30.c
index 3f56971..bf13053 100644
--- a/board/toradex/apalis_t30/apalis_t30.c
+++ b/board/toradex/apalis_t30/apalis_t30.c
@@ -1,5 +1,5 @@
 /*
- *  (C) Copyright 2014
+ *  (C) Copyright 2014-2016
  *  Marcel Ziswiler 
  *
  * SPDX-License-Identifier:GPL-2.0+
@@ -17,6 +17,8 @@
 
 #include "pinmux-config-apalis_t30.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define PMU_I2C_ADDRESS0x2D
 #define MAX_I2C_RETRY  3
 
@@ -29,6 +31,14 @@ int arch_misc_init(void)
return 0;
 }
 
+int checkboard_fallback(void)
+{
+   printf("Model: Toradex Apalis T30 %dGB\n",
+  (gd->ram_size == 0x4000) ? 1 : 2);
+
+   return 0;
+}
+
 /*
  * Routine: pinmux_init
  * Description: Do individual peripheral pinmux configs
diff --git a/board/toradex/colibri_imx7/Kconfig 
b/board/toradex/colibri_imx7/Kconfig
index 7bba26b..5012616 100644
--- a/board/toradex/colibri_imx7/Kconfig
+++ b/board/toradex/colibri_imx7/Kconfig
@@ -16,5 +16,19 @@ config COLIBRI_IMX7_EXT_PHYCLK
  clock source.
default y
 
+config TRDX_CFG_BLOCK
+   default y
+
+config TRDX_HAVE_NAND
+   default y
+
+config TRDX_CFG_BLOCK_OFFSET
+   default "2048"
+
+config TRDX_CFG_BLOCK_OFFSET2
+   default "133120"
+
+config TRDX_CFG_BLOCK_2ND_ETHADDR
+   default y
 
 endif
diff --git a/board/toradex/colibri_pxa270/Kconfig 
b/board/toradex/colibri_pxa270/Kconfig
index 949407a..c301159 100644
--- a/board/toradex/colibri_pxa270/Kconfig
+++ b/board/toradex/colibri_pxa270/Kconfig
@@ -9,4 +9,13 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
default "colibri_pxa270"
 
+config TRDX_CFG_BLOCK
+   default y
+
+config TRDX_HAVE_NOR
+   default y
+
+config TRDX_CFG_BLOCK_OFFSET
+   default "262144"
+
 endif
diff --git a/board/toradex/colibri_pxa270/colibri_pxa270.c 
b/board/toradex/colibri_pxa270/colibri_pxa270.c
index 3def0a6..5737363 100644
--- a/board/toradex/colibri_pxa270/colibri_pxa270.c
+++ b/board/toradex/colibri_pxa270/colibri_pxa270.c
@@ -2,6 +2,7 @@
  * Toradex Colibri PXA270 Support
  *
  * Copyright (C) 2010 Marek Vasut 
+ * Copyright (C) 2016 Marcel Ziswiler 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -32,6 +33,13 @@ int board_init(void)
return 0;
 }
 
+int checkboard_fallback(void)
+{
+   puts("Model: Toradex Colibri PXA270\n");
+
+   return 0;
+}
+
 int dram_init(void)
 {
pxa2xx_dram_init();
diff --git a/board/toradex/colibri_t20/Kconfig 
b/board/toradex/colibri_t20/Kconfig
index 7f373b2..9b68d5f 100644
--- a/board/toradex/colibri_t20/Kconfig
+++ b/board/toradex/colibri_t20/Kconfig
@@ -9,4 +9,13 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
default "colibri_t20"
 
+config TRDX_CFG_BLOCK
+   default y
+
+config TRDX_HAVE_NAND
+   default y
+
+config TRDX_CFG_BLOCK_OFFSET
+   default "3145728"
+
 endif
diff --git a/board/toradex/colibri_t20/colibri_t20.c 
b/board/toradex/colibri_t20/colibri_t20.c
index 68fbf49..24988eb 100644
--- a/board/toradex/colibri_t20/colibri_t20.c
+++ 

[U-Boot] [PATCH 5/5] apalis/colibri_t30: move environment location

[Marcel Ziswiler]

Now with the config block handling in place move the U-Boot environment
location before the config block at the end of 1st "boot sector" as
deployed during production using our downstream BSP.

Signed-off-by: Marcel Ziswiler 

---

 include/configs/apalis_t30.h  | 7 ---
 include/configs/colibri_t30.h | 7 ---
 2 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h
index a2e5252..3bcf6d0 100644
--- a/include/configs/apalis_t30.h
+++ b/include/configs/apalis_t30.h
@@ -34,11 +34,12 @@
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC
 
-/* Environment in eMMC, at the end of 2nd "boot sector" */
+/* Environment in eMMC, before config block at the end of 1st "boot sector" */
 #define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_ENV_OFFSET  (-CONFIG_ENV_SIZE)
+#define CONFIG_ENV_OFFSET  (-CONFIG_ENV_SIZE + \
+CONFIG_TRDX_CFG_BLOCK_OFFSET)
 #define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_SYS_MMC_ENV_PART2
+#define CONFIG_SYS_MMC_ENV_PART1
 
 /* USB host support */
 #define CONFIG_USB_EHCI
diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h
index 9e11393..324aa3b 100644
--- a/include/configs/colibri_t30.h
+++ b/include/configs/colibri_t30.h
@@ -34,11 +34,12 @@
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC
 
-/* Environment in eMMC, at the end of 2nd "boot sector" */
+/* Environment in eMMC, before config block at the end of 1st "boot sector" */
 #define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_ENV_OFFSET  (-CONFIG_ENV_SIZE)
+#define CONFIG_ENV_OFFSET  (-CONFIG_ENV_SIZE + \
+CONFIG_TRDX_CFG_BLOCK_OFFSET)
 #define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_SYS_MMC_ENV_PART2
+#define CONFIG_SYS_MMC_ENV_PART1
 
 /* USB host support */
 #define CONFIG_USB_EHCI
-- 
2.5.5

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[U-Boot] [PATCH 0/5] toradex: config block handling

[Marcel Ziswiler]

This series integrates Toradex factory configuration block handling. The
config block is a data structure which gets stored to flash during
production testing. The structure holds such information as board resp.
hardware revision, product ID and serial number which is used as the NIC
part of the Ethernet MAC address as well. The config block will be read
upon boot by the checkboard() function, displayed as part of the board
information and passed to Linux via device tree or ATAGs.


Marcel Ziswiler (5):
  colibri_imx7/vf: move to custom checkboard_fallback()
  apalis/colibri_t20/t30: deactivate displaying board info
  toradex: config block handling
  apalis/colibri_imx7/pxa270/t20/t30/vf: integrate config block handling
  apalis/colibri_t30: move environment location

 arch/arm/Kconfig  |   1 +
 board/toradex/apalis_t30/Kconfig  |  16 +
 board/toradex/apalis_t30/apalis_t30.c |  12 +-
 board/toradex/colibri_imx7/Kconfig|  14 +
 board/toradex/colibri_imx7/colibri_imx7.c |   6 +-
 board/toradex/colibri_pxa270/Kconfig  |   9 +
 board/toradex/colibri_pxa270/colibri_pxa270.c |   8 +
 board/toradex/colibri_t20/Kconfig |   9 +
 board/toradex/colibri_t20/colibri_t20.c   |  13 +
 board/toradex/colibri_t30/Kconfig |  16 +
 board/toradex/colibri_t30/colibri_t30.c   |   9 +-
 board/toradex/colibri_vf/Kconfig  |  12 +
 board/toradex/colibri_vf/colibri_vf.c |   8 +-
 board/toradex/common/Kconfig  |  73 
 board/toradex/common/Makefile |   4 +
 board/toradex/common/common.c | 179 +
 board/toradex/common/common.h |  13 +
 board/toradex/common/common.mk|   8 +
 board/toradex/common/configblock.c| 545 ++
 board/toradex/common/configblock.h|  68 
 include/configs/apalis_t30.h  |  13 +-
 include/configs/colibri_imx7.h|   6 +-
 include/configs/colibri_pxa270.h  |   7 +-
 include/configs/colibri_t20.h |   4 +-
 include/configs/colibri_t30.h |  13 +-
 include/configs/colibri_vf.h  |   8 +-
 26 files changed, 1048 insertions(+), 26 deletions(-)
 create mode 100644 board/toradex/common/Kconfig
 create mode 100644 board/toradex/common/Makefile
 create mode 100644 board/toradex/common/common.c
 create mode 100644 board/toradex/common/common.h
 create mode 100644 board/toradex/common/common.mk
 create mode 100644 board/toradex/common/configblock.c
 create mode 100644 board/toradex/common/configblock.h

-- 
2.5.5

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[U-Boot] [PATCH 1/5] colibri_imx7/vf: move to custom checkboard_fallback()

[Marcel Ziswiler]

Rename checkboard() to checkboard_fallback() in order to avoid a
name clash with our upcoming common implementation thereof.

Signed-off-by: Marcel Ziswiler 
---

 board/toradex/colibri_imx7/colibri_imx7.c | 6 +++---
 board/toradex/colibri_vf/colibri_vf.c | 8 
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/board/toradex/colibri_imx7/colibri_imx7.c 
b/board/toradex/colibri_imx7/colibri_imx7.c
index 8eedd65..73cd89c 100644
--- a/board/toradex/colibri_imx7/colibri_imx7.c
+++ b/board/toradex/colibri_imx7/colibri_imx7.c
@@ -377,10 +377,10 @@ int board_late_init(void)
return 0;
 }
 
-int checkboard(void)
+int checkboard_fallback(void)
 {
-   printf("Model: Toradex Colibri iMX7%c\n",
-  is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S');
+   printf("Model: Toradex Colibri iMX7%s\n",
+  is_cpu_type(MXC_CPU_MX7D) ? "D 512MB" : "S 256MB");
 
return 0;
 }
diff --git a/board/toradex/colibri_vf/colibri_vf.c 
b/board/toradex/colibri_vf/colibri_vf.c
index c65ccb3..c636a8e 100644
--- a/board/toradex/colibri_vf/colibri_vf.c
+++ b/board/toradex/colibri_vf/colibri_vf.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2015 Toradex, Inc.
+ * Copyright 2015-2016 Toradex, Inc.
  *
  * Based on vf610twr.c:
  * Copyright 2013 Freescale Semiconductor, Inc.
@@ -518,12 +518,12 @@ int board_init(void)
return 0;
 }
 
-int checkboard(void)
+int checkboard_fallback(void)
 {
if (is_colibri_vf61())
-   puts("Board: Colibri VF61\n");
+   puts("Model: Toradex Colibri VF61 256MB\n");
else
-   puts("Board: Colibri VF50\n");
+   puts("Model: Toradex Colibri VF50 128MB\n");
 
return 0;
 }
-- 
2.5.5

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[U-Boot] [PATCH 2/5] apalis/colibri_t20/t30: deactivate displaying board info

[Marcel Ziswiler]

Avoid a checkboard() name clash with our upcoming custom implementation
thereof.

Signed-off-by: Marcel Ziswiler 
---

 include/configs/apalis_t30.h  | 1 +
 include/configs/colibri_t20.h | 1 +
 include/configs/colibri_t30.h | 1 +
 3 files changed, 3 insertions(+)

diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h
index 3fc1779..dc17733 100644
--- a/include/configs/apalis_t30.h
+++ b/include/configs/apalis_t30.h
@@ -17,6 +17,7 @@
 
 /* High-level configuration options */
 #define CONFIG_TEGRA_BOARD_STRING  "Toradex Apalis T30"
+#undef CONFIG_DISPLAY_BOARDINFO/* As defined in tegra-common */
 
 /* Board-specific serial config */
 #define CONFIG_TEGRA_ENABLE_UARTA
diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h
index d9954c1..2764f8d 100644
--- a/include/configs/colibri_t20.h
+++ b/include/configs/colibri_t20.h
@@ -15,6 +15,7 @@
 
 /* High-level configuration options */
 #define CONFIG_TEGRA_BOARD_STRING  "Toradex Colibri T20"
+#undef CONFIG_DISPLAY_BOARDINFO/* As defined in tegra-common */
 
 /* Board-specific serial config */
 #define CONFIG_TEGRA_ENABLE_UARTA
diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h
index e2a2549..d83c5a0 100644
--- a/include/configs/colibri_t30.h
+++ b/include/configs/colibri_t30.h
@@ -17,6 +17,7 @@
 
 /* High-level configuration options */
 #define CONFIG_TEGRA_BOARD_STRING  "Toradex Colibri T30"
+#undef CONFIG_DISPLAY_BOARDINFO/* As defined in tegra-common */
 
 /* Board-specific serial config */
 #define CONFIG_TEGRA_ENABLE_UARTA
-- 
2.5.5

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Re: [U-Boot] [PATCH v4 3/5] regulator: fixed: honour optionality of enable gpio

[Stephen Warren]

On 09/16/2016 01:33 AM, Marcel Ziswiler wrote:

According to the binding documentation the fixed regulator enable GPIO
is optional. However so far registration thereof failed if no enable
GPIO was specified. Fix this by making it entirely optional whether an
enable GPIO is used.



diff --git a/drivers/power/regulator/fixed.c b/drivers/power/regulator/fixed.c



@@ -37,11 +39,14 @@ static int fixed_regulator_ofdata_to_platdata(struct 
udevice *dev)
/* Set type to fixed */
uc_pdata->type = REGULATOR_TYPE_FIXED;

-   /* Get fixed regulator gpio desc */
+   /* Get fixed regulator optional enable GPIO desc */
gpio = _pdata->gpio;
ret = gpio_request_by_name(dev, "gpio", 0, gpio, GPIOD_IS_OUT);
-   if (ret)
-   debug("Fixed regulator gpio - not found! Error: %d", ret);
+   if (ret) {
+   debug("Fixed regulator optional enable GPIO: %d\n", ret);
+   if (ret != -ENOENT)
+   return ret;


That message doesn't exactly make it obvious that it's describing a "not 
found" condition. Still, it is a debug() statement, so presumably anyone 
seeing the issue can just look at the code to see what's going on and 
work it out easily enough. So, aside from the DEBUG setting you already 
meantioned,


Acked-by: Stephen Warren 
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Re: [U-Boot] [PATCH v3] drivers: usb: xhci-fsl: Implement Erratum A-010151 for FSL USB3 controller

[Sriram Dash]

>From: Marek Vasut [mailto:ma...@denx.de]
>On 09/16/2016 11:35 AM, Sriram Dash wrote:
>
>[...]
>
 I agree to your point. We can set the bit from fsl specific file
 with the function setbits_le32(fsl_xhci->dwc3_reg->g_usb3pipectl[0],
 DWC3_GUSB3PIPECTL_DISRXDETP3);
 If any other Soc, other than fsl/nxp wants the functionality, they
 will be using the same in their respective code. What do you say?
>>>
>>> Why do you use setbits_le32() instead of writel() ?
>>>
>>
>> We will be modifying a single bit. So, better to use setbit_le32 and
>> leave other bits unchanged.
>
>In that case, you should use clrsetbits_le32() to clear the bit first in case 
>someone
>decided to clear it instead.
>

OK. Will modify in v4.

>[...]
>
>
>--
>Best regards,
>Marek Vasut
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[U-Boot] how to programatically add a second hash table to the environment?

[Robert P. J. Day]

  i'm hoping this is a simple question -- at boot time, i've added a
misc_init_r() routine that digs around in some legacy flash, pulls out
a string of (vxworks) "var=val" settings, and imports that in one shot
into an initial hash table. works fine.

  as the second step, i walk that table and, for the vxworks settings
i care about, i translate them to u-boot env variable names, possibly
massage the data values, and add those values to a *second* hash table
that now contains proper keys and values as u-boot would understand
them. (for example, vxworks would have "g=gateway", whereas i
translate that to "gatewayip=gateway" for the second hash table.)

  i now want to just add/overwrite the current u-boot environment with
what's in that second hash, and as i see it, i could just walk that
second hash and, for each ENTRY, do a call to hsearch_r() referring to
the hash table "env_htab", yes?

  i see no single call that allows me to combine hash tables, but it's
not as if i will have a lot of values to enter, so is that the right
approach -- just a short series of calls of the form:

  hsearch_r(entry, ENTER, , _htab, 0);

seems straightforward enough, just want to confirm i'm not overlooking
anything.

rday

-- 


Robert P. J. Day Ottawa, Ontario, CANADA
http://crashcourse.ca

Twitter:   http://twitter.com/rpjday
LinkedIn:   http://ca.linkedin.com/in/rpjday


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[U-Boot] [PATCH 2/2] board/liteboard: Add support for liteBoard

[Marcin Niestroj]

liteBoard is a development board which uses liteSOM as its base.

Hardware specification:
 * liteSOM (i.MX6UL, DRAM, eMMC)
 * Ethernet PHY (id 0)
 * USB host (usb_otg1)
 * MicroSD slot (uSDHC1)

Signed-off-by: Marcin Niestroj 
---
 arch/arm/cpu/armv7/mx6/Kconfig|   5 +
 board/grinn/liteboard/Kconfig |  12 ++
 board/grinn/liteboard/MAINTAINERS |   6 +
 board/grinn/liteboard/Makefile|   6 +
 board/grinn/liteboard/README  |  31 +
 board/grinn/liteboard/board.c | 270 ++
 configs/liteboard_defconfig   |  22 
 include/configs/liteboard.h   | 174 
 8 files changed, 526 insertions(+)
 create mode 100644 board/grinn/liteboard/Kconfig
 create mode 100644 board/grinn/liteboard/MAINTAINERS
 create mode 100644 board/grinn/liteboard/Makefile
 create mode 100644 board/grinn/liteboard/README
 create mode 100644 board/grinn/liteboard/board.c
 create mode 100644 configs/liteboard_defconfig
 create mode 100644 include/configs/liteboard.h

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 4214ab5..e24d0a1 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -144,6 +144,10 @@ config TARGET_PICO_IMX6UL
bool "PICO-IMX6UL-EMMC"
select MX6UL
 
+config TARGET_LITEBOARD
+   bool "Grinn liteBoard (i.MX6UL)"
+   select LITESOM
+
 config TARGET_PLATINUM_PICON
bool "platinum-picon"
select SUPPORT_SPL
@@ -222,6 +226,7 @@ source "board/freescale/mx6slevk/Kconfig"
 source "board/freescale/mx6sxsabresd/Kconfig"
 source "board/freescale/mx6sxsabreauto/Kconfig"
 source "board/freescale/mx6ul_14x14_evk/Kconfig"
+source "board/grinn/liteboard/Kconfig"
 source "board/phytec/pcm058/Kconfig"
 source "board/gateworks/gw_ventana/Kconfig"
 source "board/kosagi/novena/Kconfig"
diff --git a/board/grinn/liteboard/Kconfig b/board/grinn/liteboard/Kconfig
new file mode 100644
index 000..e035872
--- /dev/null
+++ b/board/grinn/liteboard/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_LITEBOARD
+
+config SYS_BOARD
+   default "liteboard"
+
+config SYS_VENDOR
+   default "grinn"
+
+config SYS_CONFIG_NAME
+   default "liteboard"
+
+endif
diff --git a/board/grinn/liteboard/MAINTAINERS 
b/board/grinn/liteboard/MAINTAINERS
new file mode 100644
index 000..b4474f1
--- /dev/null
+++ b/board/grinn/liteboard/MAINTAINERS
@@ -0,0 +1,6 @@
+LITEBOARD
+M: Marcin Niestroj 
+S: Maintained
+F: board/grinn/liteboard/
+F: include/configs/liteboard.h
+F: configs/liteboard_defconfig
diff --git a/board/grinn/liteboard/Makefile b/board/grinn/liteboard/Makefile
new file mode 100644
index 000..e2492d6
--- /dev/null
+++ b/board/grinn/liteboard/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2016 Grinn
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  := board.o
diff --git a/board/grinn/liteboard/README b/board/grinn/liteboard/README
new file mode 100644
index 000..bee0394
--- /dev/null
+++ b/board/grinn/liteboard/README
@@ -0,0 +1,31 @@
+How to use U-Boot on Grinn's liteBoard
+--
+
+- Build U-Boot for liteBoard:
+
+$ make mrproper
+$ make liteboard_defconfig
+$ make
+
+This will generate the SPL image called SPL and the u-boot.img.
+
+- Flash the SPL image into the micro SD card:
+
+sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+
+- Flash the u-boot.img image into the micro SD card:
+
+sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69; sync
+
+- Jumper settings:
+
+S1: 0 1 0 1 1 1
+
+where 0 means bottom position and 1 means top position (from the
+switch label numbers reference).
+
+- Insert the micro SD card in the board.
+
+- Connect USB cable between liteBoard and the PC for the power and console.
+
+- U-Boot messages should come up.
diff --git a/board/grinn/liteboard/board.c b/board/grinn/liteboard/board.c
new file mode 100644
index 000..89d525a
--- /dev/null
+++ b/board/grinn/liteboard/board.c
@@ -0,0 +1,270 @@
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright (C) 2016 Grinn
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |\
+   PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |   \
+   PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |\
+   PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |   \
+   PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+   PAD_CTL_SPEED_HIGH   |   \
+   

[U-Boot] [PATCH 1/2] ARM: imx6ul: Add support for liteSOM

[Marcin Niestroj]

liteSOM is a System On Module (http://grinn-global.com/litesom/). It
can't exists on its own, but will be used as part of other boards.

Hardware specification:
 * NXP i.MX6UL processor
 * 256M or 512M DDR3 memory
 * optional eMMC (uSDHC2)

Here we treat SOM similar to SOC, so we place it inside arch/arm/mach-*
directory and make it possible to reuse initialization code (i.e. DDR,
eMMC init) for all boards that use it.

Signed-off-by: Marcin Niestroj 
---
 arch/arm/Kconfig |   2 +
 arch/arm/Makefile|   1 +
 arch/arm/mach-litesom/Kconfig|   6 +
 arch/arm/mach-litesom/Makefile   |   6 +
 arch/arm/mach-litesom/include/mach/litesom.h |  16 +++
 arch/arm/mach-litesom/litesom.c  | 200 +++
 6 files changed, 231 insertions(+)
 create mode 100644 arch/arm/mach-litesom/Kconfig
 create mode 100644 arch/arm/mach-litesom/Makefile
 create mode 100644 arch/arm/mach-litesom/include/mach/litesom.h
 create mode 100644 arch/arm/mach-litesom/litesom.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e63309a..bf5ac39 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -917,6 +917,8 @@ source "arch/arm/mach-keystone/Kconfig"
 
 source "arch/arm/mach-kirkwood/Kconfig"
 
+source "arch/arm/mach-litesom/Kconfig"
+
 source "arch/arm/mach-mvebu/Kconfig"
 
 source "arch/arm/cpu/armv7/mx7/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 42093c2..3e804d7 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -58,6 +58,7 @@ machine-$(CONFIG_ARCH_HIGHBANK)   += highbank
 machine-$(CONFIG_ARCH_KEYSTONE)+= keystone
 # TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD
 machine-$(CONFIG_KIRKWOOD) += kirkwood
+machine-$(CONFIG_LITESOM)  += litesom
 machine-$(CONFIG_ARCH_MESON)   += meson
 machine-$(CONFIG_ARCH_MVEBU)   += mvebu
 # TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
diff --git a/arch/arm/mach-litesom/Kconfig b/arch/arm/mach-litesom/Kconfig
new file mode 100644
index 000..9b7f36d
--- /dev/null
+++ b/arch/arm/mach-litesom/Kconfig
@@ -0,0 +1,6 @@
+config LITESOM
+   bool
+   select MX6UL
+   select DM
+   select DM_THERMAL
+   select SUPPORT_SPL
diff --git a/arch/arm/mach-litesom/Makefile b/arch/arm/mach-litesom/Makefile
new file mode 100644
index 000..b15eb64
--- /dev/null
+++ b/arch/arm/mach-litesom/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2016 Grinn
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  := litesom.o
diff --git a/arch/arm/mach-litesom/include/mach/litesom.h 
b/arch/arm/mach-litesom/include/mach/litesom.h
new file mode 100644
index 000..6833949
--- /dev/null
+++ b/arch/arm/mach-litesom/include/mach/litesom.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2016 Grinn
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __ARCH_ARM_MACH_LITESOM_SOM_H__
+#define __ARCH_ARM_MACH_LITESOM_SOM_H__
+
+int litesom_mmc_init(bd_t *bis);
+
+#ifdef CONFIG_SPL_BUILD
+void litesom_init_f(void);
+#endif
+
+#endif
diff --git a/arch/arm/mach-litesom/litesom.c b/arch/arm/mach-litesom/litesom.c
new file mode 100644
index 000..ac2eccf
--- /dev/null
+++ b/arch/arm/mach-litesom/litesom.c
@@ -0,0 +1,200 @@
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright (C) 2016 Grinn
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |\
+   PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |   \
+   PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+   gd->ram_size = imx_ddr_size();
+
+   return 0;
+}
+
+static iomux_v3_cfg_t const emmc_pads[] = {
+   MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+   /* RST_B */
+   MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#ifdef CONFIG_FSL_ESDHC
+static struct fsl_esdhc_cfg emmc_cfg = {USDHC2_BASE_ADDR, 0, 8};
+
+#define EMMC_PWR_GPIO  IMX_GPIO_NR(4, 10)
+
+int litesom_mmc_init(bd_t *bis)
+{
+   int ret;

[U-Boot] [PATCH 0/2] ARM: imx6ul: Support liteSOM and liteBoard

[Marcin Niestroj]

Hi,

These patches add support for liteSOM (http://grinn-global.com/litesom/),
and liteBoard (which uses liteSOM as it's base).

liteSOM consists of processor (NXP i.MX6UL), RAM memory (up to 512M DDR3)
and flash (eMMC card). The idea is that every board vendor can use liteSOM
as it's base for designed board. Hence, we need a way to reuse common code
between those board.

liteBoard is a development kit (and reference platform for liteSOM), that
mainly shows possibilities and use cases of liteSOM.

Patches were developed and tested on 2016.09.

Marcin Niestroj (2):
  ARM: imx6ul: Add support for liteSOM
  board/liteboard: Add support for liteBoard

 arch/arm/Kconfig |   2 +
 arch/arm/Makefile|   1 +
 arch/arm/cpu/armv7/mx6/Kconfig   |   5 +
 arch/arm/mach-litesom/Kconfig|   6 +
 arch/arm/mach-litesom/Makefile   |   6 +
 arch/arm/mach-litesom/include/mach/litesom.h |  16 ++
 arch/arm/mach-litesom/litesom.c  | 200 
 board/grinn/liteboard/Kconfig|  12 ++
 board/grinn/liteboard/MAINTAINERS|   6 +
 board/grinn/liteboard/Makefile   |   6 +
 board/grinn/liteboard/README |  31 +++
 board/grinn/liteboard/board.c| 270 +++
 configs/liteboard_defconfig  |  22 +++
 include/configs/liteboard.h  | 174 +
 14 files changed, 757 insertions(+)
 create mode 100644 arch/arm/mach-litesom/Kconfig
 create mode 100644 arch/arm/mach-litesom/Makefile
 create mode 100644 arch/arm/mach-litesom/include/mach/litesom.h
 create mode 100644 arch/arm/mach-litesom/litesom.c
 create mode 100644 board/grinn/liteboard/Kconfig
 create mode 100644 board/grinn/liteboard/MAINTAINERS
 create mode 100644 board/grinn/liteboard/Makefile
 create mode 100644 board/grinn/liteboard/README
 create mode 100644 board/grinn/liteboard/board.c
 create mode 100644 configs/liteboard_defconfig
 create mode 100644 include/configs/liteboard.h

-- 
2.9.3

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[U-Boot] [PATCH 6/9] arm64: mvebu: Add Armada 7K db-88f7040 development board support

[Stefan Roese]

This patch adds basic support for the Marvell Armada 7K DB-88F7040
development board. Supported are the following interfaces:
- UART
- SPI (incl. SPI NOR)
- I2C
- USB
- SATA / AHCI

Support for other interfaces will follow.

Signed-off-by: Stefan Roese 
Cc: Nadav Haklai 
Cc: Neta Zur Hershkovits 
Cc: Kostya Porotchkin 
Cc: Omri Itach 
Cc: Igal Liberman 
Cc: Haim Boot 
Cc: Hanna Hawa 
---
 arch/arm/mach-mvebu/Kconfig|   7 ++
 board/Marvell/mvebu_db-88f7040/MAINTAINERS |   6 ++
 board/Marvell/mvebu_db-88f7040/Makefile|   7 ++
 board/Marvell/mvebu_db-88f7040/board.c | 152 +
 configs/mvebu_db-88f7040_defconfig |  47 +
 include/configs/mvebu_db-88f7040.h | 133 +
 6 files changed, 352 insertions(+)
 create mode 100644 board/Marvell/mvebu_db-88f7040/MAINTAINERS
 create mode 100644 board/Marvell/mvebu_db-88f7040/Makefile
 create mode 100644 board/Marvell/mvebu_db-88f7040/board.c
 create mode 100644 configs/mvebu_db-88f7040_defconfig
 create mode 100644 include/configs/mvebu_db-88f7040.h

diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 54b3b72..9bdcdc8 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -73,6 +73,10 @@ config TARGET_DB_88F6820_GP
bool "Support DB-88F6820-GP"
select DB_88F6820_GP
 
+config TARGET_MVEBU_DB_88F7040
+   bool "Support DB-88F7040 Armada 7040"
+   select ARMADA_8K
+
 config TARGET_DB_MV784MP_GP
bool "Support db-mv784mp-gp"
select MV78460
@@ -96,6 +100,7 @@ config SYS_BOARD
default "mvebu_db-88f3720" if TARGET_MVEBU_DB_88F3720
default "db-88f6720" if TARGET_DB_88F6720
default "db-88f6820-gp" if TARGET_DB_88F6820_GP
+   default "mvebu_db-88f7040" if TARGET_MVEBU_DB_88F7040
default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
default "ds414" if TARGET_DS414
default "maxbcm" if TARGET_MAXBCM
@@ -106,6 +111,7 @@ config SYS_CONFIG_NAME
default "mvebu_db-88f3720" if TARGET_MVEBU_DB_88F3720
default "db-88f6720" if TARGET_DB_88F6720
default "db-88f6820-gp" if TARGET_DB_88F6820_GP
+   default "mvebu_db-88f7040" if TARGET_MVEBU_DB_88F7040
default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
default "ds414" if TARGET_DS414
default "maxbcm" if TARGET_MAXBCM
@@ -116,6 +122,7 @@ config SYS_VENDOR
default "Marvell" if TARGET_MVEBU_DB_88F3720
default "Marvell" if TARGET_DB_88F6720
default "Marvell" if TARGET_DB_88F6820_GP
+   default "Marvell" if TARGET_MVEBU_DB_88F7040
default "solidrun" if TARGET_CLEARFOG
default "Synology" if TARGET_DS414
 
diff --git a/board/Marvell/mvebu_db-88f7040/MAINTAINERS 
b/board/Marvell/mvebu_db-88f7040/MAINTAINERS
new file mode 100644
index 000..820461b
--- /dev/null
+++ b/board/Marvell/mvebu_db-88f7040/MAINTAINERS
@@ -0,0 +1,6 @@
+MVEBU_DB_88F7040 BOARD
+M: Stefan Roese 
+S: Maintained
+F: board/Marvell/mvebu_db-88f7040/
+F: include/configs/mvebu_db-88f7040.h
+F: configs/mvebu_db-88f7040_defconfig
diff --git a/board/Marvell/mvebu_db-88f7040/Makefile 
b/board/Marvell/mvebu_db-88f7040/Makefile
new file mode 100644
index 000..ed39738
--- /dev/null
+++ b/board/Marvell/mvebu_db-88f7040/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2016 Stefan Roese 
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  := board.o
diff --git a/board/Marvell/mvebu_db-88f7040/board.c 
b/board/Marvell/mvebu_db-88f7040/board.c
new file mode 100644
index 000..48bd55c
--- /dev/null
+++ b/board/Marvell/mvebu_db-88f7040/board.c
@@ -0,0 +1,152 @@
+/*
+ * Copyright (C) 2016 Stefan Roese 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* IO expander I2C device */
+#define I2C_IO_EXP_ADDR0x21
+#define I2C_IO_CFG_REG_0   0x6
+#define I2C_IO_DATA_OUT_REG_0  0x2
+/* VBus enable */
+#define I2C_IO_REG_0_USB_H0_OFF0
+#define I2C_IO_REG_0_USB_H1_OFF1
+#define I2C_IO_REG_VBUS((1 << I2C_IO_REG_0_USB_H0_OFF) | \
+(1 << I2C_IO_REG_0_USB_H1_OFF))
+/* Current limit */
+#define I2C_IO_REG_0_USB_H0_CL 4
+#define I2C_IO_REG_0_USB_H1_CL 5
+#define I2C_IO_REG_CL  ((1 << I2C_IO_REG_0_USB_H0_CL) | \
+(1 << I2C_IO_REG_0_USB_H1_CL))
+
+static int usb_enabled = 0;
+
+/* Board specific xHCI dis-/enable code */
+
+/*
+ * Set USB VBUS signals (via I2C IO expander/GPIO) as output and set
+ * output value as disabled
+ *
+ * Set USB Current Limit signals (via I2C IO expander/GPIO) as output
+ * and set output value as enabled
+ */
+int board_xhci_config(void)
+{
+   struct 

[U-Boot] [PATCH 1/9] drivers/phy: Add Marvell SerDes / PHY drivers used on Armada 7K/8K

[Stefan Roese]

This version is based on the Marvell U-Boot version with this patch
applied as latest patch:

Git ID 7f408573: "fix: comphy: cp110: add comphy initialization for usb
device mode" from 2016-07-05.

Signed-off-by: Stefan Roese 
Cc: Nadav Haklai 
Cc: Neta Zur Hershkovits 
Cc: Kostya Porotchkin 
Cc: Omri Itach 
Cc: Igal Liberman 
Cc: Haim Boot 
Cc: Hanna Hawa 
---
 drivers/phy/marvell/Makefile   |1 +
 drivers/phy/marvell/comphy.h   |   18 +-
 drivers/phy/marvell/comphy_core.c  |3 +
 drivers/phy/marvell/comphy_cp110.c | 1726 
 drivers/phy/marvell/comphy_hpipe.h |   38 +
 drivers/phy/marvell/sata.h |   30 +
 drivers/phy/marvell/utmi_phy.h |   90 ++
 7 files changed, 1904 insertions(+), 2 deletions(-)
 create mode 100644 drivers/phy/marvell/comphy_cp110.c
 create mode 100644 drivers/phy/marvell/sata.h
 create mode 100644 drivers/phy/marvell/utmi_phy.h

diff --git a/drivers/phy/marvell/Makefile b/drivers/phy/marvell/Makefile
index 91df554..f181505 100644
--- a/drivers/phy/marvell/Makefile
+++ b/drivers/phy/marvell/Makefile
@@ -5,3 +5,4 @@
 obj-$(CONFIG_MVEBU_COMPHY_SUPPORT) += comphy_core.o
 obj-$(CONFIG_MVEBU_COMPHY_SUPPORT) += comphy_mux.o
 obj-$(CONFIG_ARMADA_3700) += comphy_a3700.o
+obj-$(CONFIG_ARMADA_8K) += comphy_cp110.o
diff --git a/drivers/phy/marvell/comphy.h b/drivers/phy/marvell/comphy.h
index 5c50e9c..df5b7d5 100644
--- a/drivers/phy/marvell/comphy.h
+++ b/drivers/phy/marvell/comphy.h
@@ -60,6 +60,9 @@
 #define COMMON_PHY_SD_CTRL1_RXAUI0_MASK\
(0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET)
 
+/* ToDo: Get this address via DT */
+#define MVEBU_CP0_REGS_BASE0xF200UL
+
 #define DFX_DEV_GEN_CTRL12 (MVEBU_CP0_REGS_BASE + 0x400280)
 #define DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET7
 #define DFX_DEV_GEN_PCIE_CLK_SRC_MASK  \
@@ -117,10 +120,21 @@ static inline int comphy_a3700_init(struct 
chip_serdes_phy_config *ptr_chip_cfg,
return -1;
 }
 #endif
-int comphy_ap806_init(struct chip_serdes_phy_config *ptr_chip_cfg,
- struct comphy_map *serdes_map);
+
+#ifdef CONFIG_ARMADA_8K
 int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
  struct comphy_map *serdes_map);
+#else
+static inline int comphy_cp110_init(struct chip_serdes_phy_config 
*ptr_chip_cfg,
+ struct comphy_map *serdes_map)
+{
+   /*
+* This function should never be called in this configuration, so
+* lets return an error here.
+*/
+   return -1;
+}
+#endif
 
 void comphy_dedicated_phys_init(void);
 
diff --git a/drivers/phy/marvell/comphy_core.c 
b/drivers/phy/marvell/comphy_core.c
index 519bc16..799e034 100644
--- a/drivers/phy/marvell/comphy_core.c
+++ b/drivers/phy/marvell/comphy_core.c
@@ -139,6 +139,9 @@ static int comphy_probe(struct udevice *dev)
if (of_device_is_compatible(dev, "marvell,comphy-armada-3700"))
chip_cfg->ptr_comphy_chip_init = comphy_a3700_init;
 
+   if (of_device_is_compatible(dev, "marvell,comphy-cp110"))
+   chip_cfg->ptr_comphy_chip_init = comphy_cp110_init;
+
/*
 * Bail out if no chip_init function is defined, e.g. no
 * compatible node is found
diff --git a/drivers/phy/marvell/comphy_cp110.c 
b/drivers/phy/marvell/comphy_cp110.c
new file mode 100644
index 000..25c067d
--- /dev/null
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -0,0 +1,1726 @@
+/*
+ * Copyright (C) 2015-2016 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "comphy.h"
+#include "comphy_hpipe.h"
+#include "sata.h"
+#include "utmi_phy.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SD_ADDR(base, lane)(base + 0x1000 * lane)
+#define HPIPE_ADDR(base, lane) (SD_ADDR(base, lane) + 0x800)
+#define COMPHY_ADDR(base, lane)(base + 0x28 * lane)
+
+struct utmi_phy_data {
+   void __iomem *utmi_base_addr;
+   void __iomem *usb_cfg_addr;
+   void __iomem *utmi_cfg_addr;
+   u32 utmi_phy_port;
+};
+
+/*
+ * For CP-110 we have 2 Selector registers "PHY Selectors",
+ * and "PIPE Selectors".
+ * PIPE selector include USB and PCIe options.
+ * PHY selector include the Ethernet and SATA options, every Ethernet
+ * option has different options, for example: serdes lane2 had option
+ * Eth_port_0 that include (SGMII0, XAUI0, RXAUI0, KR)
+ */
+struct comphy_mux_data cp110_comphy_phy_mux_data[] = {
+   {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 0 */
+{PHY_TYPE_XAUI2, 0x1}, {PHY_TYPE_SATA1, 0x4} } },
+   {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII3, 0x1}, /* Lane 1 */
+{PHY_TYPE_XAUI3, 0x1}, 

[U-Boot] [PATCH 8/9] arm64: mvebu: Armada 7K/8K: Add COMPHY device tree nodes

[Stefan Roese]

This patch adds the COMPHY device tree nodes that are still missing to
the Armada 7K/8K dts files.

Signed-off-by: Stefan Roese 
Cc: Nadav Haklai 
Cc: Neta Zur Hershkovits 
Cc: Kostya Porotchkin 
Cc: Omri Itach 
Cc: Igal Liberman 
Cc: Haim Boot 
Cc: Hanna Hawa 
---
 arch/arm/dts/armada-7040-db.dts   | 40 +++
 arch/arm/dts/armada-cp110-master.dtsi | 28 
 2 files changed, 68 insertions(+)

diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts
index 070b589..df0c327 100644
--- a/arch/arm/dts/armada-7040-db.dts
+++ b/arch/arm/dts/armada-7040-db.dts
@@ -146,3 +146,43 @@
 _usb3_1 {
status = "okay";
 };
+
+_cp110 {
+   phy0 {
+   phy-type = ;
+   phy-speed = ;
+   };
+
+   phy1 {
+   phy-type = ;
+   phy-speed = ;
+   };
+
+   phy2 {
+   phy-type = ;
+   phy-speed = ;
+   };
+
+   phy3 {
+   phy-type = ;
+   phy-speed = ;
+   };
+
+   phy4 {
+   phy-type = ;
+   phy-speed = ;
+   };
+
+   phy5 {
+   phy-type = ;
+   phy-speed = ;
+   };
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
diff --git a/arch/arm/dts/armada-cp110-master.dtsi 
b/arch/arm/dts/armada-cp110-master.dtsi
index 367138b..7da98bf 100644
--- a/arch/arm/dts/armada-cp110-master.dtsi
+++ b/arch/arm/dts/armada-cp110-master.dtsi
@@ -44,6 +44,8 @@
  * Device Tree file for Marvell Armada CP110 Master.
  */
 
+#include 
+
 / {
cp110-master {
#address-cells = <2>;
@@ -146,6 +148,32 @@
clocks = <_syscon0 1 21>;
status = "disabled";
};
+
+   comphy_cp110: comphy@441000 {
+   compatible = "marvell,mvebu-comphy", 
"marvell,comphy-cp110";
+   reg = <0x441000 0x8>,
+ <0x12 0x8>;
+   mux-bitcount = <4>;
+   max-lanes = <6>;
+   };
+
+   utmi0: utmi@58 {
+   compatible = "marvell,mvebu-utmi-2.6.0";
+   reg = <0x58 0x1000>,/* utmi-unit */
+ <0x440420 0x4>,   /* usb-cfg */
+ <0x440440 0x4>;   /* utmi-cfg */
+   utmi-port = ;
+   status = "disabled";
+   };
+
+   utmi1: utmi@581000 {
+   compatible = "marvell,mvebu-utmi-2.6.0";
+   reg = <0x581000 0x1000>,/* utmi-unit */
+ <0x440420 0x4>,   /* usb-cfg */
+ <0x440444 0x4>;   /* utmi-cfg */
+   utmi-port = ;
+   status = "disabled";
+   };
};
 
cpm_pcie0: pcie@f260 {
-- 
2.9.3

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[U-Boot] [PATCH 3/9] ahci: Make ahci_port_base() non-static to enable overwrite

[Stefan Roese]

To allow a board- / platform-specific ahci_port_base() function, this
patch removes "static inline" and adds __weak to this function. This
will be used by the upcoming Armada 7K/8K SATA / AHCI support, which
unfortunately needs a different port base address calculation.

Signed-off-by: Stefan Roese 
Cc: Nadav Haklai 
Cc: Neta Zur Hershkovits 
Cc: Kostya Porotchkin 
Cc: Omri Itach 
Cc: Igal Liberman 
Cc: Haim Boot 
Cc: Hanna Hawa 
---
 drivers/block/ahci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c
index e3e783a..cd99737 100644
--- a/drivers/block/ahci.c
+++ b/drivers/block/ahci.c
@@ -45,7 +45,7 @@ u16 *ataid[AHCI_MAX_PORTS];
 #define WAIT_MS_FLUSH  5000
 #define WAIT_MS_LINKUP 200
 
-static inline void __iomem *ahci_port_base(void __iomem *base, u32 port)
+__weak void __iomem *ahci_port_base(void __iomem *base, u32 port)
 {
return base + 0x100 + (port * 0x80);
 }
-- 
2.9.3

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[U-Boot] [PATCH 2/9] usb: xhci-mvebu: Add Armada 8K to compatiblity list

[Stefan Roese]

To enable this driver on Armada 7K/8K this patch adds the compatibility
property to the list.

Signed-off-by: Stefan Roese 
Cc: Nadav Haklai 
Cc: Neta Zur Hershkovits 
Cc: Kostya Porotchkin 
Cc: Omri Itach 
Cc: Igal Liberman 
Cc: Haim Boot 
Cc: Hanna Hawa 
---
 drivers/usb/host/xhci-mvebu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/usb/host/xhci-mvebu.c b/drivers/usb/host/xhci-mvebu.c
index e09e87a..23c241a 100644
--- a/drivers/usb/host/xhci-mvebu.c
+++ b/drivers/usb/host/xhci-mvebu.c
@@ -79,6 +79,7 @@ static int xhci_usb_ofdata_to_platdata(struct udevice *dev)
 
 static const struct udevice_id xhci_usb_ids[] = {
{ .compatible = "marvell,armada3700-xhci" },
+   { .compatible = "marvell,armada-8k-xhci" },
{ }
 };
 
-- 
2.9.3

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[U-Boot] [PATCH 7/9] arm64: mvebu: armada-ap806.dtsi: Add clock-frequency to UART DT node

[Stefan Roese]

The clock frequency needs to be provided in the DT. Otherwise the driver
won't start in U-Boot.

Signed-off-by: Stefan Roese 
Cc: Nadav Haklai 
Cc: Neta Zur Hershkovits 
Cc: Kostya Porotchkin 
Cc: Omri Itach 
Cc: Igal Liberman 
Cc: Haim Boot 
Cc: Hanna Hawa 
---
 arch/arm/dts/armada-ap806.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/armada-ap806.dtsi b/arch/arm/dts/armada-ap806.dtsi
index 20d256b..d315b29 100644
--- a/arch/arm/dts/armada-ap806.dtsi
+++ b/arch/arm/dts/armada-ap806.dtsi
@@ -202,6 +202,7 @@
reg-io-width = <1>;
clocks = <_syscon 3>;
status = "disabled";
+   clock-frequency = <2>;
};
 
uart1: serial@512100 {
-- 
2.9.3

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[U-Boot] [PATCH 9/9] arm64: mvebu: armada-7040-db.dts: Add I2C and SPI aliases

[Stefan Roese]

Add I2C and SPI aliases to enable usage in U-Boot.

Signed-off-by: Stefan Roese 
Cc: Nadav Haklai 
Cc: Neta Zur Hershkovits 
Cc: Kostya Porotchkin 
Cc: Omri Itach 
Cc: Igal Liberman 
Cc: Haim Boot 
Cc: Hanna Hawa 
---
 arch/arm/dts/armada-7040-db.dts | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts
index df0c327..7d0059a 100644
--- a/arch/arm/dts/armada-7040-db.dts
+++ b/arch/arm/dts/armada-7040-db.dts
@@ -55,6 +55,11 @@
stdout-path = "serial0:115200n8";
};
 
+   aliases {
+   i2c0 = _i2c0;
+   spi0 = _spi1;
+   };
+
memory@ {
device_type = "memory";
reg = <0x0 0x0 0x0 0x8000>;
-- 
2.9.3

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[U-Boot] [PATCH 5/9] arm64: mvebu: Add basic support for the Marvell Armada 7K/8K SoC

[Stefan Roese]

Compared to the Armada 3700, the Armada 7K and 8K are much more on the
high-end side: they use a dual Cortex-A72 or a quad Cortex-A72, as
opposed to the Cortex-A53 for the Armada 3700.

The Armada 7K and 8K also use a fairly unique architecture, internally
they are composed of several components:

- One AP (Application Processor), which contains the processor itself
  and a few core hardware blocks. The AP used in the Armada 7K and 8K
  is called AP806, and is available in two configurations:
  dual Cortex-A72 and quad Cortex-A72.
- One or two CP (Communication Processor), which contain most of the I/O
  interfaces (SATA, PCIe, Ethernet, etc.). The 7K family chips have one
  CP, while the 8K family chips integrate two CPs, providing two times
  the number of I/O interfaces available in the CP.
  The CP used in the 7K and 8K is called CP110.

All in all, this gives the following combinations:

- Armada 7020, which is a dual Cortex-A72 with one CP
- Armada 7040, which is a quad Cortex-A72 with one CP
- Armada 8020, which is a dual Cortex-A72 with two CPs
- Armada 8040, which is a quad Cortex-A72 with two CPs

This patch adds basic support for this ARMv8 based SoC into U-Boot.
Future patches will integrate other device drivers and board support,
starting with the Marvell DB-88F7040 development board.

Signed-off-by: Stefan Roese 
Cc: Nadav Haklai 
Cc: Neta Zur Hershkovits 
Cc: Kostya Porotchkin 
Cc: Omri Itach 
Cc: Igal Liberman 
Cc: Haim Boot 
Cc: Hanna Hawa 
---
 arch/arm/Kconfig|   2 +-
 arch/arm/mach-mvebu/Kconfig |   7 +-
 arch/arm/mach-mvebu/Makefile|   3 +
 arch/arm/mach-mvebu/arm64-common.c  | 124 
 arch/arm/mach-mvebu/armada3700/Makefile |   1 -
 arch/arm/mach-mvebu/armada3700/cpu.c| 107 
 arch/arm/mach-mvebu/armada8k/Makefile   |   7 ++
 arch/arm/mach-mvebu/armada8k/cpu.c  |  64 ++
 arch/arm/mach-mvebu/include/mach/soc.h  |   2 +
 arch/arm/mach-mvebu/{armada3700 => }/sata.c |   9 ++
 10 files changed, 216 insertions(+), 110 deletions(-)
 create mode 100644 arch/arm/mach-mvebu/arm64-common.c
 create mode 100644 arch/arm/mach-mvebu/armada8k/Makefile
 create mode 100644 arch/arm/mach-mvebu/armada8k/cpu.c
 rename arch/arm/mach-mvebu/{armada3700 => }/sata.c (77%)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f9d0d2e..61a2fe6 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -164,7 +164,7 @@ config KIRKWOOD
select CPU_ARM926EJS
 
 config ARCH_MVEBU
-   bool "Marvell MVEBU family (Armada XP/375/38x)"
+   bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
select OF_CONTROL
select OF_SEPARATE
select DM
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index bede700..54b3b72 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -31,6 +31,11 @@ config ARMADA_3700
bool
select ARM64
 
+# Armada 7K and 8K are very similar - use only one Kconfig symbol for both
+config ARMADA_8K
+   bool
+   select ARM64
+
 # Armada XP/38x SoC types...
 config MV78230
bool
@@ -49,7 +54,7 @@ config DB_88F6820_GP
select ARMADA_38X
 
 choice
-   prompt "Marvell MVEBU (Armada XP/375/38x/3700) board select"
+   prompt "Armada XP/375/38x/3700/7K/8K board select"
optional
 
 config TARGET_CLEARFOG
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 07dc16c..65e90c4 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -7,6 +7,9 @@
 ifdef CONFIG_ARM64
 
 obj-$(CONFIG_ARMADA_3700) += armada3700/
+obj-$(CONFIG_ARMADA_8K) += armada8k/
+obj-y += arm64-common.o
+obj-y += sata.o
 
 else # CONFIG_ARM64
 
diff --git a/arch/arm/mach-mvebu/arm64-common.c 
b/arch/arm/mach-mvebu/arm64-common.c
new file mode 100644
index 000..7055a81
--- /dev/null
+++ b/arch/arm/mach-mvebu/arm64-common.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2016 Stefan Roese 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * On ARMv8, MBus is not configured in U-Boot. To enable compilation
+ * of the already implemented drivers, lets add a dummy version of
+ * this function so that linking does not fail.
+ */
+const struct mbus_dram_target_info *mvebu_mbus_dram_info(void)
+{
+   return NULL;
+}
+
+/* DRAM init code ... */
+
+static const void *get_memory_reg_prop(const void *fdt, int *lenp)
+{
+   int offset;
+
+   offset = fdt_path_offset(fdt, "/memory");
+   if (offset < 0)
+   return NULL;
+
+   return fdt_getprop(fdt, offset, "reg", lenp);
+}
+
+int dram_init(void)
+{
+  

[U-Boot] [PATCH 4/9] arm64: mvebu: Armada 7K/8K: Add Armada 7K/8K dts files

[Stefan Roese]

This patch integrates the Armada 7K/8K dts files from the latest
submission on the linux-arm-kernel mailing list.

Signed-off-by: Stefan Roese 
Cc: Nadav Haklai 
Cc: Neta Zur Hershkovits 
Cc: Kostya Porotchkin 
Cc: Omri Itach 
Cc: Igal Liberman 
Cc: Haim Boot 
Cc: Hanna Hawa 
---
 arch/arm/dts/Makefile |   1 +
 arch/arm/dts/armada-7040-db.dts   | 148 ++
 arch/arm/dts/armada-7040.dtsi |  55 
 arch/arm/dts/armada-ap806-quad.dtsi   |  82 
 arch/arm/dts/armada-ap806.dtsi| 229 ++
 arch/arm/dts/armada-cp110-master.dtsi | 228 +
 6 files changed, 743 insertions(+)
 create mode 100644 arch/arm/dts/armada-7040-db.dts
 create mode 100644 arch/arm/dts/armada-7040.dtsi
 create mode 100644 arch/arm/dts/armada-ap806-quad.dtsi
 create mode 100644 arch/arm/dts/armada-ap806.dtsi
 create mode 100644 arch/arm/dts/armada-cp110-master.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 4a51de1..92155f5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -71,6 +71,7 @@ dtb-$(CONFIG_ARCH_MVEBU) +=   \
armada-375-db.dtb   \
armada-388-clearfog.dtb \
armada-388-gp.dtb   \
+   armada-7040-db.dtb  \
armada-xp-gp.dtb\
armada-xp-maxbcm.dtb\
armada-xp-synology-ds414.dtb\
diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts
new file mode 100644
index 000..070b589
--- /dev/null
+++ b/arch/arm/dts/armada-7040-db.dts
@@ -0,0 +1,148 @@
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Device Tree file for Marvell Armada 7040 Development board platform
+ */
+
+#include "armada-7040.dtsi"
+
+/ {
+   model = "Marvell Armada 7040 DB board";
+   compatible = "marvell,armada7040-db", "marvell,armada7040",
+"marvell,armada-ap806-quad", "marvell,armada-ap806";
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   memory@ {
+   device_type = "memory";
+   reg = <0x0 0x0 0x0 0x8000>;
+   };
+};
+
+ {
+   status = "okay";
+   clock-frequency = <10>;
+};
+
+ {
+   status = "okay";
+
+   spi-flash@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <1000>;
+
+   partitions {
+   compatible = "fixed-partitions";
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   partition@0 {
+

[U-Boot] [PATCH 14/15] arm64: mvebu: Add support for the Marvell Armada 3700 SoC

[Stefan Roese]

The Armada 3700 integrates the following interfaces (not complete list):
- Dual Cortex-A53 ARMv8
- USB 3.0
- SATA 3.0
- PCIe 2.0
- 2 x Gigabit Ethernet 1Gbps / 2.5Gbps
- ...

This patch adds basic support for this ARMv8 based SoC into U-Boot.
Future patches will integrate other device drivers and board support
for the Marvell DB-88F3720 development board.

Signed-off-by: Stefan Roese 
Cc: Nadav Haklai 
Cc: Kostya Porotchkin 
Cc: Wilson Ding 
Cc: Victor Gu 
Cc: Hua Jing 
Cc: Terry Zhou 
Cc: Hanna Hawa 
Cc: Haim Boot 
---
 arch/arm/Kconfig|   6 -
 arch/arm/mach-mvebu/Kconfig |  25 -
 arch/arm/mach-mvebu/Makefile|  15 ++-
 arch/arm/mach-mvebu/armada3700/Makefile |   8 ++
 arch/arm/mach-mvebu/armada3700/cpu.c| 188 
 arch/arm/mach-mvebu/armada3700/sata.c   |  45 
 arch/arm/mach-mvebu/include/mach/cpu.h  |   7 ++
 arch/arm/mach-mvebu/include/mach/soc.h  |   2 +-
 8 files changed, 284 insertions(+), 12 deletions(-)
 create mode 100644 arch/arm/mach-mvebu/armada3700/Makefile
 create mode 100644 arch/arm/mach-mvebu/armada3700/cpu.c
 create mode 100644 arch/arm/mach-mvebu/armada3700/sata.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e63309a..f9d0d2e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -165,8 +165,6 @@ config KIRKWOOD
 
 config ARCH_MVEBU
bool "Marvell MVEBU family (Armada XP/375/38x)"
-   select CPU_V7
-   select SUPPORT_SPL
select OF_CONTROL
select OF_SEPARATE
select DM
@@ -174,10 +172,6 @@ config ARCH_MVEBU
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
-   select SPL_DM
-   select SPL_DM_SEQ_ALIAS
-   select SPL_OF_CONTROL
-   select SPL_SIMPLE_BUS
 
 config TARGET_DEVKIT3250
bool "Support devkit3250"
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 220886a..e01b5c3 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -1,14 +1,37 @@
 if ARCH_MVEBU
 
+config ARMADA_32BIT
+   bool
+   select CPU_V7
+   select SUPPORT_SPL
+   select SPL_DM
+   select SPL_DM_SEQ_ALIAS
+   select SPL_OF_CONTROL
+   select SPL_SIMPLE_BUS
+
+config ARMADA_64BIT
+   bool
+   select ARM64
+
+# ARMv7 SoCs...
 config ARMADA_375
bool
+   select ARMADA_32BIT
 
 config ARMADA_38X
bool
+   select ARMADA_32BIT
 
 config ARMADA_XP
bool
+   select ARMADA_32BIT
+
+# ARMv8 SoCs...
+config ARMADA_3700
+   bool
+   select ARM64
 
+# Armada XP/38x SoC types...
 config MV78230
bool
select ARMADA_XP
@@ -26,7 +49,7 @@ config DB_88F6820_GP
select ARMADA_38X
 
 choice
-   prompt "Marvell MVEBU (Armada XP/375/38x) board select"
+   prompt "Marvell MVEBU (Armada XP/375/38x/3700) board select"
optional
 
 config TARGET_CLEARFOG
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index ac009a3..07dc16c 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -1,16 +1,22 @@
 #
-# Copyright (C) 2014-2015 Stefan Roese 
+# Copyright (C) 2014-2016 Stefan Roese 
 #
 # SPDX-License-Identifier: GPL-2.0+
 #
 
+ifdef CONFIG_ARM64
+
+obj-$(CONFIG_ARMADA_3700) += armada3700/
+
+else # CONFIG_ARM64
+
 ifdef CONFIG_KIRKWOOD
 
 obj-y  = dram.o
 obj-y  += gpio.o
 obj-y  += timer.o
 
-else
+else # CONFIG_KIRKWOOD
 
 obj-y  = cpu.o
 obj-y  += dram.o
@@ -18,7 +24,7 @@ ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_ARMADA_375) += ../../../drivers/ddr/marvell/axp/xor.o
 obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o
 obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o
-endif
+endif # CONFIG_SPL_BUILD
 obj-y  += gpio.o
 obj-y  += mbus.o
 obj-y  += timer.o
@@ -28,4 +34,5 @@ obj-$(CONFIG_SPL_BUILD) += lowlevel_spl.o
 obj-$(CONFIG_ARMADA_38X) += serdes/a38x/
 obj-$(CONFIG_ARMADA_XP) += serdes/axp/
 
-endif
+endif # CONFIG_KIRKWOOD
+endif # CONFIG_ARM64
diff --git a/arch/arm/mach-mvebu/armada3700/Makefile 
b/arch/arm/mach-mvebu/armada3700/Makefile
new file mode 100644
index 000..b1fac57
--- /dev/null
+++ b/arch/arm/mach-mvebu/armada3700/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2016 Stefan Roese 
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = cpu.o
+obj-y += sata.o
diff --git a/arch/arm/mach-mvebu/armada3700/cpu.c 
b/arch/arm/mach-mvebu/armada3700/cpu.c
new file mode 100644
index 000..7d8f7b8
--- /dev/null
+++ b/arch/arm/mach-mvebu/armada3700/cpu.c
@@ -0,0 +1,188 @@
+/*
+ * Copyright (C) 2016 Stefan Roese 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;

[U-Boot] [PATCH 06/15] usb: ehci: ehci-marvell.c: Add Armada 3700 support (ARMv8)

[Stefan Roese]

This patch adds DM based support for the Armada 3700 EHCI controller.
The address windows don't need to get configured in this case. The
difference here is detected via DT compatible property at runtime.

With this support and the DM xHCI driver, both XHCI and eHCI can be
used simultaniously on the MVEBU boards now.

Signed-off-by: Stefan Roese 
Cc: Nadav Haklai 
Cc: Kostya Porotchkin 
Cc: Wilson Ding 
Cc: Victor Gu 
Cc: Hua Jing 
Cc: Terry Zhou 
Cc: Hanna Hawa 
Cc: Haim Boot 
Cc: Marek Vasut 
---
 drivers/usb/host/ehci-marvell.c | 59 -
 1 file changed, 52 insertions(+), 7 deletions(-)

diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c
index 5b0f46a..72b9b30 100644
--- a/drivers/usb/host/ehci-marvell.c
+++ b/drivers/usb/host/ehci-marvell.c
@@ -26,6 +26,16 @@ DECLARE_GLOBAL_DATA_PTR;
 #define USB_WINDOW_BASE(i) (0x324 + ((i) << 4))
 #define USB_TARGET_DRAM0x0
 
+#define USB2_SBUSCFG_OFF   0x90
+
+#define USB_SBUSCFG_BAWR_OFF   0x6
+#define USB_SBUSCFG_BARD_OFF   0x3
+#define USB_SBUSCFG_AHBBRST_OFF0x0
+
+#define USB_SBUSCFG_BAWR_ALIGN_64B 0x4
+#define USB_SBUSCFG_BARD_ALIGN_64B 0x4
+#define USB_SBUSCFG_AHBBRST_INCR16 0x7
+
 /*
  * USB 2.0 Bridge Address Decoding registers setup
  */
@@ -41,7 +51,7 @@ struct ehci_mvebu_priv {
  * to the common mvebu archticture including the mbus setup, this
  * will be the only function needed to configure the access windows
  */
-static void usb_brg_adrdec_setup(u32 base)
+static void usb_brg_adrdec_setup(void *base)
 {
const struct mbus_dram_target_info *dram;
int i;
@@ -66,6 +76,29 @@ static void usb_brg_adrdec_setup(u32 base)
}
 }
 
+static void marvell_ehci_powerup_fixup(struct ehci_ctrl *ctrl,
+  uint32_t *status_reg, uint32_t *reg)
+{
+   struct ehci_mvebu_priv *priv = ctrl->priv;
+
+   /*
+* Set default value for reg SBUSCFG, which is Control for the AMBA
+* system bus interface:
+* BAWR = BARD = 4 : Align rd/wr bursts packets larger than 64 bytes
+* AHBBRST = 7 : Align AHB burst for packets larger than 64 bytes
+*/
+   writel((USB_SBUSCFG_BAWR_ALIGN_64B << USB_SBUSCFG_BAWR_OFF) |
+  (USB_SBUSCFG_BARD_ALIGN_64B << USB_SBUSCFG_BARD_OFF) |
+  (USB_SBUSCFG_AHBBRST_INCR16 << USB_SBUSCFG_AHBBRST_OFF),
+  priv->hcd_base + USB2_SBUSCFG_OFF);
+
+   mdelay(50);
+}
+
+static struct ehci_ops marvell_ehci_ops = {
+   .powerup_fixup  = NULL,
+};
+
 static int ehci_mvebu_probe(struct udevice *dev)
 {
struct ehci_mvebu_priv *priv = dev_get_priv(dev);
@@ -81,17 +114,28 @@ static int ehci_mvebu_probe(struct udevice *dev)
return -ENXIO;
}
 
-   usb_brg_adrdec_setup(priv->hcd_base);
+   /*
+* For SoCs without hlock like Armada3700 we need to program the sbuscfg
+* reg to guarantee AHB master's burst will not overrun or underrun
+* the FIFO. Otherwise all USB2 write option will fail.
+* Also, the address decoder doesn't need to get setup with this
+* SoC, so don't call usb_brg_adrdec_setup().
+*/
+   if (of_device_is_compatible(dev, "marvell,armada3700-ehci"))
+   marvell_ehci_ops.powerup_fixup = marvell_ehci_powerup_fixup;
+   else
+   usb_brg_adrdec_setup((void *)priv->hcd_base);
 
hccr = (struct ehci_hccr *)(priv->hcd_base + 0x100);
hcor = (struct ehci_hcor *)
-   ((u32)hccr + HC_LENGTH(ehci_readl(>cr_capbase)));
+   ((uintptr_t)hccr + HC_LENGTH(ehci_readl(>cr_capbase)));
 
-   debug("ehci-marvell: init hccr %x and hcor %x hc_length %d\n",
- (u32)hccr, (u32)hcor,
- (u32)HC_LENGTH(ehci_readl(>cr_capbase)));
+   debug("ehci-marvell: init hccr %lx and hcor %lx hc_length %ld\n",
+ (uintptr_t)hccr, (uintptr_t)hcor,
+ (uintptr_t)HC_LENGTH(ehci_readl(>cr_capbase)));
 
-   return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
+   return ehci_register(dev, hccr, hcor, _ehci_ops, 0,
+USB_INIT_HOST);
 }
 
 static int ehci_mvebu_remove(struct udevice *dev)
@@ -107,6 +151,7 @@ static int ehci_mvebu_remove(struct udevice *dev)
 
 static const struct udevice_id ehci_usb_ids[] = {
{ .compatible = "marvell,orion-ehci", },
+   { .compatible = "marvell,armada3700-ehci", },
{ }
 };
 
-- 
2.9.3

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[U-Boot] [PATCH 11/15] arm64: mvebu: Armada 3700: Add I2C device tree nodes

[Stefan Roese]

This patch adds the I2C device tree nodes that are still missing to
the Armada 3700 dts files.

Signed-off-by: Stefan Roese 
Cc: Nadav Haklai 
Cc: Kostya Porotchkin 
Cc: Wilson Ding 
Cc: Victor Gu 
Cc: Hua Jing 
Cc: Terry Zhou 
Cc: Hanna Hawa 
Cc: Haim Boot 
---
 arch/arm/dts/armada-3720-db.dts | 5 +
 arch/arm/dts/armada-37xx.dtsi   | 6 ++
 2 files changed, 11 insertions(+)

diff --git a/arch/arm/dts/armada-3720-db.dts b/arch/arm/dts/armada-3720-db.dts
index 87fde2a..ec73786 100644
--- a/arch/arm/dts/armada-3720-db.dts
+++ b/arch/arm/dts/armada-3720-db.dts
@@ -58,6 +58,7 @@
 
aliases {
ethernet0 = 
+   i2c0 = 
spi0 = 
};
 
@@ -72,6 +73,10 @@
phy-mode = "rgmii";
 };
 
+ {
+   status = "okay";
+};
+
 /* CON3 */
  {
status = "okay";
diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi
index 0c01d43..9f350df 100644
--- a/arch/arm/dts/armada-37xx.dtsi
+++ b/arch/arm/dts/armada-37xx.dtsi
@@ -153,6 +153,12 @@
status = "disabled";
};
 
+   i2c0: i2c@11000 {
+   compatible = "marvell,armada-3700-i2c";
+   reg = <0x11000 0x100>;
+   status = "disabled";
+   };
+
spi0: spi@10600 {
compatible = "marvell,armada-3700-spi";
reg = <0x10600 0x50>;
-- 
2.9.3

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[U-Boot] [PATCH 12/15] arm64: mvebu: Armada 3700: Add COMPHY device tree nodes

[Stefan Roese]

This patch adds the COMPHY device tree nodes that are still missing to
the Armada 3700 dts files.

Signed-off-by: Stefan Roese 
Cc: Nadav Haklai 
Cc: Kostya Porotchkin 
Cc: Wilson Ding 
Cc: Victor Gu 
Cc: Hua Jing 
Cc: Terry Zhou 
Cc: Hanna Hawa 
Cc: Haim Boot 
---
 arch/arm/dts/armada-3720-db.dts | 12 
 arch/arm/dts/armada-37xx.dtsi   |  9 +
 2 files changed, 21 insertions(+)

diff --git a/arch/arm/dts/armada-3720-db.dts b/arch/arm/dts/armada-3720-db.dts
index ec73786..192c59f 100644
--- a/arch/arm/dts/armada-3720-db.dts
+++ b/arch/arm/dts/armada-3720-db.dts
@@ -68,6 +68,18 @@
};
 };
 
+ {
+   phy0 {
+   phy-type = ;
+   phy-speed = ;
+   };
+
+   phy1 {
+   phy-type = ;
+   phy-speed = ;
+   };
+};
+
  {
status = "okay";
phy-mode = "rgmii";
diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi
index 9f350df..ceeb6e5 100644
--- a/arch/arm/dts/armada-37xx.dtsi
+++ b/arch/arm/dts/armada-37xx.dtsi
@@ -45,6 +45,7 @@
  */
 
 #include 
+#include 
 
 / {
model = "Marvell Armada 37xx SoC";
@@ -169,6 +170,14 @@
spi-max-frequency = <4>;
status = "disabled";
};
+
+   comphy: comphy@18300 {
+   compatible = "marvell,mvebu-comphy", 
"marvell,comphy-armada-3700";
+   reg = <0x18300 0x28>,
+ <0x1f300 0x3d000>;
+   mux-bitcount = <1>;
+   max-lanes = <2>;
+   };
};
};
 };
-- 
2.9.3

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[U-Boot] [PATCH 09/15] arm64: mvebu: Armada 3700: Add SPI device tree nodes

[Stefan Roese]

This patch adds the SPI device tree nodes that are still missing to
the Armada 3700 dts files.

Signed-off-by: Stefan Roese 
Cc: Nadav Haklai 
Cc: Kostya Porotchkin 
Cc: Wilson Ding 
Cc: Victor Gu 
Cc: Hua Jing 
Cc: Terry Zhou 
Cc: Hanna Hawa 
Cc: Haim Boot 
---
 arch/arm/dts/armada-3720-db.dts | 17 +
 arch/arm/dts/armada-37xx.dtsi   | 11 +++
 2 files changed, 28 insertions(+)

diff --git a/arch/arm/dts/armada-3720-db.dts b/arch/arm/dts/armada-3720-db.dts
index 86110a6..52c90c2 100644
--- a/arch/arm/dts/armada-3720-db.dts
+++ b/arch/arm/dts/armada-3720-db.dts
@@ -56,6 +56,10 @@
stdout-path = "serial0:115200n8";
};
 
+   aliases {
+   spi0 = 
+   };
+
memory {
device_type = "memory";
reg = <0x 0x 0x 0x2000>;
@@ -67,6 +71,19 @@
status = "okay";
 };
 
+ {
+   status = "okay";
+
+   spi-flash@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "st,m25p128", "jedec,spi-nor";
+   reg = <0>; /* Chip select 0 */
+   spi-max-frequency = <5000>;
+   m25p,fast-read;
+   };
+};
+
 /* Exported on the micro USB connector CON32 through an FTDI */
  {
status = "okay";
diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi
index 9e2efb8..bb14f54 100644
--- a/arch/arm/dts/armada-37xx.dtsi
+++ b/arch/arm/dts/armada-37xx.dtsi
@@ -140,6 +140,17 @@
reg = <0x1d0 0x1>, /* GICD */
  <0x1d4 0x4>; /* GICR */
};
+
+   spi0: spi@10600 {
+   compatible = "marvell,armada-3700-spi";
+   reg = <0x10600 0x50>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   #clock-cells = <0>;
+   clock-frequency = <16>;
+   spi-max-frequency = <4>;
+   status = "disabled";
+   };
};
};
 };
-- 
2.9.3

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[U-Boot] [PATCH 07/15] drivers/phy: Add Marvell SerDes / PHY drivers used on Armada 3k

[Stefan Roese]

This version is based on the Marvell U-Boot version with this patch
applied as latest patch:

Git ID 7f408573: "fix: comphy: cp110: add comphy initialization for usb
device mode" from 2016-07-05.

Signed-off-by: Stefan Roese 
Cc: Nadav Haklai 
Cc: Kostya Porotchkin 
Cc: Wilson Ding 
Cc: Victor Gu 
Cc: Hua Jing 
Cc: Terry Zhou 
Cc: Hanna Hawa 
Cc: Haim Boot 
---
 drivers/Kconfig  |   2 +
 drivers/Makefile |   1 +
 drivers/phy/marvell/Kconfig  |   9 +
 drivers/phy/marvell/Makefile |   7 +
 drivers/phy/marvell/comphy.h | 139 +
 drivers/phy/marvell/comphy_a3700.c   | 962 +++
 drivers/phy/marvell/comphy_a3700.h   | 275 +
 drivers/phy/marvell/comphy_core.c| 197 +++
 drivers/phy/marvell/comphy_hpipe.h   | 382 
 drivers/phy/marvell/comphy_mux.c | 118 
 include/dt-bindings/comphy/comphy_data.h |  61 ++
 11 files changed, 2153 insertions(+)
 create mode 100644 drivers/phy/marvell/Kconfig
 create mode 100644 drivers/phy/marvell/Makefile
 create mode 100644 drivers/phy/marvell/comphy.h
 create mode 100644 drivers/phy/marvell/comphy_a3700.c
 create mode 100644 drivers/phy/marvell/comphy_a3700.h
 create mode 100644 drivers/phy/marvell/comphy_core.c
 create mode 100644 drivers/phy/marvell/comphy_hpipe.h
 create mode 100644 drivers/phy/marvell/comphy_mux.c
 create mode 100644 include/dt-bindings/comphy/comphy_data.h

diff --git a/drivers/Kconfig b/drivers/Kconfig
index 4f84469..572 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -46,6 +46,8 @@ source "drivers/pci/Kconfig"
 
 source "drivers/pcmcia/Kconfig"
 
+source "drivers/phy/marvell/Kconfig"
+
 source "drivers/pinctrl/Kconfig"
 
 source "drivers/power/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 7861d34..365cc8d 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -56,6 +56,7 @@ obj-y += misc/
 obj-y += pcmcia/
 obj-y += dfu/
 obj-$(CONFIG_X86) += pch/
+obj-y += phy/marvell/
 obj-y += rtc/
 obj-y += sound/
 obj-y += spmi/
diff --git a/drivers/phy/marvell/Kconfig b/drivers/phy/marvell/Kconfig
new file mode 100644
index 000..4240028
--- /dev/null
+++ b/drivers/phy/marvell/Kconfig
@@ -0,0 +1,9 @@
+config MVEBU_COMPHY_SUPPORT
+   bool "ComPhy SerDes driver"
+   default n
+   help
+ Choose this option to add support
+ for Comphy driver.
+ This driver passes over the lanes
+ and initialize the lane depends on the
+ type and speed.
diff --git a/drivers/phy/marvell/Makefile b/drivers/phy/marvell/Makefile
new file mode 100644
index 000..91df554
--- /dev/null
+++ b/drivers/phy/marvell/Makefile
@@ -0,0 +1,7 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_MVEBU_COMPHY_SUPPORT) += comphy_core.o
+obj-$(CONFIG_MVEBU_COMPHY_SUPPORT) += comphy_mux.o
+obj-$(CONFIG_ARMADA_3700) += comphy_a3700.o
diff --git a/drivers/phy/marvell/comphy.h b/drivers/phy/marvell/comphy.h
new file mode 100644
index 000..5c50e9c
--- /dev/null
+++ b/drivers/phy/marvell/comphy.h
@@ -0,0 +1,139 @@
+/*
+ * Copyright (C) 2015-2016 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _COMPHY_H_
+#define _COMPHY_H_
+
+#include 
+#include 
+
+#if defined(DEBUG)
+#define debug_enter()  printf("> Enter %s\n", __func__);
+#define debug_exit()   printf("< Exit  %s\n", __func__);
+#else
+#define debug_enter()
+#define debug_exit()
+#endif
+
+/* COMPHY registers */
+#define COMMON_PHY_CFG1_REG0x0
+#define COMMON_PHY_CFG1_PWR_UP_OFFSET  1
+#define COMMON_PHY_CFG1_PWR_UP_MASK\
+   (0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET)
+#define COMMON_PHY_CFG1_PIPE_SELECT_OFFSET 2
+#define COMMON_PHY_CFG1_PIPE_SELECT_MASK   \
+   (0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET)
+#define COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET13
+#define COMMON_PHY_CFG1_PWR_ON_RESET_MASK  \
+   (0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET)
+#define COMMON_PHY_CFG1_CORE_RSTN_OFFSET   14
+#define COMMON_PHY_CFG1_CORE_RSTN_MASK \
+   (0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET)
+#define COMMON_PHY_PHY_MODE_OFFSET 15
+#define COMMON_PHY_PHY_MODE_MASK   \
+   (0x1 << COMMON_PHY_PHY_MODE_OFFSET)
+
+#define COMMON_PHY_CFG6_REG0x14
+#define COMMON_PHY_CFG6_IF_40_SEL_OFFSET   18
+#define COMMON_PHY_CFG6_IF_40_SEL_MASK \
+   (0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET)
+
+#define COMMON_SELECTOR_PHY_OFFSET 0x140
+#define COMMON_SELECTOR_PIPE_OFFSET0x144
+
+#define COMMON_PHY_SD_CTRL10x148
+#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET 0
+#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK   

[U-Boot] [PATCH 15/15] arm64: mvebu: Add Armada 3700 db-88f3720 development board support

[Stefan Roese]

This patch adds basic support for the Marvell Armada 3700 DB-88F3720
development board. Supported are the following interfaces:
- UART
- SPI (incl. SPI NOR)
- I2C
- Ethernet

Signed-off-by: Stefan Roese 
Cc: Nadav Haklai 
Cc: Kostya Porotchkin 
Cc: Wilson Ding 
Cc: Victor Gu 
Cc: Hua Jing 
Cc: Terry Zhou 
Cc: Hanna Hawa 
Cc: Haim Boot 
---
 arch/arm/mach-mvebu/Kconfig|   7 ++
 board/Marvell/mvebu_db-88f3720/MAINTAINERS |   6 ++
 board/Marvell/mvebu_db-88f3720/Makefile|   7 ++
 board/Marvell/mvebu_db-88f3720/board.c | 134 ++
 configs/mvebu_db-88f3720_defconfig |  49 ++
 include/configs/mvebu_db-88f3720.h | 145 +
 6 files changed, 348 insertions(+)
 create mode 100644 board/Marvell/mvebu_db-88f3720/MAINTAINERS
 create mode 100644 board/Marvell/mvebu_db-88f3720/Makefile
 create mode 100644 board/Marvell/mvebu_db-88f3720/board.c
 create mode 100644 configs/mvebu_db-88f3720_defconfig
 create mode 100644 include/configs/mvebu_db-88f3720.h

diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index e01b5c3..bede700 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -56,6 +56,10 @@ config TARGET_CLEARFOG
bool "Support ClearFog"
select DB_88F6820_GP
 
+config TARGET_MVEBU_DB_88F3720
+   bool "Support DB-88F3720 Armada 3720"
+   select ARMADA_3700
+
 config TARGET_DB_88F6720
bool "Support DB-88F6720 Armada 375"
select ARMADA_375
@@ -84,6 +88,7 @@ endchoice
 
 config SYS_BOARD
default "clearfog" if TARGET_CLEARFOG
+   default "mvebu_db-88f3720" if TARGET_MVEBU_DB_88F3720
default "db-88f6720" if TARGET_DB_88F6720
default "db-88f6820-gp" if TARGET_DB_88F6820_GP
default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
@@ -93,6 +98,7 @@ config SYS_BOARD
 
 config SYS_CONFIG_NAME
default "clearfog" if TARGET_CLEARFOG
+   default "mvebu_db-88f3720" if TARGET_MVEBU_DB_88F3720
default "db-88f6720" if TARGET_DB_88F6720
default "db-88f6820-gp" if TARGET_DB_88F6820_GP
default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
@@ -102,6 +108,7 @@ config SYS_CONFIG_NAME
 
 config SYS_VENDOR
default "Marvell" if TARGET_DB_MV784MP_GP
+   default "Marvell" if TARGET_MVEBU_DB_88F3720
default "Marvell" if TARGET_DB_88F6720
default "Marvell" if TARGET_DB_88F6820_GP
default "solidrun" if TARGET_CLEARFOG
diff --git a/board/Marvell/mvebu_db-88f3720/MAINTAINERS 
b/board/Marvell/mvebu_db-88f3720/MAINTAINERS
new file mode 100644
index 000..4e80917
--- /dev/null
+++ b/board/Marvell/mvebu_db-88f3720/MAINTAINERS
@@ -0,0 +1,6 @@
+MVEBU_DB_88F3720 BOARD
+M: Stefan Roese 
+S: Maintained
+F: board/Marvell/mvebu_db-88f3720/
+F: include/configs/mvebu_db-88f3720.h
+F: configs/mvebu_db-88f3720_defconfig
diff --git a/board/Marvell/mvebu_db-88f3720/Makefile 
b/board/Marvell/mvebu_db-88f3720/Makefile
new file mode 100644
index 000..ed39738
--- /dev/null
+++ b/board/Marvell/mvebu_db-88f3720/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2016 Stefan Roese 
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  := board.o
diff --git a/board/Marvell/mvebu_db-88f3720/board.c 
b/board/Marvell/mvebu_db-88f3720/board.c
new file mode 100644
index 000..edf88c7
--- /dev/null
+++ b/board/Marvell/mvebu_db-88f3720/board.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright (C) 2016 Stefan Roese 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* IO expander I2C device */
+#define I2C_IO_EXP_ADDR0x22
+#define I2C_IO_CFG_REG_0   0x6
+#define I2C_IO_DATA_OUT_REG_0  0x2
+#define I2C_IO_REG_0_SATA_OFF  2
+#define I2C_IO_REG_0_USB_H_OFF 1
+
+int board_early_init_f(void)
+{
+   /* Nothing to do (yet), perhaps later some pin-muxing etc */
+
+   return 0;
+}
+
+int board_init(void)
+{
+   /* adress of boot parameters */
+   gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+   return 0;
+}
+
+/* Board specific AHCI / SATA enable code */
+int board_ahci_enable(void)
+{
+   struct udevice *dev;
+   int ret;
+   u8 buf[8];
+
+   /* Configure IO exander PCA9555: 7bit address 0x22 */
+   ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, );
+   if (ret) {
+   printf("Cannot find PCA9555: %d\n", ret);
+   return 0;
+   }
+
+   ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
+   if (ret) {
+   printf("Failed to read IO expander value via I2C\n");
+   return -EIO;
+   }
+
+   /*
+* Enable SATA power via IO expander connected via I2C by setting
+

[U-Boot] [PATCH 10/15] arm64: mvebu: Armada 3700: Add ethernet device tree nodes

[Stefan Roese]

This patch adds the ethernet device tree nodes that are still missing to
the Armada 3700 dts files.

Signed-off-by: Stefan Roese 
Cc: Nadav Haklai 
Cc: Kostya Porotchkin 
Cc: Wilson Ding 
Cc: Victor Gu 
Cc: Hua Jing 
Cc: Terry Zhou 
Cc: Hanna Hawa 
Cc: Haim Boot 
---
 arch/arm/dts/armada-3720-db.dts |  6 ++
 arch/arm/dts/armada-37xx.dtsi   | 12 
 2 files changed, 18 insertions(+)

diff --git a/arch/arm/dts/armada-3720-db.dts b/arch/arm/dts/armada-3720-db.dts
index 52c90c2..87fde2a 100644
--- a/arch/arm/dts/armada-3720-db.dts
+++ b/arch/arm/dts/armada-3720-db.dts
@@ -57,6 +57,7 @@
};
 
aliases {
+   ethernet0 = 
spi0 = 
};
 
@@ -66,6 +67,11 @@
};
 };
 
+ {
+   status = "okay";
+   phy-mode = "rgmii";
+};
+
 /* CON3 */
  {
status = "okay";
diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi
index bb14f54..0c01d43 100644
--- a/arch/arm/dts/armada-37xx.dtsi
+++ b/arch/arm/dts/armada-37xx.dtsi
@@ -141,6 +141,18 @@
  <0x1d4 0x4>; /* GICR */
};
 
+   eth0: neta@3 {
+   compatible = "marvell,armada-3700-neta";
+   reg = <0x3 0x20>;
+   status = "disabled";
+   };
+
+   eth1: neta@4 {
+   compatible = "marvell,armada-3700-neta";
+   reg = <0x4 0x20>;
+   status = "disabled";
+   };
+
spi0: spi@10600 {
compatible = "marvell,armada-3700-spi";
reg = <0x10600 0x50>;
-- 
2.9.3

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[U-Boot] [PATCH 13/15] arm64: mvebu: Armada 3700: Add USB device tree nodes

[Stefan Roese]

This patch adds the USB device tree nodes that are still missing to
the Armada 3700 dts files.

Signed-off-by: Stefan Roese 
Cc: Nadav Haklai 
Cc: Kostya Porotchkin 
Cc: Wilson Ding 
Cc: Victor Gu 
Cc: Hua Jing 
Cc: Terry Zhou 
Cc: Hanna Hawa 
Cc: Haim Boot 
---
 arch/arm/dts/armada-3720-db.dts | 5 +
 arch/arm/dts/armada-37xx.dtsi   | 6 ++
 2 files changed, 11 insertions(+)

diff --git a/arch/arm/dts/armada-3720-db.dts b/arch/arm/dts/armada-3720-db.dts
index 192c59f..1ebfa1e 100644
--- a/arch/arm/dts/armada-3720-db.dts
+++ b/arch/arm/dts/armada-3720-db.dts
@@ -112,6 +112,11 @@
status = "okay";
 };
 
+/* CON29 */
+ {
+   status = "okay";
+};
+
 /* CON31 */
  {
status = "okay";
diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi
index ceeb6e5..e27eae0 100644
--- a/arch/arm/dts/armada-37xx.dtsi
+++ b/arch/arm/dts/armada-37xx.dtsi
@@ -114,6 +114,12 @@
status = "disabled";
};
 
+   usb2: usb@5e000 {
+   compatible = "marvell,armada3700-ehci";
+   reg = <0x5e000 0x450>;
+   status = "disabled";
+   };
+
xor@60900 {
compatible = "marvell,armada-3700-xor";
reg = <0x60900 0x100
-- 
2.9.3

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[U-Boot] [PATCH 04/15] net: mvneta: Add support for Armada 3700 SoC

[Stefan Roese]

This patch adds support for the Armada 3700 SoC to the Marvell mvneta
network driver.

Not like A380, in Armada3700, there are two layers of decode windows for GBE:
First layer is:  GbE Address window that resides inside the GBE unit,
Second layer is: Fabric address window which is located in the NIC400
 (South Fabric).
To simplify the address decode configuration for Armada3700, we bypass the
first layer of GBE decode window by setting the first window to 4GB.

Signed-off-by: Stefan Roese 
Cc: Nadav Haklai 
Cc: Kostya Porotchkin 
Cc: Wilson Ding 
Cc: Victor Gu 
Cc: Hua Jing 
Cc: Terry Zhou 
Cc: Hanna Hawa 
Cc: Haim Boot 
Cc: Joe Hershberger 
---
 drivers/net/mvneta.c | 39 ++-
 1 file changed, 38 insertions(+), 1 deletion(-)

diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c
index 433e186..2b98a92 100644
--- a/drivers/net/mvneta.c
+++ b/drivers/net/mvneta.c
@@ -91,7 +91,10 @@ DECLARE_GLOBAL_DATA_PTR;
 #define MVNETA_WIN_BASE(w)  (0x2200 + ((w) << 3))
 #define MVNETA_WIN_SIZE(w)  (0x2204 + ((w) << 3))
 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
+#define MVNETA_WIN_SIZE_MASK   (0x)
 #define MVNETA_BASE_ADDR_ENABLE 0x2290
+#define MVNETA_PORT_ACCESS_PROTECT  0x2294
+#define  MVNETA_PORT_ACCESS_PROTECT_WIN0_RW0x3
 #define MVNETA_PORT_CONFIG  0x2400
 #define  MVNETA_UNI_PROMISC_MODEBIT(0)
 #define  MVNETA_DEF_RXQ(q)  ((q) << 1)
@@ -1241,6 +1244,36 @@ static int mvneta_init2(struct mvneta_port *pp)
 }
 
 /* platform glue : initialize decoding windows */
+
+/*
+ * Not like A380, in Armada3700, there are two layers of decode windows for 
GBE:
+ * First layer is:  GbE Address window that resides inside the GBE unit,
+ * Second layer is: Fabric address window which is located in the NIC400
+ *  (South Fabric).
+ * To simplify the address decode configuration for Armada3700, we bypass the
+ * first layer of GBE decode window by setting the first window to 4GB.
+ */
+static void mvneta_bypass_mbus_windows(struct mvneta_port *pp)
+{
+   u32 tmp_value;
+
+   /*
+* Set window size to 4GB, to bypass GBE address decode, leave the
+* work to MBUS decode window
+*/
+   mvreg_write(pp, MVNETA_WIN_SIZE(0), MVNETA_WIN_SIZE_MASK);
+
+   /* Enable GBE address decode window 0 by set bit 0 to 0 */
+   tmp_value = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE);
+   tmp_value = tmp_value & ~(1);
+   mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, tmp_value);
+
+   /* Set GBE address decode window 0 to full Access (read or write) */
+   tmp_value = mvreg_read(pp, MVNETA_PORT_ACCESS_PROTECT);
+   tmp_value = tmp_value | MVNETA_PORT_ACCESS_PROTECT_WIN0_RW;
+   mvreg_write(pp, MVNETA_PORT_ACCESS_PROTECT, tmp_value);
+}
+
 static void mvneta_conf_mbus_windows(struct mvneta_port *pp)
 {
const struct mbus_dram_target_info *dram;
@@ -1609,7 +1642,10 @@ static int mvneta_probe(struct udevice *dev)
pp->base = (void __iomem *)pdata->iobase;
 
/* Configure MBUS address windows */
-   mvneta_conf_mbus_windows(pp);
+   if (of_device_is_compatible(dev, "marvell,armada-3700-neta"))
+   mvneta_bypass_mbus_windows(pp);
+   else
+   mvneta_conf_mbus_windows(pp);
 
/* PHY interface is already decoded in mvneta_ofdata_to_platdata() */
pp->phy_interface = pdata->phy_interface;
@@ -1672,6 +1708,7 @@ static int mvneta_ofdata_to_platdata(struct udevice *dev)
 static const struct udevice_id mvneta_ids[] = {
{ .compatible = "marvell,armada-370-neta" },
{ .compatible = "marvell,armada-xp-neta" },
+   { .compatible = "marvell,armada-3700-neta" },
{ }
 };
 
-- 
2.9.3

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[U-Boot] [PATCH 03/15] net: mvneta: Make driver 64bit safe

[Stefan Roese]

The mvneta driver is also used on the ARMv8 64bit Armada 3700 SoC. This
patch fixes the compilation warnings seen on this 64bit platform.

Signed-off-by: Stefan Roese 
Cc: Nadav Haklai 
Cc: Kostya Porotchkin 
Cc: Wilson Ding 
Cc: Victor Gu 
Cc: Hua Jing 
Cc: Terry Zhou 
Cc: Hanna Hawa 
Cc: Haim Boot 
Cc: Joe Hershberger 
---
 drivers/net/mvneta.c | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c
index c23fe9a..433e186 100644
--- a/drivers/net/mvneta.c
+++ b/drivers/net/mvneta.c
@@ -1022,7 +1022,7 @@ static int mvneta_txq_init(struct mvneta_port *pp,
txq->size = pp->tx_ring_size;
 
/* Allocate memory for TX descriptors */
-   txq->descs_phys = (u32)txq->descs;
+   txq->descs_phys = (dma_addr_t)txq->descs;
if (txq->descs == NULL)
return -ENOMEM;
 
@@ -1504,10 +1504,10 @@ static int mvneta_send(struct udevice *dev, void 
*packet, int length)
/* Get a descriptor for the first part of the packet */
tx_desc = mvneta_txq_next_desc_get(txq);
 
-   tx_desc->buf_phys_addr = (u32)packet;
+   tx_desc->buf_phys_addr = (u32)(uintptr_t)packet;
tx_desc->data_size = length;
-   flush_dcache_range((u32)packet,
-  (u32)packet + ALIGN(length, PKTALIGN));
+   flush_dcache_range((ulong)packet,
+  (ulong)packet + ALIGN(length, PKTALIGN));
 
/* First and Last descriptor */
tx_desc->command = MVNETA_TX_L4_CSUM_NOT | MVNETA_TXD_FLZ_DESC;
@@ -1563,7 +1563,7 @@ static int mvneta_recv(struct udevice *dev, int flags, 
uchar **packetp)
rx_bytes = rx_desc->data_size - 6;
 
/* give packet to stack - skip on first 2 bytes */
-   data = (u8 *)rx_desc->buf_cookie + 2;
+   data = (u8 *)(uintptr_t)rx_desc->buf_cookie + 2;
/*
 * No cache invalidation needed here, since the rx_buffer's are
 * located in a uncached memory region
@@ -1594,13 +1594,13 @@ static int mvneta_probe(struct udevice *dev)
if (!buffer_loc.tx_descs) {
/* Align buffer area for descs and rx_buffers to 1MiB */
bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
-   mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE,
+   mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, BD_SPACE,
DCACHE_OFF);
buffer_loc.tx_descs = (struct mvneta_tx_desc *)bd_space;
buffer_loc.rx_descs = (struct mvneta_rx_desc *)
-   ((u32)bd_space +
+   ((phys_addr_t)bd_space +
 MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc));
-   buffer_loc.rx_buffers = (u32)
+   buffer_loc.rx_buffers = (phys_addr_t)
(bd_space +
 MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc) +
 MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc));
-- 
2.9.3

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[U-Boot] [PATCH 05/15] usb: xhci: Add Marvell MVEBU xHCI support

[Stefan Roese]

This patch adds DM based support for the xHCI USB 3.0 controller
integrated in the Armada 3700 SoC. It may be extended to be used
by other MVEBU SoCs as well.

Signed-off-by: Stefan Roese 
Cc: Nadav Haklai 
Cc: Kostya Porotchkin 
Cc: Wilson Ding 
Cc: Victor Gu 
Cc: Hua Jing 
Cc: Terry Zhou 
Cc: Hanna Hawa 
Cc: Haim Boot 
Cc: Marek Vasut 
---
 drivers/usb/host/Kconfig  |  9 
 drivers/usb/host/Makefile |  1 +
 drivers/usb/host/xhci-mvebu.c | 96 +++
 3 files changed, 106 insertions(+)
 create mode 100644 drivers/usb/host/xhci-mvebu.c

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index e0699d4..f996c75 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -28,6 +28,15 @@ config USB_XHCI_DWC3
  Say Y or if your system has a Dual Role SuperSpeed
  USB controller based on the DesignWare USB3 IP Core.
 
+config USB_XHCI_MVEBU
+   bool "MVEBU USB 3.0 support"
+   default y
+   depends on ARCH_MVEBU
+   help
+ Choose this option to add support for USB 3.0 driver on mvebu
+ SoCs, which includes Armada8K, Armada3700 and other Armada
+ family SoCs.
+
 endif # USB_XHCI_HCD
 
 config USB_EHCI_HCD
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 620d114..519325d 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -60,6 +60,7 @@ obj-$(CONFIG_USB_XHCI_ZYNQMP) += xhci-zynqmp.o
 obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
 obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
 obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o
+obj-$(CONFIG_USB_XHCI_MVEBU) += xhci-mvebu.o
 obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
 obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
 obj-$(CONFIG_USB_XHCI_UNIPHIER) += xhci-uniphier.o
diff --git a/drivers/usb/host/xhci-mvebu.c b/drivers/usb/host/xhci-mvebu.c
new file mode 100644
index 000..e09e87a
--- /dev/null
+++ b/drivers/usb/host/xhci-mvebu.c
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2015 Marvell International Ltd.
+ *
+ * MVEBU USB HOST xHCI Controller
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "xhci.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct mvebu_xhci_platdata {
+   fdt_addr_t hcd_base;
+};
+
+/**
+ * Contains pointers to register base addresses
+ * for the usb controller.
+ */
+struct mvebu_xhci {
+   struct xhci_ctrl ctrl;  /* Needs to come first in this struct! */
+   struct usb_platdata usb_plat;
+   struct xhci_hccr *hcd;
+};
+
+/*
+ * Dummy implementation that can be overwritten by a board
+ * specific function
+ */
+__weak int board_xhci_enable(void)
+{
+   return 0;
+}
+
+static int xhci_usb_probe(struct udevice *dev)
+{
+   struct mvebu_xhci_platdata *plat = dev_get_platdata(dev);
+   struct mvebu_xhci *ctx = dev_get_priv(dev);
+   struct xhci_hcor *hcor;
+   int len;
+
+   ctx->hcd = (struct xhci_hccr *)plat->hcd_base;
+   len = HC_LENGTH(xhci_readl(>hcd->cr_capbase));
+   hcor = (struct xhci_hcor *)((uintptr_t)ctx->hcd + len);
+
+   /* Enable USB xHCI (VBUS, reset etc) in board specific code */
+   board_xhci_enable();
+
+   return xhci_register(dev, ctx->hcd, hcor);
+}
+
+static int xhci_usb_remove(struct udevice *dev)
+{
+   return xhci_deregister(dev);
+}
+
+static int xhci_usb_ofdata_to_platdata(struct udevice *dev)
+{
+   struct mvebu_xhci_platdata *plat = dev_get_platdata(dev);
+
+   /*
+* Get the base address for XHCI controller from the device node
+*/
+   plat->hcd_base = dev_get_addr(dev);
+   if (plat->hcd_base == FDT_ADDR_T_NONE) {
+   debug("Can't get the XHCI register base address\n");
+   return -ENXIO;
+   }
+
+   return 0;
+}
+
+static const struct udevice_id xhci_usb_ids[] = {
+   { .compatible = "marvell,armada3700-xhci" },
+   { }
+};
+
+U_BOOT_DRIVER(usb_xhci) = {
+   .name   = "xhci_mvebu",
+   .id = UCLASS_USB,
+   .of_match = xhci_usb_ids,
+   .ofdata_to_platdata = xhci_usb_ofdata_to_platdata,
+   .probe = xhci_usb_probe,
+   .remove = xhci_usb_remove,
+   .ops= _usb_ops,
+   .platdata_auto_alloc_size = sizeof(struct mvebu_xhci_platdata),
+   .priv_auto_alloc_size = sizeof(struct mvebu_xhci),
+   .flags  = DM_FLAG_ALLOC_PRIV_DMA,
+};
-- 
2.9.3

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[U-Boot] [PATCH 08/15] arm64: mvebu: Armada 3700: Add Armada 37xx dts files

[Stefan Roese]

This patch integrates the Armada 3700 dts files from the latest
submission on the linux-arm-kernel mailing list.

Signed-off-by: Stefan Roese 
Cc: Nadav Haklai 
Cc: Kostya Porotchkin 
Cc: Wilson Ding 
Cc: Victor Gu 
Cc: Hua Jing 
Cc: Terry Zhou 
Cc: Hanna Hawa 
Cc: Haim Boot 
---
 arch/arm/dts/Makefile   |   1 +
 arch/arm/dts/armada-371x.dtsi   |  53 +++
 arch/arm/dts/armada-3720-db.dts |  78 +
 arch/arm/dts/armada-372x.dtsi   |  62 +
 arch/arm/dts/armada-37xx.dtsi   | 145 
 5 files changed, 339 insertions(+)
 create mode 100644 arch/arm/dts/armada-371x.dtsi
 create mode 100644 arch/arm/dts/armada-3720-db.dts
 create mode 100644 arch/arm/dts/armada-372x.dtsi
 create mode 100644 arch/arm/dts/armada-37xx.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a4ab069..4a51de1 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -67,6 +67,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra210-p2571.dtb
 
 dtb-$(CONFIG_ARCH_MVEBU) +=\
+   armada-3720-db.dtb  \
armada-375-db.dtb   \
armada-388-clearfog.dtb \
armada-388-gp.dtb   \
diff --git a/arch/arm/dts/armada-371x.dtsi b/arch/arm/dts/armada-371x.dtsi
new file mode 100644
index 000..c9e5325
--- /dev/null
+++ b/arch/arm/dts/armada-371x.dtsi
@@ -0,0 +1,53 @@
+/*
+ * Device Tree Include file for Marvell Armada 371x family of SoCs
+ * (also named 88F3710)
+ *
+ * Copyright (C) 2016 Marvell
+ *
+ * Gregory CLEMENT 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "armada-37xx.dtsi"
+
+/ {
+   model = "Marvell Armada 3710 SoC";
+   compatible = "marvell,armada3710", "marvell,armada3700";
+};
diff --git a/arch/arm/dts/armada-3720-db.dts b/arch/arm/dts/armada-3720-db.dts
new file mode 100644
index 000..86110a6
--- /dev/null
+++ b/arch/arm/dts/armada-3720-db.dts
@@ -0,0 +1,78 @@
+/*
+ * Device Tree file for Marvell Armada 3720 development board
+ * (DB-88F3720-DDR3)
+ * Copyright (C) 2016 Marvell
+ *
+ * Gregory CLEMENT 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY 

[U-Boot] [PATCH 02/15] spi: Add driver for Marvell Armada 3700 SoC

[Stefan Roese]

The SPI IP core in the Marvell Armada 3700 is similar to the one in the
other Armada SoCs. But the differences are big enough that it makes
sense to introduce a new driver instead of cluttering the old
kirkwood driver with #ifdef's.

Signed-off-by: Stefan Roese 
Cc: Nadav Haklai 
Cc: Kostya Porotchkin 
Cc: Wilson Ding 
Cc: Victor Gu 
Cc: Hua Jing 
Cc: Terry Zhou 
Cc: Hanna Hawa 
Cc: Haim Boot 
Cc: Jagan Teki 
---
 drivers/spi/Kconfig   |   7 ++
 drivers/spi/Makefile  |   1 +
 drivers/spi/mvebu_a3700_spi.c | 281 ++
 3 files changed, 289 insertions(+)
 create mode 100644 drivers/spi/mvebu_a3700_spi.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index aca385d..bc5e716 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -75,6 +75,13 @@ config ICH_SPI
  access the SPI NOR flash on platforms embedding this Intel
  ICH IP core.
 
+config MVEBU_A3700_SPI
+   bool "Marvell Armada 3700 SPI driver"
+   help
+ Enable the Marvell Armada 3700 SPI driver. This driver can be
+ used to access the SPI NOR flash on platforms embedding this
+ Marvell IP core.
+
 config PIC32_SPI
bool "Microchip PIC32 SPI driver"
depends on MACH_PIC32
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index b1d9e20..247c5f6 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
 obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
 obj-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
 obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
+obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
 obj-$(CONFIG_MXC_SPI) += mxc_spi.o
 obj-$(CONFIG_MXS_SPI) += mxs_spi.o
 obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
diff --git a/drivers/spi/mvebu_a3700_spi.c b/drivers/spi/mvebu_a3700_spi.c
new file mode 100644
index 000..26f9a8f
--- /dev/null
+++ b/drivers/spi/mvebu_a3700_spi.c
@@ -0,0 +1,281 @@
+/*
+ * Copyright (C) 2015 Marvell International Ltd.
+ *
+ * Copyright (C) 2016 Stefan Roese 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SPI_TIMEOUT1
+
+#define MVEBU_SPI_A3700_XFER_RDY   BIT(1)
+#define MVEBU_SPI_A3700_FIFO_FLUSH BIT(9)
+#define MVEBU_SPI_A3700_BYTE_LEN   BIT(5)
+#define MVEBU_SPI_A3700_CLK_PHABIT(6)
+#define MVEBU_SPI_A3700_CLK_POLBIT(7)
+#define MVEBU_SPI_A3700_FIFO_ENBIT(17)
+#define MVEBU_SPI_A3700_SPI_EN_0   BIT(16)
+#define MVEBU_SPI_A3700_CLK_PRESCALE_BIT   0
+#define MVEBU_SPI_A3700_CLK_PRESCALE_MASK  \
+   (0x1f << MVEBU_SPI_A3700_CLK_PRESCALE_BIT)
+
+/* SPI registers */
+struct spi_reg {
+   u32 ctrl;   /* 0x10600 */
+   u32 cfg;/* 0x10604 */
+   u32 dout;   /* 0x10608 */
+   u32 din;/* 0x1060c */
+};
+
+struct mvebu_spi_platdata {
+   struct spi_reg *spireg;
+};
+
+static void spi_cs_activate(struct spi_reg *reg, int cs)
+{
+   setbits_le32(>ctrl, MVEBU_SPI_A3700_SPI_EN_0 << cs);
+}
+
+static void spi_cs_deactivate(struct spi_reg *reg, int cs)
+{
+   clrbits_le32(>ctrl, MVEBU_SPI_A3700_SPI_EN_0 << cs);
+}
+
+/**
+ * spi_legacy_shift_byte() - triggers the real SPI transfer
+ * @bytelen:   Indicate how many bytes to transfer.
+ * @dout:  Buffer address of what to send.
+ * @din:   Buffer address of where to receive.
+ *
+ * This function triggers the real SPI transfer in legacy mode. It
+ * will shift out char buffer from @dout, and shift in char buffer to
+ * @din, if necessary.
+ *
+ * This function assumes that only one byte is shifted at one time.
+ * However, it is not its responisbility to set the transfer type to
+ * one-byte. Also, it does not guarantee that it will work if transfer
+ * type becomes two-byte. See spi_set_legacy() for details.
+ *
+ * In legacy mode, simply write to the SPI_DOUT register will trigger
+ * the transfer.
+ *
+ * If @dout == NULL, which means no actual data needs to be sent out,
+ * then the function will shift out 0x00 in order to shift in data.
+ * The XFER_RDY flag is checked every time before accessing SPI_DOUT
+ * and SPI_DIN register.
+ *
+ * The number of transfers to be triggerred is decided by @bytelen.
+ *
+ * Return: 0 - cool
+ * -ETIMEDOUT - XFER_RDY flag timeout
+ */
+static int spi_legacy_shift_byte(struct spi_reg *reg, unsigned int bytelen,
+const void *dout, void *din)
+{
+   const u8 *dout_8;
+   u8 *din_8;
+   int ret;
+
+   /* Use 0x00 as dummy dout */
+   const u8 dummy_dout = 0x0;
+   u32 

[U-Boot] [PATCH 01/15] serial: Add serial_mvebu_a3700 for Armada 3700 SoC

[Stefan Roese]

The Armada 3700's UART is a simple serial port. It has a 32 bytes
Tx FIFO and a 64 bytes Rx FIFO integrated. This patch adds support
for this UART including the DEBUG UART functions for very early
debug output.

Signed-off-by: Stefan Roese 
Cc: Nadav Haklai 
Cc: Kostya Porotchkin 
Cc: Wilson Ding 
Cc: Victor Gu 
Cc: Hua Jing 
Cc: Terry Zhou 
Cc: Hanna Hawa 
Cc: Haim Boot 
---
 drivers/serial/Kconfig  |  15 
 drivers/serial/Makefile |   1 +
 drivers/serial/serial_mvebu_a3700.c | 173 
 3 files changed, 189 insertions(+)
 create mode 100644 drivers/serial/serial_mvebu_a3700.c

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index ab5df70..541cf2e 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -147,6 +147,13 @@ config DEBUG_UART_ARM_DCC
  This port is available at least on ARMv6, ARMv7, ARMv8 and XScale
  architectures.
 
+config DEBUG_MVEBU_A3700_UART
+   bool "Marvell Armada 3700"
+   help
+ Select this to enable a debug UART using the serial_mvebu driver. You
+ will need to provide parameters to make this work. The driver will
+ be available until the real driver-model serial is running.
+
 config DEBUG_UART_ZYNQ
bool "Xilinx Zynq"
help
@@ -295,6 +302,13 @@ config FSL_LPUART
  Select this to enable a Low Power UART for Freescale VF610 and
  QorIQ Layerscape devices.
 
+config MVEBU_A3700_UART
+   bool "UART support for Armada 3700"
+   default n
+   help
+ Choose this option to add support for UART driver on the Marvell
+ Armada 3700 SoC. The base address is configured via DT.
+
 config PIC32_SERIAL
bool "Support for Microchip PIC32 on-chip UART"
depends on DM_SERIAL && MACH_PIC32
@@ -371,4 +385,5 @@ config MSM_SERIAL
  It should support all Qualcomm devices with UARTDM version 1.4,
  for example APQ8016 and MSM8916.
  Single baudrate is supported in current implementation (115200).
+
 endmenu
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 6986d65..21b1292 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o
 obj-$(CONFIG_STM32X7_SERIAL) += serial_stm32x7.o
 obj-$(CONFIG_BCM283X_MU_SERIAL) += serial_bcm283x_mu.o
 obj-$(CONFIG_MSM_SERIAL) += serial_msm.o
+obj-$(CONFIG_MVEBU_A3700_UART) += serial_mvebu_a3700.o
 
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial_mvebu_a3700.c 
b/drivers/serial/serial_mvebu_a3700.c
new file mode 100644
index 000..e7b2db1
--- /dev/null
+++ b/drivers/serial/serial_mvebu_a3700.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright (C) 2016 Stefan Roese 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+struct mvebu_platdata {
+   void __iomem *base;
+};
+
+/*
+ * Register offset
+ */
+#define UART_RX_REG0x00
+#define UART_TX_REG0x04
+#define UART_CTRL_REG  0x08
+#define UART_STATUS_REG0x0c
+#define UART_BAUD_REG  0x10
+#define UART_POSSR_REG 0x14
+
+#define UART_STATUS_RX_RDY 0x10
+#define UART_STATUS_TXFIFO_FULL0x800
+
+#define UART_CTRL_RXFIFO_RESET 0x4000
+#define UART_CTRL_TXFIFO_RESET 0x8000
+
+static int mvebu_serial_putc(struct udevice *dev, const char ch)
+{
+   struct mvebu_platdata *plat = dev_get_platdata(dev);
+   void __iomem *base = plat->base;
+
+   while (readl(base + UART_STATUS_REG) & UART_STATUS_TXFIFO_FULL)
+   ;
+
+   writel(ch, base + UART_TX_REG);
+
+   return 0;
+}
+
+static int mvebu_serial_getc(struct udevice *dev)
+{
+   struct mvebu_platdata *plat = dev_get_platdata(dev);
+   void __iomem *base = plat->base;
+
+   while (!(readl(base + UART_STATUS_REG) & UART_STATUS_RX_RDY))
+   ;
+
+   return readl(base + UART_RX_REG) & 0xff;
+}
+
+static int mvebu_serial_pending(struct udevice *dev, bool input)
+{
+   struct mvebu_platdata *plat = dev_get_platdata(dev);
+   void __iomem *base = plat->base;
+
+   if (readl(base + UART_STATUS_REG) & UART_STATUS_RX_RDY)
+   return 1;
+
+   return 0;
+}
+
+static int mvebu_serial_setbrg(struct udevice *dev, int baudrate)
+{
+   struct mvebu_platdata *plat = dev_get_platdata(dev);
+   void __iomem *base = plat->base;
+
+   /*
+* Calculate divider
+* baudrate = clock / 16 / divider
+*/
+   writel(CONFIG_UART_BASE_CLOCK / baudrate / 16, base + UART_BAUD_REG);
+
+   /*
+* Set Programmable Oversampling Stack to 0,
+* UART defaults to 16x scheme
+*/
+   writel(0, base + UART_POSSR_REG);
+
+ 

[U-Boot] [PATCH 7/7] i2c: mvtwsi.c: Add support for Marvell Armada 7K/8K

[Stefan Roese]

By adding the "marvell,mv78230-i2c" compatible property, we can enable
this I2C driver to support these new ARM64 chips as well.

Signed-off-by: Stefan Roese 
Cc: Nadav Haklai 
Cc: Neta Zur Hershkovits 
Cc: Kostya Porotchkin 
Cc: Omri Itach 
Cc: Igal Liberman 
Cc: Haim Boot 
Cc: Hanna Hawa 
Cc: Heiko Schocher 
---
 drivers/i2c/mvtwsi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index 3765fed..9d36e44 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -830,6 +830,7 @@ static const struct dm_i2c_ops mvtwsi_i2c_ops = {
 
 static const struct udevice_id mvtwsi_i2c_ids[] = {
{ .compatible = "marvell,mv64xxx-i2c", },
+   { .compatible = "marvell,mv78230-i2c", },
{ /* sentinel */ }
 };
 
-- 
2.9.3

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[U-Boot] [PATCH 6/7] i2c: mv_i2c.c: Validate read length in I2C command

[Stefan Roese]

From: jinghua 

The I2C bus will get stuck when reading 0 byte. So we add validation of
the read length in i2c_read(). This issue only occurs on read operation.

Signed-off-by: jinghua 
Signed-off-by: Stefan Roese 
Cc: Nadav Haklai 
Cc: Kostya Porotchkin 
Cc: Wilson Ding 
Cc: Victor Gu 
Cc: Hua Jing 
Cc: Terry Zhou 
Cc: Hanna Hawa 
Cc: Haim Boot 
Cc: Heiko Schocher 
---
 drivers/i2c/mv_i2c.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/i2c/mv_i2c.c b/drivers/i2c/mv_i2c.c
index 291b2d7..7f52fa2 100644
--- a/drivers/i2c/mv_i2c.c
+++ b/drivers/i2c/mv_i2c.c
@@ -243,6 +243,11 @@ static int __i2c_read(struct mv_i2c *base, uchar chip, u8 
*addr, int alen,
debug("i2c_read(chip=0x%02x, addr=0x%02x, alen=0x%02x, "
  "len=0x%02x)\n", chip, *addr, alen, len);
 
+   if (len == 0) {
+   printf("reading zero byte is invalid\n");
+   return -EINVAL;
+   }
+
i2c_reset(base);
 
/* dummy chip address write */
-- 
2.9.3

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[U-Boot] [PATCH 5/7] i2c: mv_i2c.c: Enable runtime speed selection (standard vs fast mode)

[Stefan Roese]

This patch adds runtime speed configuration to the mv_i2c driver.
Currently standard (max 100kHz) and fast mode (max 400kHz) are
supported.

Signed-off-by: Stefan Roese 
Cc: Nadav Haklai 
Cc: Kostya Porotchkin 
Cc: Wilson Ding 
Cc: Victor Gu 
Cc: Hua Jing 
Cc: Terry Zhou 
Cc: Hanna Hawa 
Cc: Haim Boot 
Cc: Heiko Schocher 
---
 drivers/i2c/mv_i2c.c | 30 +-
 drivers/i2c/mv_i2c.h | 15 +--
 2 files changed, 38 insertions(+), 7 deletions(-)

diff --git a/drivers/i2c/mv_i2c.c b/drivers/i2c/mv_i2c.c
index 341126a..291b2d7 100644
--- a/drivers/i2c/mv_i2c.c
+++ b/drivers/i2c/mv_i2c.c
@@ -68,6 +68,10 @@ __weak void i2c_clk_enable(void)
  */
 static void i2c_reset(struct mv_i2c *base)
 {
+   u32 icr_mode;
+
+   /* Save bus mode (standard or fast speed) for later use */
+   icr_mode = readl(>icr) & ICR_MODE_MASK;
writel(readl(>icr) & ~ICR_IUE, >icr); /* disable unit */
writel(readl(>icr) | ICR_UR, >icr);   /* reset the unit */
udelay(100);
@@ -76,7 +80,8 @@ static void i2c_reset(struct mv_i2c *base)
i2c_clk_enable();
 
writel(CONFIG_SYS_I2C_SLAVE, >isar); /* set our slave address */
-   writel(I2C_ICR_INIT, >icr); /* set control reg values */
+   /* set control reg values */
+   writel(I2C_ICR_INIT | icr_mode, >icr);
writel(I2C_ISR_INIT, >isr); /* set clear interrupt bits */
writel(readl(>icr) | ICR_IUE, >icr); /* enable unit */
udelay(100);
@@ -416,6 +421,8 @@ unsigned int i2c_get_bus_num(void)
 /* API Functions */
 void i2c_init(int speed, int slaveaddr)
 {
+   u32 val;
+
 #ifdef CONFIG_I2C_MULTI_BUS
current_bus = 0;
base_glob = (struct mv_i2c *)i2c_regs[current_bus];
@@ -423,6 +430,12 @@ void i2c_init(int speed, int slaveaddr)
base_glob = (struct mv_i2c *)CONFIG_MV_I2C_REG;
 #endif
 
+   if (speed > 10)
+   val = ICR_FM;
+   else
+   val = ICR_SM;
+   clrsetbits_le32(_glob->icr, ICR_MODE_MASK, val);
+
i2c_board_init(base_glob);
 }
 
@@ -543,6 +556,20 @@ static int mv_i2c_xfer(struct udevice *bus, struct i2c_msg 
*msg, int nmsgs)
   omsg->len, dmsg->buf, dmsg->len);
 }
 
+static int mv_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
+{
+   struct mv_i2c_priv *priv = dev_get_priv(bus);
+   u32 val;
+
+   if (speed > 10)
+   val = ICR_FM;
+   else
+   val = ICR_SM;
+   clrsetbits_le32(>base->icr, ICR_MODE_MASK, val);
+
+   return 0;
+}
+
 static int mv_i2c_probe(struct udevice *bus)
 {
struct mv_i2c_priv *priv = dev_get_priv(bus);
@@ -554,6 +581,7 @@ static int mv_i2c_probe(struct udevice *bus)
 
 static const struct dm_i2c_ops mv_i2c_ops = {
.xfer   = mv_i2c_xfer,
+   .set_bus_speed  = mv_i2c_set_bus_speed,
 };
 
 static const struct udevice_id mv_i2c_ids[] = {
diff --git a/drivers/i2c/mv_i2c.h b/drivers/i2c/mv_i2c.h
index ae27c44..1e62892 100644
--- a/drivers/i2c/mv_i2c.h
+++ b/drivers/i2c/mv_i2c.h
@@ -23,12 +23,7 @@ extern void i2c_clk_enable(void);
 #define I2C_READ   0
 #define I2C_WRITE  1
 
-#if (CONFIG_SYS_I2C_SPEED == 40)
-#define I2C_ICR_INIT   (ICR_FM | ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD \
-   | ICR_SCLE)
-#else
 #define I2C_ICR_INIT   (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
-#endif
 
 #define I2C_ISR_INIT   0x7FF
 /* - Control register bits  */
@@ -48,7 +43,15 @@ extern void i2c_clk_enable(void);
 #define ICR_ALDIE  0x1000  /* enable arbitration interrupt */
 #define ICR_SADIE  0x2000  /* slave address detected int enable */
 #define ICR_UR 0x4000  /* unit reset */
-#define ICR_FM 0x8000  /* Fast Mode */
+#ifdef CONFIG_ARMADA_3700
+#define ICR_SM 0x0 /* Standard Mode */
+#define ICR_FM 0x1 /* Fast Mode */
+#define ICR_MODE_MASK  0x3 /* Mode mask */
+#else
+#define ICR_SM 0x0 /* Standard Mode */
+#define ICR_FM 0x08000 /* Fast Mode */
+#define ICR_MODE_MASK  0x18000 /* Mode mask */
+#endif
 
 /* - Status register bits - */
 
-- 
2.9.3

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[U-Boot] [PATCH 4/7] i2c: mv_i2c.c: Add DM support

[Stefan Roese]

Signed-off-by: Stefan Roese 
Cc: Nadav Haklai 
Cc: Kostya Porotchkin 
Cc: Wilson Ding 
Cc: Victor Gu 
Cc: Hua Jing 
Cc: Terry Zhou 
Cc: Hanna Hawa 
Cc: Haim Boot 
Cc: Heiko Schocher 
---
 drivers/i2c/mv_i2c.c | 184 +--
 1 file changed, 136 insertions(+), 48 deletions(-)

diff --git a/drivers/i2c/mv_i2c.c b/drivers/i2c/mv_i2c.c
index 30b986e..341126a 100644
--- a/drivers/i2c/mv_i2c.c
+++ b/drivers/i2c/mv_i2c.c
@@ -18,6 +18,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include "mv_i2c.h"
@@ -30,6 +31,16 @@ struct mv_i2c_msg {
u8 data;
 };
 
+#ifdef CONFIG_ARMADA_3700
+/* Armada 3700 has no padding between the registers */
+struct mv_i2c {
+   u32 ibmr;
+   u32 idbr;
+   u32 icr;
+   u32 isr;
+   u32 isar;
+};
+#else
 struct mv_i2c {
u32 ibmr;
u32 pad0;
@@ -41,6 +52,15 @@ struct mv_i2c {
u32 pad3;
u32 isar;
 };
+#endif
+
+/*
+ * Dummy implementation that can be overwritten by a board
+ * specific function
+ */
+__weak void i2c_clk_enable(void)
+{
+}
 
 /*
  * i2c_reset: - reset the host controller
@@ -210,37 +230,13 @@ i2c_transfer_finish:
return ret;
 }
 
-static int __i2c_probe_chip(struct mv_i2c *base, uchar chip)
-{
-   struct mv_i2c_msg msg;
-
-   i2c_reset(base);
-
-   msg.condition = I2C_COND_START;
-   msg.acknack   = I2C_ACKNAK_WAITACK;
-   msg.direction = I2C_WRITE;
-   msg.data  = (chip << 1) + 1;
-   if (i2c_transfer(base, ))
-   return -1;
-
-   msg.condition = I2C_COND_STOP;
-   msg.acknack   = I2C_ACKNAK_SENDNAK;
-   msg.direction = I2C_READ;
-   msg.data  = 0x00;
-   if (i2c_transfer(base, ))
-   return -1;
-
-   return 0;
-}
-
-static int __i2c_read(struct mv_i2c *base, uchar chip, uint addr, int alen,
+static int __i2c_read(struct mv_i2c *base, uchar chip, u8 *addr, int alen,
  uchar *buffer, int len)
 {
struct mv_i2c_msg msg;
-   u8 addr_bytes[3]; /* lowest...highest byte of data address */
 
debug("i2c_read(chip=0x%02x, addr=0x%02x, alen=0x%02x, "
- "len=0x%02x)\n", chip, addr, alen, len);
+ "len=0x%02x)\n", chip, *addr, alen, len);
 
i2c_reset(base);
 
@@ -258,17 +254,13 @@ static int __i2c_read(struct mv_i2c *base, uchar chip, 
uint addr, int alen,
 * send memory address bytes;
 * alen defines how much bytes we have to send.
 */
-   /*addr &= ((1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)-1); */
-   addr_bytes[0] = (u8)((addr >>  0) & 0x00FF);
-   addr_bytes[1] = (u8)((addr >>  8) & 0x00FF);
-   addr_bytes[2] = (u8)((addr >> 16) & 0x00FF);
-
while (--alen >= 0) {
-   debug("i2c_read: send memory word address byte %1d\n", alen);
+   debug("i2c_read: send address byte %02x (alen=%d)\n",
+ *addr, alen);
msg.condition = I2C_COND_NORMAL;
msg.acknack   = I2C_ACKNAK_WAITACK;
msg.direction = I2C_WRITE;
-   msg.data  = addr_bytes[alen];
+   msg.data  = *(addr++);
if (i2c_transfer(base, ))
return -1;
}
@@ -299,8 +291,8 @@ static int __i2c_read(struct mv_i2c *base, uchar chip, uint 
addr, int alen,
return -1;
 
*buffer = msg.data;
-   debug("i2c_read: reading byte (0x%08x)=0x%02x\n",
- (unsigned int)buffer, *buffer);
+   debug("i2c_read: reading byte (%p)=0x%02x\n",
+ buffer, *buffer);
buffer++;
}
 
@@ -309,14 +301,13 @@ static int __i2c_read(struct mv_i2c *base, uchar chip, 
uint addr, int alen,
return 0;
 }
 
-static int __i2c_write(struct mv_i2c *base, uchar chip, uint addr, int alen,
+static int __i2c_write(struct mv_i2c *base, uchar chip, u8 *addr, int alen,
   uchar *buffer, int len)
 {
struct mv_i2c_msg msg;
-   u8 addr_bytes[3]; /* lowest...highest byte of data address */
 
debug("i2c_write(chip=0x%02x, addr=0x%02x, alen=0x%02x, "
- "len=0x%02x)\n", chip, addr, alen, len);
+ "len=0x%02x)\n", chip, *addr, alen, len);
 
i2c_reset(base);
 
@@ -334,24 +325,21 @@ static int __i2c_write(struct mv_i2c *base, uchar chip, 
uint addr, int alen,
 * send memory address bytes;
 * alen defines how much bytes we have to send.
 */
-   addr_bytes[0] = (u8)((addr >>  0) & 0x00FF);
-   addr_bytes[1] = (u8)((addr >>  8) & 0x00FF);
-   addr_bytes[2] = (u8)((addr >> 16) & 0x00FF);
-
while (--alen >= 0) {
-   debug("i2c_write: send memory word address\n");

[U-Boot] [PATCH 1/7] i2c: mv_i2c.c: cosmetic: Coding style cleanups

[Stefan Roese]

Some mostly indentation coding style cleanups. Also, move this driver
to use debug() for debug output.

Signed-off-by: Stefan Roese 
Cc: Nadav Haklai 
Cc: Kostya Porotchkin 
Cc: Wilson Ding 
Cc: Victor Gu 
Cc: Hua Jing 
Cc: Terry Zhou 
Cc: Hanna Hawa 
Cc: Haim Boot 
Cc: Heiko Schocher 
---
 drivers/i2c/mv_i2c.c | 68 ++--
 1 file changed, 34 insertions(+), 34 deletions(-)

diff --git a/drivers/i2c/mv_i2c.c b/drivers/i2c/mv_i2c.c
index fc02e65..0877c51 100644
--- a/drivers/i2c/mv_i2c.c
+++ b/drivers/i2c/mv_i2c.c
@@ -24,12 +24,6 @@
 #include 
 #include "mv_i2c.h"
 
-#ifdef DEBUG_I2C
-#define PRINTD(x) printf x
-#else
-#define PRINTD(x)
-#endif
-
 /* All transfers are described by this data structure */
 struct mv_i2c_msg {
u8 condition;
@@ -234,33 +228,39 @@ int i2c_transfer(struct mv_i2c_msg *msg)
return 0;
 
 transfer_error_msg_empty:
-   PRINTD(("i2c_transfer: error: 'msg' is empty\n"));
-   ret = -1; goto i2c_transfer_finish;
+   debug("i2c_transfer: error: 'msg' is empty\n");
+   ret = -1;
+   goto i2c_transfer_finish;
 
 transfer_error_transmit_timeout:
-   PRINTD(("i2c_transfer: error: transmit timeout\n"));
-   ret = -2; goto i2c_transfer_finish;
+   debug("i2c_transfer: error: transmit timeout\n");
+   ret = -2;
+   goto i2c_transfer_finish;
 
 transfer_error_ack_missing:
-   PRINTD(("i2c_transfer: error: ACK missing\n"));
-   ret = -3; goto i2c_transfer_finish;
+   debug("i2c_transfer: error: ACK missing\n");
+   ret = -3;
+   goto i2c_transfer_finish;
 
 transfer_error_receive_timeout:
-   PRINTD(("i2c_transfer: error: receive timeout\n"));
-   ret = -4; goto i2c_transfer_finish;
+   debug("i2c_transfer: error: receive timeout\n");
+   ret = -4;
+   goto i2c_transfer_finish;
 
 transfer_error_illegal_param:
-   PRINTD(("i2c_transfer: error: illegal parameters\n"));
-   ret = -5; goto i2c_transfer_finish;
+   debug("i2c_transfer: error: illegal parameters\n");
+   ret = -5;
+   goto i2c_transfer_finish;
 
 transfer_error_bus_busy:
-   PRINTD(("i2c_transfer: error: bus is busy\n"));
-   ret = -6; goto i2c_transfer_finish;
+   debug("i2c_transfer: error: bus is busy\n");
+   ret = -6;
+   goto i2c_transfer_finish;
 
 i2c_transfer_finish:
-   PRINTD(("i2c_transfer: ISR: 0x%04x\n", readl(>isr)));
-   i2c_reset();
-   return ret;
+   debug("i2c_transfer: ISR: 0x%04x\n", readl(>isr));
+   i2c_reset();
+   return ret;
 }
 
 /*  */
@@ -325,13 +325,13 @@ int i2c_read(uchar chip, uint addr, int alen, uchar 
*buffer, int len)
struct mv_i2c_msg msg;
u8 addr_bytes[3]; /* lowest...highest byte of data address */
 
-   PRINTD(("i2c_read(chip=0x%02x, addr=0x%02x, alen=0x%02x, "
-   "len=0x%02x)\n", chip, addr, alen, len));
+   debug("i2c_read(chip=0x%02x, addr=0x%02x, alen=0x%02x, "
+ "len=0x%02x)\n", chip, addr, alen, len);
 
i2c_reset();
 
/* dummy chip address write */
-   PRINTD(("i2c_read: dummy chip address write\n"));
+   debug("i2c_read: dummy chip address write\n");
msg.condition = I2C_COND_START;
msg.acknack   = I2C_ACKNAK_WAITACK;
msg.direction = I2C_WRITE;
@@ -350,7 +350,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar 
*buffer, int len)
addr_bytes[2] = (u8)((addr >> 16) & 0x00FF);
 
while (--alen >= 0) {
-   PRINTD(("i2c_read: send memory word address byte %1d\n", alen));
+   debug("i2c_read: send memory word address byte %1d\n", alen);
msg.condition = I2C_COND_NORMAL;
msg.acknack   = I2C_ACKNAK_WAITACK;
msg.direction = I2C_WRITE;
@@ -360,7 +360,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar 
*buffer, int len)
}
 
/* start read sequence */
-   PRINTD(("i2c_read: start read sequence\n"));
+   debug("i2c_read: start read sequence\n");
msg.condition = I2C_COND_START;
msg.acknack   = I2C_ACKNAK_WAITACK;
msg.direction = I2C_WRITE;
@@ -385,8 +385,8 @@ int i2c_read(uchar chip, uint addr, int alen, uchar 
*buffer, int len)
return -1;
 
*buffer = msg.data;
-   PRINTD(("i2c_read: reading byte (0x%08x)=0x%02x\n",
-   (unsigned int)buffer, *buffer));
+   debug("i2c_read: reading byte (0x%08x)=0x%02x\n",
+ (unsigned int)buffer, *buffer);
buffer++;
}
 
@@ -413,13 

[U-Boot] [PATCH 3/7] i2c: mv_i2c.c: Prepare driver for DM conversion

[Stefan Roese]

To prepare for the DM conversion, we add a layer of compatibility
functions to be used by both the legacy and the DM functions.

Signed-off-by: Stefan Roese 
Cc: Nadav Haklai 
Cc: Kostya Porotchkin 
Cc: Wilson Ding 
Cc: Victor Gu 
Cc: Hua Jing 
Cc: Terry Zhou 
Cc: Hanna Hawa 
Cc: Haim Boot 
Cc: Heiko Schocher 
---
 drivers/i2c/mv_i2c.c | 267 +++
 1 file changed, 141 insertions(+), 126 deletions(-)

diff --git a/drivers/i2c/mv_i2c.c b/drivers/i2c/mv_i2c.c
index 36482d5..30b986e 100644
--- a/drivers/i2c/mv_i2c.c
+++ b/drivers/i2c/mv_i2c.c
@@ -18,9 +18,8 @@
  */
 
 #include 
-#include 
-
 #include 
+#include 
 #include "mv_i2c.h"
 
 /* All transfers are described by this data structure */
@@ -43,62 +42,11 @@ struct mv_i2c {
u32 isar;
 };
 
-static struct mv_i2c *base;
-static void i2c_board_init(struct mv_i2c *base)
-{
-#ifdef CONFIG_SYS_I2C_INIT_BOARD
-   u32 icr;
-   /*
-* call board specific i2c bus reset routine before accessing the
-* environment, which might be in a chip on that bus. For details
-* about this problem see doc/I2C_Edge_Conditions.
-*
-* disable I2C controller first, otherwhise it thinks we want to
-* talk to the slave port...
-*/
-   icr = readl(>icr);
-   writel(readl(>icr) & ~(ICR_SCLE | ICR_IUE), >icr);
-
-   i2c_init_board();
-
-   writel(icr, >icr);
-#endif
-}
-
-#ifdef CONFIG_I2C_MULTI_BUS
-static unsigned long i2c_regs[CONFIG_MV_I2C_NUM] = CONFIG_MV_I2C_REG;
-static unsigned int bus_initialized[CONFIG_MV_I2C_NUM];
-static unsigned int current_bus;
-
-int i2c_set_bus_num(unsigned int bus)
-{
-   if ((bus < 0) || (bus >= CONFIG_MV_I2C_NUM)) {
-   printf("Bad bus: %d\n", bus);
-   return -1;
-   }
-
-   base = (struct mv_i2c *)i2c_regs[bus];
-   current_bus = bus;
-
-   if (!bus_initialized[current_bus]) {
-   i2c_board_init(base);
-   bus_initialized[current_bus] = 1;
-   }
-
-   return 0;
-}
-
-unsigned int i2c_get_bus_num(void)
-{
-   return current_bus;
-}
-#endif
-
 /*
  * i2c_reset: - reset the host controller
  *
  */
-static void i2c_reset(void)
+static void i2c_reset(struct mv_i2c *base)
 {
writel(readl(>icr) & ~ICR_IUE, >icr); /* disable unit */
writel(readl(>icr) | ICR_UR, >icr);   /* reset the unit */
@@ -120,7 +68,7 @@ static void i2c_reset(void)
  *
  * @return: 1 in case of success, 0 means timeout (no match within 10 ms).
  */
-static int i2c_isr_set_cleared(unsigned long set_mask,
+static int i2c_isr_set_cleared(struct mv_i2c *base, unsigned long set_mask,
   unsigned long cleared_mask)
 {
int timeout = 1000, isr;
@@ -150,7 +98,7 @@ static int i2c_isr_set_cleared(unsigned long set_mask,
  *  -5: illegal parameters
  *  -6: bus is busy and couldn't be aquired
  */
-int i2c_transfer(struct mv_i2c_msg *msg)
+static int i2c_transfer(struct mv_i2c *base, struct mv_i2c_msg *msg)
 {
int ret;
 
@@ -160,7 +108,7 @@ int i2c_transfer(struct mv_i2c_msg *msg)
switch (msg->direction) {
case I2C_WRITE:
/* check if bus is not busy */
-   if (!i2c_isr_set_cleared(0, ISR_IBB))
+   if (!i2c_isr_set_cleared(base, 0, ISR_IBB))
goto transfer_error_bus_busy;
 
/* start transmission */
@@ -179,7 +127,7 @@ int i2c_transfer(struct mv_i2c_msg *msg)
writel(readl(>icr) | ICR_TB, >icr);
 
/* transmit register empty? */
-   if (!i2c_isr_set_cleared(ISR_ITE, 0))
+   if (!i2c_isr_set_cleared(base, ISR_ITE, 0))
goto transfer_error_transmit_timeout;
 
/* clear 'transmit empty' state */
@@ -187,14 +135,14 @@ int i2c_transfer(struct mv_i2c_msg *msg)
 
/* wait for ACK from slave */
if (msg->acknack == I2C_ACKNAK_WAITACK)
-   if (!i2c_isr_set_cleared(0, ISR_ACKNAK))
+   if (!i2c_isr_set_cleared(base, 0, ISR_ACKNAK))
goto transfer_error_ack_missing;
break;
 
case I2C_READ:
 
/* check if bus is not busy */
-   if (!i2c_isr_set_cleared(0, ISR_IBB))
+   if (!i2c_isr_set_cleared(base, 0, ISR_IBB))
goto transfer_error_bus_busy;
 
/* start receive */
@@ -212,7 +160,7 @@ int i2c_transfer(struct mv_i2c_msg *msg)
writel(readl(>icr) | ICR_TB, >icr);
 
/* receive register full? */
-   if (!i2c_isr_set_cleared(ISR_IRF, 0))
+   if (!i2c_isr_set_cleared(base, ISR_IRF, 0))
goto 

[U-Boot] [PATCH 2/7] i2c: mv_i2c.c: Remove CONFIG_HARD_I2C

[Stefan Roese]

CONFIG_HARD_I2C is not needed, lets remove it.

Signed-off-by: Stefan Roese 
Cc: Nadav Haklai 
Cc: Kostya Porotchkin 
Cc: Wilson Ding 
Cc: Victor Gu 
Cc: Hua Jing 
Cc: Terry Zhou 
Cc: Hanna Hawa 
Cc: Haim Boot 
Cc: Heiko Schocher 
---
 drivers/i2c/mv_i2c.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/i2c/mv_i2c.c b/drivers/i2c/mv_i2c.c
index 0877c51..36482d5 100644
--- a/drivers/i2c/mv_i2c.c
+++ b/drivers/i2c/mv_i2c.c
@@ -20,7 +20,6 @@
 #include 
 #include 
 
-#ifdef CONFIG_HARD_I2C
 #include 
 #include "mv_i2c.h"
 
@@ -468,4 +467,3 @@ int i2c_write(uchar chip, uint addr, int alen, uchar 
*buffer, int len)
 
return 0;
 }
-#endif /* CONFIG_HARD_I2C */
-- 
2.9.3

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