Re: [U-Boot] [PATCH v2 8/9] arm64: rk3399: add SPL support
Hi Simon, On 02/23/2017 12:16 PM, Simon Glass wrote: Hi Kever, On 13 February 2017 at 02:39, Kever Yang wrote: Add SPL support for rk3399, default with of-platdata enabled. Signed-off-by: Kever Yang --- Changes in v2: - split SPL patch into 4 patches Changes in v1: None arch/arm/Kconfig | 1 + arch/arm/mach-rockchip/Kconfig| 2 + arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk3399-board-spl.c | 158 ++ include/configs/rk3399_common.h | 6 ++ 5 files changed, 168 insertions(+) create mode 100644 arch/arm/mach-rockchip/rk3399-board-spl.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d871a45..9a0efe4 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -882,6 +882,7 @@ config ARCH_ROCKCHIP select DM select SPL_DM if SPL select SYS_MALLOC_F + select SPL_SEPARATE_BSS if SPL Unfortunately this line seems to break firefly-rk3288, for example. Can you perhaps move it to RK3399 only? Yes, I can move it to RK3399, can I send v4 patch only for this one, because the patch is too big. Thanks, - Kever Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 5/7] rockchip: rk3328: add sysreset driver
Add rk3328 sysreset driver.
Signed-off-by: William Zhang
Signed-off-by: Kever Yang
Acked-by: Simon Glass
---
Changes in v3: None
Changes in v2:
- fix include header file order
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_rk3328.c | 45 ++
2 files changed, 46 insertions(+)
create mode 100644 drivers/sysreset/sysreset_rk3328.c
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index 37638a8..12cfa79 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -10,6 +10,7 @@ ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_ROCKCHIP_RK3036) += sysreset_rk3036.o
endif
obj-$(CONFIG_ROCKCHIP_RK3288) += sysreset_rk3288.o
+obj-$(CONFIG_ROCKCHIP_RK3328) += sysreset_rk3328.o
obj-$(CONFIG_ROCKCHIP_RK3399) += sysreset_rk3399.o
obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
obj-$(CONFIG_ARCH_SNAPDRAGON) += sysreset_snapdragon.o
diff --git a/drivers/sysreset/sysreset_rk3328.c
b/drivers/sysreset/sysreset_rk3328.c
new file mode 100644
index 000..7b9af09
--- /dev/null
+++ b/drivers/sysreset/sysreset_rk3328.c
@@ -0,0 +1,45 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+int rk3328_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+ struct rk3328_cru *cru = rockchip_get_cru();
+
+ if (IS_ERR(cru))
+ return PTR_ERR(cru);
+ switch (type) {
+ case SYSRESET_WARM:
+ writel(0xeca8, &cru->glb_srst_snd_value);
+ break;
+ case SYSRESET_COLD:
+ writel(0xfdb9, &cru->glb_srst_fst_value);
+ break;
+ default:
+ return -EPROTONOSUPPORT;
+ }
+
+ return -EINPROGRESS;
+}
+
+static struct sysreset_ops rk3328_sysreset = {
+ .request= rk3328_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_rk3328) = {
+ .name = "rk3328_sysreset",
+ .id = UCLASS_SYSRESET,
+ .ops= &rk3328_sysreset,
+};
--
1.9.1
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[U-Boot] [PATCH v3 7/7] rockchip: rk3288: add defconfig for evb-rk3328
Enable board config for evb-rk3328. SDcard and eMMC boot is OK in this initial version, USB and EMAC function is not available now, will comes later. Signed-off-by: William Zhang Signed-off-by: Kever Yang Acked-by: Simon Glass --- Changes in v3: None Changes in v2: None configs/evb-rk3328_defconfig | 36 1 file changed, 36 insertions(+) create mode 100644 configs/evb-rk3328_defconfig diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig new file mode 100644 index 000..df22105 --- /dev/null +++ b/configs/evb-rk3328_defconfig @@ -0,0 +1,36 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_ROCKCHIP_RK3328=y +CONFIG_DEFAULT_DEVICE_TREE="rk3328-evb" +CONFIG_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_ROCKCHIP_RK3328_PINCTRL=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_RAM=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0xFF13 +CONFIG_DEBUG_UART_CLOCK=2400 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_SYSRESET=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_ERRNO_STR=y -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 3/7] rockchip: rk3328: add clock driver
Add rk3328 clock driver and cru structure definition.
Signed-off-by: William Zhang
Signed-off-by: Kever Yang
---
Changes in v3:
- remove I2C reg value MACRO definition
Changes in v2:
- split rockchip_get_cru into arch/arm/mach-rockchip
- fix include header file order
- drop MACRO for I2C reg access
- use OSC_HZ for 24*1024*1024
arch/arm/include/asm/arch-rockchip/cru_rk3328.h | 70 +++
arch/arm/mach-rockchip/rk3328/Makefile | 1 +
arch/arm/mach-rockchip/rk3328/clk_rk3328.c | 31 ++
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk_rk3328.c | 581
5 files changed, 684 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3328.h
create mode 100644 arch/arm/mach-rockchip/rk3328/clk_rk3328.c
create mode 100644 drivers/clk/rockchip/clk_rk3328.c
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h
b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h
new file mode 100644
index 000..948706e
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CRU_RK3328_H_
+#define __ASM_ARCH_CRU_RK3328_H_
+
+#include
+
+struct rk3328_clk_priv {
+ struct rk3328_cru *cru;
+ ulong rate;
+};
+
+struct rk3328_cru {
+ u32 apll_con[5];
+ u32 reserved1[3];
+ u32 dpll_con[5];
+ u32 reserved2[3];
+ u32 cpll_con[5];
+ u32 reserved3[3];
+ u32 gpll_con[5];
+ u32 reserved4[3];
+ u32 mode_con;
+ u32 misc;
+ u32 reserved5[2];
+ u32 glb_cnt_th;
+ u32 glb_rst_st;
+ u32 glb_srst_snd_value;
+ u32 glb_srst_fst_value;
+ u32 npll_con[5];
+ u32 reserved6[(0x100 - 0xb4) / 4];
+ u32 clksel_con[53];
+ u32 reserved7[(0x200 - 0x1d4) / 4];
+ u32 clkgate_con[29];
+ u32 reserved8[3];
+ u32 ssgtbl[32];
+ u32 softrst_con[12];
+ u32 reserved9[(0x380 - 0x330) / 4];
+ u32 sdmmc_con[2];
+ u32 sdio_con[2];
+ u32 emmc_con[2];
+ u32 sdmmc_ext_con[2];
+};
+check_member(rk3328_cru, sdmmc_ext_con[1], 0x39c);
+#define MHz100
+#define KHz1000
+#define OSC_HZ (24 * MHz)
+#define APLL_HZ(600 * MHz)
+#define GPLL_HZ(576 * MHz)
+#define CPLL_HZ(594 * MHz)
+
+#define CLK_CORE_HZ(600 * MHz)
+#define ACLKM_CORE_HZ (300 * MHz)
+#define PCLK_DBG_HZ(300 * MHz)
+
+#define PERIHP_ACLK_HZ (144000 * KHz)
+#define PERIHP_HCLK_HZ (72000 * KHz)
+#define PERIHP_PCLK_HZ (72000 * KHz)
+
+#define PWM_CLOCK_HZ(74 * MHz)
+
+enum apll_frequencies {
+ APLL_816_MHZ,
+ APLL_600_MHZ,
+};
+
+#endif /* __ASM_ARCH_CRU_RK3328_H_ */
diff --git a/arch/arm/mach-rockchip/rk3328/Makefile
b/arch/arm/mach-rockchip/rk3328/Makefile
index 8ecf8ee..bbab036 100644
--- a/arch/arm/mach-rockchip/rk3328/Makefile
+++ b/arch/arm/mach-rockchip/rk3328/Makefile
@@ -4,5 +4,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
+obj-y += clk_rk3328.o
obj-y += rk3328.o
obj-y += syscon_rk3328.o
diff --git a/arch/arm/mach-rockchip/rk3328/clk_rk3328.c
b/arch/arm/mach-rockchip/rk3328/clk_rk3328.c
new file mode 100644
index 000..1205516
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3328/clk_rk3328.c
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include
+#include
+#include
+#include
+
+int rockchip_get_clk(struct udevice **devp)
+{
+ return uclass_get_device_by_driver(UCLASS_CLK,
+ DM_GET_DRIVER(rockchip_rk3328_cru), devp);
+}
+
+void *rockchip_get_cru(void)
+{
+ struct rk3328_clk_priv *priv;
+ struct udevice *dev;
+ int ret;
+
+ ret = rockchip_get_clk(&dev);
+ if (ret)
+ return ERR_PTR(ret);
+
+ priv = dev_get_addr_ptr(dev);
+
+ return priv->cru;
+}
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 1f8e417..c4e81e9 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -6,4 +6,5 @@
obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
+obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o
diff --git a/drivers/clk/rockchip/clk_rk3328.c
b/drivers/clk/rockchip/clk_rk3328.c
new file mode 100644
index 000..0ff1e30
--- /dev/null
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -0,0 +1,581 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct pll_div {
+ u32 refdiv;
+ u32 fbdiv;
+ u32 postdiv1;
+ u32 postdiv2;
+ u32 frac;
+};
[U-Boot] [PATCH v3 1/7] rockchip: rk3328: add device tree file
Add dts binding header for rk3328, files origin from kernel.
Signed-off-by: William Zhang
Signed-off-by: Kever Yang
Acked-by: Simon Glass
---
Changes in v3:
- Moved new binding #defines into this patch to avoid build error
Changes in v2: None
arch/arm/dts/Makefile |1 +
arch/arm/dts/rk3328-evb.dts| 45 +
arch/arm/dts/rk3328.dtsi | 1477
include/dt-bindings/clock/rk3328-cru.h | 394 +
include/dt-bindings/pinctrl/rockchip.h |2 +
5 files changed, 1919 insertions(+)
create mode 100644 arch/arm/dts/rk3328-evb.dts
create mode 100644 arch/arm/dts/rk3328.dtsi
create mode 100644 include/dt-bindings/clock/rk3328-cru.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index eb68c20..1a6659c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -38,6 +38,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-fennec.dtb \
rk3288-tinker.dtb \
rk3288-popmetal.dtb \
+ rk3328-evb.dtb \
rk3399-evb.dtb
dtb-$(CONFIG_ARCH_MESON) += \
meson-gxbb-odroidc2.dtb
diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts
new file mode 100644
index 000..01794ed
--- /dev/null
+++ b/arch/arm/dts/rk3328-evb.dts
@@ -0,0 +1,45 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "rk3328.dtsi"
+
+/ {
+ model = "Rockchip RK3328 EVB";
+ compatible = "rockchip,rk3328-evb", "rockchip,rk3328";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ card-detect-delay = <200>;
+ disable-wp;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>,
<&sdmmc0_bus4>;
+ status = "okay";
+};
+
+&emmc {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ supports-emmc;
+ disable-wp;
+ non-removable;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi
new file mode 100644
index 000..8a98ee3
--- /dev/null
+++ b/arch/arm/dts/rk3328.dtsi
@@ -0,0 +1,1477 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+/ {
+ compatible = "rockchip,rk3328";
+
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+// clocks = <&cru ARMCLK>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ };
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ };
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ };
+ };
+
+ cpu0_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@40800 {
+ opp-hz = /bits/ 64 <40800>;
+ opp-microvolt = <95>;
+ clock-latency-ns = <4>;
+ opp-suspend;
+ };
+ opp@6 {
+ opp-hz = /bits/ 64 <6>;
+ opp-microvolt = <95>;
+ clock-latency-ns = <4>;
+ };
+ opp@81600 {
+ opp-hz = /bits/ 64 <81600>;
+ opp-microvolt = <100>;
+ clock-latency-ns = <4>;
+ };
+
[U-Boot] [PATCH v3 6/7] rockchip: rk3328: add evb-rk3328 support
evb-rk3328 is an evb from Rockchip based on rk3328 SoC: - 2 USB2.0 Host port; - 1 USB3.0 Host port; - 1 HDMI port; - 2 10/100M eth port; - 2GB ddr; - 16GB eMMC; - UART to USB debug port; Signed-off-by: William Zhang Signed-off-by: Kever Yang Acked-by: Simon Glass --- Changes in v3: - Moved changes to arch/arm/mach-rockchip/rk3328/Kconfig into this patch Changes in v2: - README file fix arch/arm/mach-rockchip/rk3328/Kconfig | 23 +++ board/rockchip/evb_rk3328/Kconfig | 15 board/rockchip/evb_rk3328/MAINTAINERS | 6 +++ board/rockchip/evb_rk3328/Makefile | 7 board/rockchip/evb_rk3328/README | 70 ++ board/rockchip/evb_rk3328/evb-rk3328.c | 40 +++ include/configs/evb_rk3328.h | 26 + 7 files changed, 187 insertions(+) create mode 100644 arch/arm/mach-rockchip/rk3328/Kconfig create mode 100644 board/rockchip/evb_rk3328/Kconfig create mode 100644 board/rockchip/evb_rk3328/MAINTAINERS create mode 100644 board/rockchip/evb_rk3328/Makefile create mode 100644 board/rockchip/evb_rk3328/README create mode 100644 board/rockchip/evb_rk3328/evb-rk3328.c create mode 100644 include/configs/evb_rk3328.h diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig b/arch/arm/mach-rockchip/rk3328/Kconfig new file mode 100644 index 000..43afba2 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3328/Kconfig @@ -0,0 +1,23 @@ +if ROCKCHIP_RK3328 + +choice + prompt "RK3328 board select" + +config TARGET_EVB_RK3328 + bool "RK3328 evaluation board" + help + RK3328evb is a evaluation board for Rockchip rk3328, + with full function and phisical connectors support like + usb2.0 host ports, LVDS, JTAG, MAC, SDcard, HDMI, USB-2-serial... + +endchoice + +config SYS_SOC + default "rockchip" + +config SYS_MALLOC_F_LEN + default 0x0800 + +source "board/rockchip/evb_rk3328/Kconfig" + +endif diff --git a/board/rockchip/evb_rk3328/Kconfig b/board/rockchip/evb_rk3328/Kconfig new file mode 100644 index 000..ef446b4 --- /dev/null +++ b/board/rockchip/evb_rk3328/Kconfig @@ -0,0 +1,15 @@ +if TARGET_EVB_RK3328 + +config SYS_BOARD + default "evb_rk3328" + +config SYS_VENDOR + default "rockchip" + +config SYS_CONFIG_NAME + default "evb_rk3328" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS new file mode 100644 index 000..9db604f --- /dev/null +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -0,0 +1,6 @@ +EVB-RK3328 +M: William Zhang +S: Maintained +F: board/rockchip/evb_rk3328 +F: include/configs/evb_rk3328.h +F: configs/evb-rk3328_defconfig diff --git a/board/rockchip/evb_rk3328/Makefile b/board/rockchip/evb_rk3328/Makefile new file mode 100644 index 000..81c5de8 --- /dev/null +++ b/board/rockchip/evb_rk3328/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2016 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += evb-rk3328.o diff --git a/board/rockchip/evb_rk3328/README b/board/rockchip/evb_rk3328/README new file mode 100644 index 000..6cbb66a --- /dev/null +++ b/board/rockchip/evb_rk3328/README @@ -0,0 +1,70 @@ +Introduction + + +RK3328 key features we might use in U-Boot: +* CPU: ARMv8 64bit quad-core Cortex-A53 +* IRAM: 36KB +* DRAM: 4GB-16MB dual-channel +* eMMC: support eMMC 5.0/5.1, suport HS400, HS200, DDR50 +* SD/MMC: support SD 3.0, MMC 4.51 +* USB: USB2.0 EHCI host port *2 +* Display: RGB/HDMI/DP/MIPI/EDP + +evb key features: +* regulator: pwm regulator for CPU B/L +* PMIC: rk808 +* debug console: UART2 + +In order to support Arm Trust Firmware(ATF), we need to use the +miniloader from rockchip which: +* do DRAM init +* load and verify ATF image +* load and verify U-Boot image + +Here is the step-by-step to boot to U-Boot on rk3328. + +Get the Source and prebuild binary +== + + > mkdir ~/evb_rk3328 + > cd ~/evb_rk3328 + > git clone https://github.com/ARM-software/arm-trusted-firmware.git + > git clone https://github.com/rockchip-linux/rkbin + > git clone https://github.com/rockchip-linux/rkflashtool + +Compile ATF +=== + + > cd arm-trusted-firmware + > make realclean + > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3328 bl31 + +Compile U-Boot +== + + > cd ../u-boot + > make CROSS_COMPILE=aarch64-linux-gnu- evb-rk3328_defconfig all + +Compile rkflashtool +=== + + > cd ../rkflashtool + > make + +Package image for miniloader + + > cd .. + > cp arm-trusted-firmware/build/rk3328/release/bl31.bin rkbin/rk33 + > ./rkbin/tools/trust_merger rkbin/tools/RK3328TRUST.ini + > ./rkbin/tools/loaderimage --pack --uboot u-boot/u-boot-dtb.bin uboot.img + > mkdir image + > mv trust.img ./image/ + > mv uboot.img ./image/rk3328evb-uboot.bin + +Fla
[U-Boot] [PATCH v3 2/7] rockchip: rk3328: add soc basic support
RK3328 is a SoC from Rockchip with quad-core Cortex-A53 CPU.
It supports two USB2.0 EHCI ports. Other interfaces are very
much like RK3288, the DRAM are 32bit width address and support
address from 0 to 4GB-16MB range.
Signed-off-by: William Zhang
Signed-off-by: Kever Yang
Acked-by: Simon Glass
---
Changes in v3:
- Removed contents of rk3328/Kconfig to avoid build error
Changes in v2: None
arch/arm/mach-rockchip/Kconfig| 11 +
arch/arm/mach-rockchip/Makefile | 1 +
arch/arm/mach-rockchip/rk3328/Makefile| 8
arch/arm/mach-rockchip/rk3328/rk3328.c| 39
arch/arm/mach-rockchip/rk3328/syscon_rk3328.c | 20 +
include/configs/rk3328_common.h | 65 +++
6 files changed, 144 insertions(+)
create mode 100644 arch/arm/mach-rockchip/rk3328/Makefile
create mode 100644 arch/arm/mach-rockchip/rk3328/rk3328.c
create mode 100644 arch/arm/mach-rockchip/rk3328/syscon_rk3328.c
create mode 100644 include/configs/rk3328_common.h
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 5c4a4c2..9c01971 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -23,6 +23,16 @@ config ROCKCHIP_RK3288
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
+config ROCKCHIP_RK3328
+ bool "Support Rockchip RK3328"
+ select ARM64
+ help
+ The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
+ including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
+ video interfaces supporting HDMI and eDP, several DDR3 options
+ and video codec support. Peripherals include Gigabit Ethernet,
+ USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
+
config ROCKCHIP_RK3399
bool "Support Rockchip RK3399"
select ARM64
@@ -47,5 +57,6 @@ config SPL_MMC_SUPPORT
source "arch/arm/mach-rockchip/rk3036/Kconfig"
source "arch/arm/mach-rockchip/rk3288/Kconfig"
+source "arch/arm/mach-rockchip/rk3328/Kconfig"
source "arch/arm/mach-rockchip/rk3399/Kconfig"
endif
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 6e79fed..49d90b9 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -17,4 +17,5 @@ obj-y += rk_timer.o
endif
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
+obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
diff --git a/arch/arm/mach-rockchip/rk3328/Makefile
b/arch/arm/mach-rockchip/rk3328/Makefile
new file mode 100644
index 000..8ecf8ee
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3328/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2016 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += rk3328.o
+obj-y += syscon_rk3328.o
diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c
b/arch/arm/mach-rockchip/rk3328/rk3328.c
new file mode 100644
index 000..857f014
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3328/rk3328.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+
+static struct mm_region rk3328_mem_map[] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0x8000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xf000UL,
+ .phys = 0xf000UL,
+ .size = 0x1000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+PTE_BLOCK_NON_SHARE |
+PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = rk3328_mem_map;
+
+int arch_cpu_init(void)
+{
+ /* We do some SoC one time setting here. */
+
+ return 0;
+}
diff --git a/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c
b/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c
new file mode 100644
index 000..a1a368f
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c
@@ -0,0 +1,20 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+
+static const struct udevice_id rk3328_syscon_ids[] = {
+ { .compatible = "rockchip,rk3328-grf", .data = ROCKCHIP_SYSCON_GRF },
+};
+
+U_BOOT_DRIVER(syscon_rk3328) = {
+ .name = "rk3328_syscon",
+ .id = UCLASS_SYSCON,
+ .of_match = rk3328_syscon_ids,
+};
diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h
new file mode 100644
index 000..eacf716
--- /dev/null
+++ b/include/configs/rk3328_common.h
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyrig
[U-Boot] [PATCH v3 4/7] rockchip: rk3328: add pinctrl driver
Add rk3328 pinctrl driver and grf/iomux structure definition.
Signed-off-by: William Zhang
Signed-off-by: Kever Yang
Acked-by: Simon Glass
---
Changes in v3: None
Changes in v2:
- fix include header file order
- add space around operators in header file
arch/arm/include/asm/arch-rockchip/grf_rk3328.h | 134
drivers/pinctrl/Kconfig | 9 +
drivers/pinctrl/rockchip/Makefile | 1 +
drivers/pinctrl/rockchip/pinctrl_rk3328.c | 419
4 files changed, 563 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3328.h
create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3328.c
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
new file mode 100644
index 000..2776cef
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
@@ -0,0 +1,134 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __SOC_ROCKCHIP_RK3328_GRF_H__
+#define __SOC_ROCKCHIP_RK3328_GRF_H__
+
+struct rk3328_grf_regs {
+ u32 gpio0a_iomux;
+ u32 gpio0b_iomux;
+ u32 gpio0c_iomux;
+ u32 gpio0d_iomux;
+ u32 gpio1a_iomux;
+ u32 gpio1b_iomux;
+ u32 gpio1c_iomux;
+ u32 gpio1d_iomux;
+ u32 gpio2a_iomux;
+ u32 gpio2bl_iomux;
+ u32 gpio2bh_iomux;
+ u32 gpio2cl_iomux;
+ u32 gpio2ch_iomux;
+ u32 gpio2d_iomux;
+ u32 gpio3al_iomux;
+ u32 gpio3ah_iomux;
+ u32 gpio3bl_iomux;
+ u32 gpio3bh_iomux;
+ u32 gpio3c_iomux;
+ u32 gpio3d_iomux;
+ u32 com_iomux;
+ u32 reserved1[(0x100 - 0x54) / 4];
+
+ u32 gpio0a_p;
+ u32 gpio0b_p;
+ u32 gpio0c_p;
+ u32 gpio0d_p;
+ u32 gpio1a_p;
+ u32 gpio1b_p;
+ u32 gpio1c_p;
+ u32 gpio1d_p;
+ u32 gpio2a_p;
+ u32 gpio2b_p;
+ u32 gpio2c_p;
+ u32 gpio2d_p;
+ u32 gpio3a_p;
+ u32 gpio3b_p;
+ u32 gpio3c_p;
+ u32 gpio3d_p;
+ u32 reserved2[(0x200 - 0x140) / 4];
+ u32 gpio0a_e;
+ u32 gpio0b_e;
+ u32 gpio0c_e;
+ u32 gpio0d_e;
+ u32 gpio1a_e;
+ u32 gpio1b_e;
+ u32 gpio1c_e;
+ u32 gpio1d_e;
+ u32 gpio2a_e;
+ u32 gpio2b_e;
+ u32 gpio2c_e;
+ u32 gpio2d_e;
+ u32 gpio3a_e;
+ u32 gpio3b_e;
+ u32 gpio3c_e;
+ u32 gpio3d_e;
+ u32 reserved3[(0x300 - 0x240) / 4];
+ u32 gpio0l_sr;
+ u32 gpio0h_sr;
+ u32 gpio1l_sr;
+ u32 gpio1h_sr;
+ u32 gpio2l_sr;
+ u32 gpio2h_sr;
+ u32 gpio3l_sr;
+ u32 gpio3h_sr;
+ u32 reserved4[(0x380 - 0x320) / 4];
+ u32 gpio0l_smt;
+ u32 gpio0h_smt;
+ u32 gpio1l_smt;
+ u32 gpio1h_smt;
+ u32 gpio2l_smt;
+ u32 gpio2h_smt;
+ u32 gpio3l_smt;
+ u32 gpio3h_smt;
+ u32 reserved5[(0x400 - 0x3a0) / 4];
+ u32 soc_con[11];
+ u32 reserved6[(0x480 - 0x42c) / 4];
+ u32 soc_status[5];
+ u32 reserved7[(0x4c0 - 0x494) / 4];
+ u32 otg3_con[2];
+ u32 reserved8[(0x500 - 0x4c8) / 4];
+ u32 cpu_con[2];
+ u32 reserved9[(0x520 - 0x508) / 4];
+ u32 cpu_status[2];
+ u32 reserved10[(0x5c8 - 0x528) / 4];
+ u32 os_reg[8];
+ u32 reserved11[(0x680 - 0x5e8) / 4];
+ u32 sig_detect_con;
+ u32 reserved12[3];
+ u32 sig_detect_status;
+ u32 reserved13[3];
+ u32 sig_detect_status_clr;
+ u32 reserved14[3];
+
+ u32 sdmmc_det_counter;
+ u32 reserved15[(0x700 - 0x6b4) / 4];
+ u32 host0_con[3];
+ u32 reserved16[(0x880 - 0x70c) / 4];
+ u32 otg_con0;
+ u32 reserved17[3];
+ u32 host0_status;
+ u32 reserved18[(0x900 - 0x894) / 4];
+ u32 mac_con[3];
+ u32 reserved19[(0xb00 - 0x90c) / 4];
+ u32 macphy_con[4];
+ u32 macphy_status;
+};
+check_member(rk3328_grf_regs, macphy_status, 0xb10);
+
+struct rk3328_sgrf_regs {
+ u32 soc_con[6];
+ u32 reserved0[(0x100 - 0x18) / 4];
+ u32 dmac_con[6];
+ u32 reserved1[(0x180 - 0x118) / 4];
+ u32 fast_boot_addr;
+ u32 reserved2[(0x200 - 0x184) / 4];
+ u32 chip_fuse_con;
+ u32 reserved3[(0x280 - 0x204) / 4];
+ u32 hdcp_key_reg[8];
+ u32 hdcp_key_access_mask;
+};
+check_member(rk3328_sgrf_regs, hdcp_key_access_mask, 0x2a0);
+
+#endif /* __SOC_ROCKCHIP_RK3328_GRF_H__ */
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index efcb4c0..16e2a17 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -148,6 +148,15 @@ config PINCTRL_AT91PIO4
This option is to enable the AT91 pinctrl driver for AT91 PIO4
controller which is available on SAMA5D2 SoC.
+config ROCKCHIP_RK3328_PINCTRL
+ bool "Rockchip pin control driver"
+ depends on DM
+ help
+ Support pin multiplexing contro
Re: [U-Boot] [PATCH] rockchip: video: fix mpixelclock in rockchip HDMI
Hi Simon,
在 2017年02月23日 11:52, Simon Glass 写道:
Hi,
On 11 January 2017 at 22:08, Simon Glass wrote:
On 28 December 2016 at 23:01, Nickey Yang wrote:
Correct mpixelclock errors in rockchip_phy_config[] and rockchip_mpll_cfg[].
Signed-off-by: Nickey Yang
---
drivers/video/rockchip/rk_hdmi.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
Applied to u-boot-rockchip, thanks!
I only just noticed, but this patch breaks HDMI output on firefly. Can
you please take a look? What does this patch actually fix?
Regards,
Simon
You can add
printf("---YYS mpll.cpce = %x \n",rockchip_mpll_cfg[i].cpce);
printf("---YYS mpll.gmp = %x \n",rockchip_mpll_cfg[i].gmp);
printf("---YYS mpll.curr = %x \n",rockchip_mpll_cfg[i].curr);
in hdmi_phy_configure(rk_hdmi.c line 409), all of those value will be
0 without this patch.
We want to get those different value by near clock settings between
rockchip_mpll_cfg[] in fact.
by the way,HDMI output on firefly will work well when reset this patch?
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Re: [U-Boot] saveenv not working with CONFIG_ENV_IS_IN_UBI
Hello Richard, Am 20.02.2017 um 22:38 schrieb Richard Cagley: I am unable to have my uboot environment variable persist when using saveenv. I have these configs set #define MTDIDS_DEFAULT "nand0=xilinx_nand" #define MTDPARTS_DEFAULT \ "mtdparts=xilinx_nand:" \ "8M(boot)ro," \ "16M(env-boot)," \ "20M(itb)," \ "-(root)" #define CONFIG_ENV_IS_IN_UBI #define CONFIG_ENV_UBI_PART "env-boot" #define CONFIG_ENV_UBI_VOLUME "u-boot-env1" #define CONFIG_ENV_UBI_VOLUME_REDUND "u-boot-env2" Once in u-boot I do something along these lines: mtdparts default nand erase.part env-boot ubi part env-boot ubi create u-boot-env1 0x2 dynamic ubi create u-boot-env2 0x2 dynamic setenv foo 1 saveenv saveenv reset printenv foo ## Error: "foo" not defined Can you provide some more informations? On which hw? Is the board support for your hw in mainline? Does UBI support work at all on your hw? Please provide a full log, may with ubi debug enabled. Thanks! bye, Heiko thanks ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] rockchip: firefly: configs: add a new config to keep non-of-platdata
Hi Simon, 2017-02-22 11:59 GMT+08:00 Simon Glass : > Hi Jacob, > > On 20 February 2017 at 03:26, Jacob Chen wrote: >> The firefly config have been changed to use SPL_BACK_TO_BROM, but we also >> want keep >> CONFIG_SPL_OF_PLATDATA as an example. >> >> So add this separate defconfig to show how both way works. >> >> Signed-off-by: Jacob Chen >> --- >> >> configs/firefly-nodtb-rk3288_defconfig | 78 >> ++ >> 1 file changed, 78 insertions(+) >> create mode 100644 configs/firefly-nodtb-rk3288_defconfig > > Thanks for this - can you also please add a MAINTAINERS file? > > Regards, > Simon > ___ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot Could i just append a line to "board/firefly/firefly-rk3288/MAINTAINERS"? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] rockchip: configs: Enable networking support on rk3288 boards
At current, only firefly and rock2 have network enabled. Let's enable other boards. Signed-off-by: Jacob Chen --- configs/evb-rk3288_defconfig | 5 - configs/fennec-rk3288_defconfig | 5 - configs/miniarm-rk3288_defconfig | 4 configs/popmetal-rk3288_defconfig | 4 4 files changed, 16 insertions(+), 2 deletions(-) diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index df58996..1b516de 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -45,8 +45,11 @@ CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_NETDEVICES=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y -# CONFIG_PINCTRL_FULL is not set CONFIG_SPL_PINCTRL=y # CONFIG_SPL_PINCTRL_FULL is not set CONFIG_ROCKCHIP_RK3288_PINCTRL=y diff --git a/configs/fennec-rk3288_defconfig b/configs/fennec-rk3288_defconfig index 21a5df7..5471970 100644 --- a/configs/fennec-rk3288_defconfig +++ b/configs/fennec-rk3288_defconfig @@ -44,8 +44,11 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_NETDEVICES=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y -# CONFIG_PINCTRL_FULL is not set CONFIG_SPL_PINCTRL=y # CONFIG_SPL_PINCTRL_FULL is not set CONFIG_ROCKCHIP_RK3288_PINCTRL=y diff --git a/configs/miniarm-rk3288_defconfig b/configs/miniarm-rk3288_defconfig index 2b6bd0b..8b86ae5 100644 --- a/configs/miniarm-rk3288_defconfig +++ b/configs/miniarm-rk3288_defconfig @@ -44,6 +44,10 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_NETDEVICES=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y # CONFIG_SPL_PINCTRL_FULL is not set diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig index c4bf33a..c25b60a 100644 --- a/configs/popmetal-rk3288_defconfig +++ b/configs/popmetal-rk3288_defconfig @@ -44,6 +44,10 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_NETDEVICES=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y # CONFIG_SPL_PINCTRL_FULL is not set -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] ARM: dts: rockchip: enable gmac for rk3288 boards
Enable gmac interface for rk3288 board dts.
use "okay" not "ok"
Signed-off-by: Jacob Chen
---
arch/arm/dts/rk3288-evb.dtsi | 22 ++
arch/arm/dts/rk3288-miniarm.dtsi | 2 +-
arch/arm/dts/rk3288-popmetal.dtsi | 2 +-
3 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/rk3288-evb.dtsi b/arch/arm/dts/rk3288-evb.dtsi
index cb7d03e..4960f33 100644
--- a/arch/arm/dts/rk3288-evb.dtsi
+++ b/arch/arm/dts/rk3288-evb.dtsi
@@ -11,6 +11,13 @@
reg = <0 0x8000>;
};
+ ext_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12500>;
+ clock-output-names = "ext_gmac";
+ };
+
keys: gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
@@ -98,6 +105,21 @@
status = "okay";
};
+&gmac {
+ phy-mode = "rgmii";
+ clock_in_out = "input";
+ snps,reset-gpio = <&gpio4 7 0>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 1 100>;
+ assigned-clocks = <&cru SCLK_MAC>;
+ assigned-clock-parents = <&ext_gmac>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ tx_delay = <0x30>;
+ rx_delay = <0x10>;
+ status = "okay";
+};
+
&hdmi {
ddc-i2c-bus = <&i2c5>;
status = "okay";
diff --git a/arch/arm/dts/rk3288-miniarm.dtsi b/arch/arm/dts/rk3288-miniarm.dtsi
index ceb4e2b..527493c 100644
--- a/arch/arm/dts/rk3288-miniarm.dtsi
+++ b/arch/arm/dts/rk3288-miniarm.dtsi
@@ -149,7 +149,7 @@
pinctrl-0 = <&rgmii_pins>;
tx_delay = <0x30>;
rx_delay = <0x10>;
- status = "ok";
+ status = "okay";
};
&hdmi {
diff --git a/arch/arm/dts/rk3288-popmetal.dtsi
b/arch/arm/dts/rk3288-popmetal.dtsi
index e5be4cb..dd6ce8b 100644
--- a/arch/arm/dts/rk3288-popmetal.dtsi
+++ b/arch/arm/dts/rk3288-popmetal.dtsi
@@ -203,7 +203,7 @@
pinctrl-0 = <&rgmii_pins>;
tx_delay = <0x30>;
rx_delay = <0x10>;
- status = "ok";
+ status = "okay";
};
&hdmi {
--
1.9.1
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Re: [U-Boot] Complete verified uboot example
On Wed, 22 Feb 2017 10:51:22 -0800
Rick Altherr wrote:
> On Tue, Feb 21, 2017 at 10:08 AM, Ron Brash
> wrote:
>
> > Hello all,
> >
> > I am adding verified kernel support on a board we are using and I am
> > struggling to fully understand all of the concepts and steps
> > required to pull everything together (on ARM, using ZImages and
> > booting with a working DTB on 4.4.3x). I also looked at the test
> > script inside of examples, but it left me with more questions than
> > understanding.
> >
> > Please correct me where appropriate in my understanding, but if I am
> > confused, likely others are too and I hope this helps everyone
> > involved overall.
> >
>
> You've asked some really good questions. Hopefully this discussion
> will end up with patches to clarify the docs.
>
>
> >
> > Steps:
> > ---
> >
> > First, u-boot needs to have the appropriate features enabled and to
> > be built using them. At a minimum, I suspect:
> >
> > CONFIG_RSA=y
> > CONFIG_FIT=y
> > CONFIG_FIT_SIGNATURE=y
> > CONFIG_OF_CONTROL=y
> >
> >
> Yup. That looks right.
>
>
> > Next, we need to derive the appropriate cryptographic
> > primitives/keys.
> >
> > #Generate a private signing key (RSA2048):
> > openssl genrsa -F4 -out \
> > "${key_dir}"/"${key_name}".key 2048
> >
> > # Generate a public key:
> > openssl req -batch -new -x509 \
> > -key "${key_dir}"/"${key_name}".key \
> > -out "${key_dir}"/"${key_name}".crt
> >
> >
> So far so good. In general, I suggest having multiple signing keys.
> You can put all the public keys in your u-boot so an image signed
> with any of those keys will be accepted. If you happen to have a
> signing key compromised, you can switch to one of the other ones.
> With that other key, you can sign an update the removes the
> compromised public key from future images.
>
>
> > Then we derive the ITS or image source file - a file that
> > hints/describes the elements that will be verified and/or inside of
> > the FIT image? Lets call this $FIT_ITS
> >
> > FIT is a container format. Generally, you'll create a FIT that
> > contains
> the zImage, dtb, initramfs, etc. With FIT support enabled in u-boot,
> you only need to provide the single FIT image address to 'bootm'.
> u-boot will use the config section to find the individual elements,
> load them into RAM as needed, and boot.
>
>
> > / dts - v1 /;
> > / {
> > description = "Configuration to load a Xen Kernel";
> > #address-cells = <1>;
> > images {
> > linux_kernel @ 1 {
> > description = "Linux zImage";
> > data = /incbin / ("pathToImage/zImage");
> > type = "kernel";
> > arch = "arm";
> > os = "linux";
> > compression = "none";
> > load = <0xaf60 >;
> > entry = <0xaf60 >;
> > hash @ 1 {
> > algo = "sha1";
> > };
> > };
> > fdt @ 1 {
> > description = "FDT blob";
> > data = /incbin / ("PathToDTBUsedByBootingKernel/ex.dtb");
> > type = "flat_dt";
> > arch = "arm";
> > compression = "none";
> > load = <0xaec0 >;
> >
>
> You generally don't need a 'load' property for the FDT or an
> initramfs. Without one, U-Boot will allocate RAM dynamically, if
> needed, and pass the relocated address to the kernel.
>
> hash @ 1 {
> > algo = "sha1";
> > };
> > };
> > };
> > configurations {
> > default = "config@1";
> > config @ 1 {
> > description = "Plain Linux";
> > kernel = "linux_kernel@1";
> > fdt = "fdt@1";
> > loadables = "linux_kernel@1";
> >
>
> 'loadables' is for other types of firmware. You only need the
> 'kernel' property for loading and booting the kernel.
>
>
> > };
> > };
> > };
> >
> > Question: Does a signature section go into this as well? underneath
> > the hash node for each value?
>
>
> > signature@1 {
> > algo = "sha1,rsa2048";
> > value = <...kernel signature 1...>
> > };
> >
>
> You add a signature section to each image you want signed within the
> FIT. In your case, add one for both the kernel and FDT images.
> Signatures go _next_ to the hash section, not in it. Omit the
> 'value' property as it will be generated for you later.
>
>
> >
> > Then using the device-tree-compiler (dtc), I create a DTB for
> > u-boot. This is the control FDT and this defines what keys are
> > used etc..
> >
>
> The control FDT is used for U-Boot's driver model _as well as_
> providing public keys for verifying images. Your board may not
> currently use a control FDT in which case you create one from scratch.
>
>
> >
> > #Assemble control FDT for U-Boot with space for public key:
> > $DTC -p 0x1000 u-boot.dts -O dtb -o u-boot.dtb
> >
> > Question: What is required inside of the u-boot.dts for u-boot? Is
> > it simply the same .dts used by the booting kernel, but with a
> > section proclaiming the keys?
> >
>
> This depends on the board you are using. For example, an AST2500
> requires a DTB for U-Boot to load the right drivers. The DTB used by
> U-Boot is slightly different from that used by Linux as the Linux DTB
> often includes addition con
Re: [U-Boot] [PATCH v2 8/9] arm64: rk3399: add SPL support
Hi Kever, On 13 February 2017 at 02:39, Kever Yang wrote: > Add SPL support for rk3399, default with of-platdata enabled. > > Signed-off-by: Kever Yang > --- > > Changes in v2: > - split SPL patch into 4 patches > > Changes in v1: None > > arch/arm/Kconfig | 1 + > arch/arm/mach-rockchip/Kconfig| 2 + > arch/arm/mach-rockchip/Makefile | 1 + > arch/arm/mach-rockchip/rk3399-board-spl.c | 158 > ++ > include/configs/rk3399_common.h | 6 ++ > 5 files changed, 168 insertions(+) > create mode 100644 arch/arm/mach-rockchip/rk3399-board-spl.c > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index d871a45..9a0efe4 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -882,6 +882,7 @@ config ARCH_ROCKCHIP > select DM > select SPL_DM if SPL > select SYS_MALLOC_F > + select SPL_SEPARATE_BSS if SPL Unfortunately this line seems to break firefly-rk3288, for example. Can you perhaps move it to RK3399 only? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 00/20] rk3188 uboot support
Am Mittwoch, 22. Februar 2017, 20:26:18 CET schrieb Simon Glass: > Hi Heiko, > > On 18 February 2017 at 11:46, Heiko Stuebner wrote: > > Hi, > > > > thanks to Kever finding the needle in the haystack (wrong resets > > in sdram driver actually resetting the sdmmc controller) the rk3188 > > can now actually load uboot into memory from spl ... yay . > > > > So this v4 does hopefully addresses all last review comments from > > Simon and includes of course the newly received tags so far. > > > > > > Heiko > > > > Heiko Stuebner (21): > > dm: allow limiting pre-reloc markings to spl or tpl > > clk: rk3288: limit gpll and cpll init to SPL build > > rockchip: rk3288: sdram: use constants in ddrconf table > > rockchip: rk3288: sdram: style fixes from rk3188 sdram review > > rockchip: Move bootrom helper compilation to a hidden option > > rockchip: Move bootrom-related declarations to a header > > rockchip: mkimage: Allow encoding of loader code in spl images > > rockchip: mkimage: Add support rk3188 serial > > rockchip: serial: Adapt rockchip of-platdata driver for rk3188 > > rockchip: rk3188: Add header files for PMU and GRF > > rockchip: rk3188: Add pinctrl driver > > rockchip: rk3188: Add sysreset driver > > rockchip: rk3188: Add rk3066/rk3188 clock bindings > > rockchip: rk3188: Add clock driver > > rockchip: rk3188: Add core devicetree files > > rockchip: rk3188: Add core support > > rockchip: rk3188: Add sdram driver > > rockchip: rk3188: Add main, spl and tpl boards > > rockchip: rk3188: Add Radxa Rock board > > rockchip: rk3188: add README.rockchip paragraph describing sd boot > > Add a temporary script that can create a bootimage for rk3188 > > > > arch/arm/dts/Makefile | 1 + > > arch/arm/dts/rk3188-radxarock.dts | 382 + > > arch/arm/dts/rk3188.dtsi| 601 ++ > > arch/arm/dts/rk3xxx.dtsi| 417 ++ > > arch/arm/include/asm/arch-rockchip/bootrom.h| 22 + > > arch/arm/include/asm/arch-rockchip/cru_rk3188.h | 191 + > > arch/arm/include/asm/arch-rockchip/ddr_rk3188.h | 25 + > > arch/arm/include/asm/arch-rockchip/ddr_rk3288.h | 8 + > > arch/arm/include/asm/arch-rockchip/grf_rk3188.h | 589 ++ > > arch/arm/include/asm/arch-rockchip/pmu_rk3188.h | 36 + > > arch/arm/mach-rockchip/Kconfig | 20 + > > arch/arm/mach-rockchip/Makefile | 14 +- > > arch/arm/mach-rockchip/rk3036-board-spl.c | 3 +- > > arch/arm/mach-rockchip/rk3188-board-spl.c | 218 ++ > > arch/arm/mach-rockchip/rk3188-board-tpl.c | 86 ++ > > arch/arm/mach-rockchip/rk3188-board.c | 71 ++ > > arch/arm/mach-rockchip/rk3188/Kconfig | 35 + > > arch/arm/mach-rockchip/rk3188/Makefile | 11 + > > arch/arm/mach-rockchip/rk3188/clk_rk3188.c | 33 + > > arch/arm/mach-rockchip/rk3188/sdram_rk3188.c| 995 > > arch/arm/mach-rockchip/rk3188/syscon_rk3188.c > > | 55 ++ > > arch/arm/mach-rockchip/rk3288-board-spl.c | 3 +- > > arch/arm/mach-rockchip/rk3288/sdram_rk3288.c| 59 +- > > board/radxa/rock/Kconfig| 15 + > > board/radxa/rock/MAINTAINERS| 6 + > > board/radxa/rock/Makefile | 7 + > > board/radxa/rock/rock.c | 7 + > > configs/rock_defconfig | 56 ++ > > doc/README.rockchip | 26 + > > doc/driver-model/README.txt | 4 + > > drivers/clk/at91/pmc.c | 3 +- > > drivers/clk/rockchip/Makefile | 1 + > > drivers/clk/rockchip/clk_rk3188.c | 527 + > > drivers/clk/rockchip/clk_rk3288.c | 2 + > > drivers/core/root.c | 2 +- > > drivers/core/util.c | 25 + > > drivers/pinctrl/Kconfig | 9 + > > drivers/pinctrl/pinctrl-uclass.c| 3 +- > > drivers/pinctrl/rockchip/Makefile | 1 + > > drivers/pinctrl/rockchip/pinctrl_rk3188.c | 611 +++ > > drivers/serial/serial_rockchip.c| 19 +- > > drivers/sysreset/Makefile | 1 + > > drivers/sysreset/sysreset_rk3188.c | 47 ++ > > include/configs/rk3188_common.h | 125 +++ > > include/configs/rock.h | 30 + > > include/dm/util.h | 26 + > > include/dt-bindings/clock/rk3066a-cru.h | 32 + > > include/dt-bindings/clock/rk3188-cru-common.h | 256 ++ > > include/dt-bindings/clock/rk3188-cru.h | 48 ++ > > mkuboot | 35 + > > scripts/Makefile.spl| 7 +- > > tools/dtoc/dtoc.py
Re: [U-Boot] [PATCH v2 1/6] sunxi: add pinctrl (UCLASS_PINCTRL) support for sunxi
On Thu, Feb 23, 2017 at 7:18 AM, Maxime Ripard
wrote:
> On Wed, Feb 22, 2017 at 09:47:27PM +0100, Philipp Tomsich wrote:
>> This change adds a full device-model pinctrl driver for sunxi (tested with
>> sun50iw1p1) based on the support available in Linux.
>>
>> Details are:
>> * implements a driver for pinctrl devices and assigns sun50i-a64-pinctrl
>>and sun50i-a64-r-pinctrl to it
>> * dynamically creates the driver_data for a sunxi_gpio (see sunxi_gpio.c)
>>driver and binds it to the same device-tree node
>> * lifts and reuses the pinctrl-sunxi.h and pinctrl-sun50i-a64.c files from
>>Linux (thanks to Maxime and Andre) and adds a pinctrl-sun50i-a64-r.c (to
>>be picked up for inclusion into Linux again)
>>
>> Signed-off-by: Philipp Tomsich
>> ---
>> arch/arm/include/asm/arch-sunxi/gpio-internal.h| 19 +
>> .../pinctrl/allwinner,pinctrl.txt | 65 +++
>> drivers/gpio/sunxi_gpio.c | 15 +-
>> drivers/pinctrl/Kconfig| 10 +
>> drivers/pinctrl/Makefile | 2 +
>> drivers/pinctrl/sunxi/Makefile | 10 +
>> drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c | 92
>> drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c | 577
>> +
>> drivers/pinctrl/sunxi/pinctrl-sunxi.c | 317 +++
>> drivers/pinctrl/sunxi/pinctrl-sunxi.h | 311 +++
>> 10 files changed, 1411 insertions(+), 7 deletions(-)
>> create mode 100644 arch/arm/include/asm/arch-sunxi/gpio-internal.h
>> create mode 100644 doc/device-tree-bindings/pinctrl/allwinner,pinctrl.txt
>> create mode 100644 drivers/pinctrl/sunxi/Makefile
>> create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
>> create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c
>> create mode 100644 drivers/pinctrl/sunxi/pinctrl-sunxi.c
>> create mode 100644 drivers/pinctrl/sunxi/pinctrl-sunxi.h
>>
>> diff --git a/arch/arm/include/asm/arch-sunxi/gpio-internal.h
>> b/arch/arm/include/asm/arch-sunxi/gpio-internal.h
>> new file mode 100644
>> index 000..4dcdd34
>> --- /dev/null
>> +++ b/arch/arm/include/asm/arch-sunxi/gpio-internal.h
>> @@ -0,0 +1,19 @@
>> +/*
>> + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +
>> +#ifndef _SUNXI_GPIO_INTERNAL_H
>> +#define _SUNXI_GPIO_INTERNAL_H
>> +
>> +/* This data structure is shared between the sunxi_gpio driver and
>> + * the sunxi_pinctrl driver.
>> + */
>> +struct sunxi_gpio_soc_data {
>> + int start;
>> + int no_banks;
>> +};
>> +
>> +#endif
>> diff --git a/doc/device-tree-bindings/pinctrl/allwinner,pinctrl.txt
>> b/doc/device-tree-bindings/pinctrl/allwinner,pinctrl.txt
>> new file mode 100644
>> index 000..946831f
>> --- /dev/null
>> +++ b/doc/device-tree-bindings/pinctrl/allwinner,pinctrl.txt
>> @@ -0,0 +1,65 @@
>> +* Allwinner Pinmux Controller
>> +
>> +Allwinner integrates multiple banks (of 32 pins each) of pin-muxing,
>> +GPIO functionality and (optional) external interrupt functionality
>> +into a single controller.
>> +
>> +For each configurable pad (certain driver-cells, such as the IO from
>> +integrated USB PHYs or DRAM, have a fixed function and can not be
>> +configured), the muxing options (input, output or one of the several
>> +functions) can be selected.
>> +
>> +Properties for the pinctrl node:
>> + - compatible: should be "allwinner,sun50i-pinctrl"
>
> There's a typo here, the compatible is sun50i-a64-pinctrl
>
>> + - reg: address and length of the register set for the device.
>> + - interrupts: interrupt for the device
>> + - clocks: A phandle to the reference clock for this device
>
> (and ideally, this would take three clocks: the bus gate + the two
> oscillators).
>
>> +
>> +Properties for the pinconfig sub-nodes:
>> + - allwinner,pins: a list of pins (e.g. "PH2", "PH3") to configure
>> + - allwinner,function: the name of pinmux function (e.g. "mmc2")
>
> allwinner,pins and allwinner,function are also deprecated in favour of
> pins and function.
>
>> + - drive-strength: a drive-stength setting of 10, 20, 30 or 40 mA
>> + - bias-pull-up
>> + - bias-pull-down
>> + - bias-disable (default)
>
> The default is not bias-disable, but to keep the current configuration
Shouldn't we just copy the binding docs from the Linux kernel?
Afterall they are supposed to be the same.
ChenYu
>> +
>> +Deprecated properties for the pinconfig sub-nodes:
>> + - allwinner,drive: one of , ,
>> + or
>> + - allwinner,pull: one of ,
>> +or
>> +
>> +Example:
>> +
>> + pio: pinctrl@1c20800 {
>> + compatible = "allwinner,sun50i-a64-pinctrl";
>> + reg = <0x01c20800 0x400>;
>> +
>> + interrupts = ,
>> + ,
>> + ;
>> + clocks = <&bus_gates 69>;
>> +
>> + gpio-controller;
>> +
Re: [U-Boot] [PATCH] rockchip: video: fix mpixelclock in rockchip HDMI
Hi, On 11 January 2017 at 22:08, Simon Glass wrote: > On 28 December 2016 at 23:01, Nickey Yang wrote: >> Correct mpixelclock errors in rockchip_phy_config[] and rockchip_mpll_cfg[]. >> >> Signed-off-by: Nickey Yang >> --- >> drivers/video/rockchip/rk_hdmi.c | 20 ++-- >> 1 file changed, 10 insertions(+), 10 deletions(-) > > Applied to u-boot-rockchip, thanks! I only just noticed, but this patch breaks HDMI output on firefly. Can you please take a look? What does this patch actually fix? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V3 12/19] i2c: lpi2c: add lpi2c driver for i.MX7ULP
Hello Peng, Am 22.02.2017 um 09:21 schrieb Peng Fan: Add lpi2c driver for i.MX7ULP. Need to enable the two options to use this driver: CONFIG_DM_I2C=y CONFIG_SYS_LPI2C_IMX=y Signed-off-by: Peng Fan Cc: Stefano Babic Cc: Heiko Schocher --- V3: none V2: none arch/arm/include/asm/arch-mx7ulp/imx_lpi2c.h | 520 +++ drivers/i2c/Kconfig | 6 + drivers/i2c/Makefile | 1 + drivers/i2c/imx_lpi2c.c | 462 4 files changed, 989 insertions(+) create mode 100644 arch/arm/include/asm/arch-mx7ulp/imx_lpi2c.h create mode 100644 drivers/i2c/imx_lpi2c.c just a nitpick ... [...] diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 39f62da..0bee0c4 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -109,6 +109,12 @@ config SYS_I2C_INTEL the I2C API meaning that any I2C operations will immediately fail for now. +config SYS_LPI2C_IMX + bool "NXP i.MX LPI2C driver" + depends on ARCH_MX7ULP + help + Add support for the NXP i.MX LPI2C driver. + config SYS_I2C_MXC bool "NXP i.MX I2C driver" depends on MX6 diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 7c86198..2cbe3bc 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o +obj-$(CONFIG_SYS_LPI2C_IMX) += imx_lpi2c.o All I2C config symbls have an "I2C" ... and you name the driver imx_lpi2c, but the config symbol lpi2c_imx ... can you please rename it to CONFIG_SYS_I2C_IMX_LPI2C and sort the list alphabetical? (heh... with the rename it is on the correct place ;-) Thanks! Beside of this, you can add my: Acked-by: Heiko Schocher bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] rockchip: firefly: configs: remove config_spl_of_platdata
On 20 February 2017 at 03:28, Jacob Chen wrote: > Hi, > > 2017-02-17 4:44 GMT+08:00 Simon Glass : >> Hi, >> >> On 14 February 2017 at 23:41, Jacob Chen wrote: >>> Hi Kever, >>> >>> >>> Kever Yang wrote on 2017年02月15日 14:13: Hi Jacob, On 02/15/2017 11:06 AM, Jacob Chen wrote: > > We should remove config_spl_of_platdata to build u-boot-spl-dtb.bin > rather than u-boot-spl-nodtb.bin > since we use spl_back_to_brom. Have you try with CONFIG_SPL_OF_PLATDATA on and without SPL_BACK_TO_BROM? If this works on firefly, then we can still leave it as an example to show how both way works. >>> >>> Firefly had been using CONFIG_SPL_OF_PLATDATA and it works well. >>> Just it will make trouble for other things to generate the u-boot blob, >>> like yocto, sdk build scripts, guides... >>> >>> At first, I also want to keep CONFIG_SPL_OF_PLATDATA in firefly, but later >>> I find that i have to do a lot of unnecessary work to deal with it, >>> so now I would like one chip use one way to generate the u-boot blob. >> >> How about having a separate board config like firefly-rk3288-dt so >> that we keep the non-of-platdata alive? It only needs a separate >> defconfig, which is pretty esay. >> >> Regards, >> Simon >> ___ >> U-Boot mailing list >> U-Boot@lists.denx.de >> http://lists.denx.de/mailman/listinfo/u-boot > > > I send a patch "rockchip: firefly: configs: add a new config to keep > non-of-platdata" to save old config. OK thanks. Acked-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 3/7] rockchip: rk3288: add clock driver
Hi Kever, On 22 February 2017 at 03:13, Kever Yang wrote: > Add rk3328 clock driver and cru structure definition. > > Signed-off-by: William Zhang > Signed-off-by: Kever Yang > --- > > Changes in v2: > - split rockchip_get_cru into arch/arm/mach-rockchip > - fix include header file order > - drop MACRO for I2C reg access It looks like they are still here. > - use OSC_HZ for 24*1024*1024 > > arch/arm/include/asm/arch-rockchip/cru_rk3328.h | 70 +++ > arch/arm/mach-rockchip/rk3328/Makefile | 1 + > arch/arm/mach-rockchip/rk3328/clk_rk3328.c | 31 ++ > drivers/clk/rockchip/Makefile | 1 + > drivers/clk/rockchip/clk_rk3328.c | 597 > > 5 files changed, 700 insertions(+) > create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3328.h > create mode 100644 arch/arm/mach-rockchip/rk3328/clk_rk3328.c > create mode 100644 drivers/clk/rockchip/clk_rk3328.c > [..] > diff --git a/drivers/clk/rockchip/clk_rk3328.c > b/drivers/clk/rockchip/clk_rk3328.c > new file mode 100644 > index 000..4428a80 > --- /dev/null > +++ b/drivers/clk/rockchip/clk_rk3328.c > @@ -0,0 +1,597 @@ > +/* > + * (C) Copyright 2017 Rockchip Electronics Co., Ltd > + * > + * SPDX-License-Identifier:GPL-2.0 > + */ > + [..] > +#define I2C_CLK_REG_MASK(bus) \ > + (CLK_I2C_DIV_CON_MASK << \ > + CLK_I2C ##bus## _DIV_CON_SHIFT | \ > + CLK_I2C_PLL_SEL_MASK << \ > + CLK_I2C ##bus## _PLL_SEL_SHIFT) > + > +#define I2C_CLK_REG_VALUE(bus, clk_div) \ > +((clk_div - 1) << \ > +CLK_I2C ##bus## _DIV_CON_SHIFT | \ > +CLK_I2C_PLL_SEL_GPLL << \ > +CLK_I2C ##bus## _PLL_SEL_SHIFT) > + > +#define I2C_CLK_DIV_VALUE(con, bus) \ > +(con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \ > +CLK_I2C_DIV_CON_MASK; See above. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/4] arm64: rk3399: add ddr controller driver
On 22 February 2017 at 01:56, Kever Yang wrote: > RK3399 support DDR3, LPDDR3, DDR4 sdram, this patch is porting from > coreboot, support 4GB lpddr3 in this version. > > Signed-off-by: Kever Yang > --- > > Changes in v3: > - enable driver without of-platdata > - add binding file for sdram driver > - some fix base on Simon's comment. > > Changes in v2: > - use lower-case hex for input dts data > - using rk3288 like style to encode/decode sys_reg > - gather some parameters as base params in rk3399_sdram_params > - add some missing comment > > Changes in v1: > - use dts for parameter > - get all controller base address from dts instead of hard code > - gather all controller into dram_info instead of separate global > variables. > - add return value for error case > > arch/arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi | 1536 > > arch/arm/include/asm/arch-rockchip/sdram_rk3399.h | 119 ++ > arch/arm/mach-rockchip/rk3399/Makefile |1 + > arch/arm/mach-rockchip/rk3399/rk3399.c |1 + > arch/arm/mach-rockchip/rk3399/sdram_rk3399.c | 1321 + > .../clock/rockchip,rk3399-dmc.txt | 42 + > 6 files changed, 3020 insertions(+) > create mode 100644 arch/arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi > create mode 100644 arch/arm/include/asm/arch-rockchip/sdram_rk3399.h > create mode 100644 arch/arm/mach-rockchip/rk3399/sdram_rk3399.c > create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3399-dmc.txt Acked-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] rockchip: set scan_dev_for_boot_part env for rockchip SoC
Hi Eddie,
On 22 February 2017 at 07:12, Eddie Cai wrote:
> Hi Simon
>
> 2017-02-22 17:05 GMT+08:00 Eddie Cai :
>>
>> Hi Simon
>>
>> 2017-02-22 11:59 GMT+08:00 Simon Glass :
>>>
>>> Hi Eddie,
>>>
>>> On 17 February 2017 at 00:57, Eddie Cai
>>> wrote:
>>> > Auto write GPT table if fail to get GPT table when
>>> > scan_dev_for_boot_part
>>> >
>>> > Signed-off-by: Eddie Cai
>>> > ---
>>> > arch/arm/mach-rockchip/rk3036-board.c | 20 ++-
>>> > arch/arm/mach-rockchip/rk3288-board.c | 20 ++-
>>> > arch/arm/mach-rockchip/rk3399-board.c | 46
>>> > +++
>>> > 3 files changed, 84 insertions(+), 2 deletions(-)
>>> > create mode 100644 arch/arm/mach-rockchip/rk3399-board.c
>>> >
>>> > diff --git a/arch/arm/mach-rockchip/rk3036-board.c
>>> > b/arch/arm/mach-rockchip/rk3036-board.c
>>> > index bf2b268..e9aeaff 100644
>>> > --- a/arch/arm/mach-rockchip/rk3036-board.c
>>> > +++ b/arch/arm/mach-rockchip/rk3036-board.c
>>> > @@ -51,7 +51,25 @@ __weak int rk_board_late_init(void)
>>> > int board_late_init(void)
>>> > {
>>> > setup_boot_mode();
>>> > -
>>> > + setenv("scan_dev_for_boot_part",
>>> > + "part list ${devtype} ${devnum} -bootable test;
>>> > "
>>> > + "if env exists test; then "
>>> > + "echo Found valid partition table; "
>>> > + "else "
>>> > + "echo No valid partition table, write the
>>> > original partition table; "
>>> > + "gpt write ${devtype} ${devnum}
>>> > ${partitions}; "
>>> > + "mmc rescan;"
>>> > + "fi;"
>>> > + "part list ${devtype} ${devnum} -bootable
>>> > devplist; "
>>> > + "env exists devplist || setenv devplist 1; "
>>> > + "for distro_bootpart in ${devplist}; do "
>>> > + "if fstype ${devtype} "
>>> > + "${devnum}:${distro_bootpart} "
>>> > + "bootfstype; then "
>>> > + "run scan_dev_for_boot; "
>>> > + "fi; "
>>> > + "done\0"
>>> > + );
>>> > return rk_board_late_init();
>>> > }
>>> >
>>> > diff --git a/arch/arm/mach-rockchip/rk3288-board.c
>>> > b/arch/arm/mach-rockchip/rk3288-board.c
>>> > index 9894a25..386b155 100644
>>> > --- a/arch/arm/mach-rockchip/rk3288-board.c
>>> > +++ b/arch/arm/mach-rockchip/rk3288-board.c
>>> > @@ -74,7 +74,25 @@ int board_late_init(void)
>>> > {
>>> > setup_boot_mode();
>>> > rk3288_qos_init();
>>> > -
>>> > + setenv("scan_dev_for_boot_part",
>>> > + "part list ${devtype} ${devnum} -bootable test;
>>> > "
>>> > + "if env exists test; then "
>>> > + "echo Found valid partition table; "
>>> > + "else "
>>> > + "echo No valid partition table, write the
>>> > original partition table; "
>>> > + "gpt write ${devtype} ${devnum}
>>> > ${partitions}; "
>>> > + "mmc rescan;"
>>> > + "fi;"
>>> > + "part list ${devtype} ${devnum} -bootable
>>> > devplist; "
>>> > + "env exists devplist || setenv devplist 1; "
>>> > + "for distro_bootpart in ${devplist}; do "
>>> > + "if fstype ${devtype} "
>>> > + "${devnum}:${distro_bootpart} "
>>> > + "bootfstype; then "
>>> > + "run scan_dev_for_boot; "
>>> > + "fi; "
>>> > + "done\0"
>>> > + );
>>> > return rk_board_late_init();
>>> > }
>>> >
>>> > diff --git a/arch/arm/mach-rockchip/rk3399-board.c
>>> > b/arch/arm/mach-rockchip/rk3399-board.c
>>> > new file mode 100644
>>> > index 000..3777643
>>> > --- /dev/null
>>> > +++ b/arch/arm/mach-rockchip/rk3399-board.c
>>> > @@ -0,0 +1,46 @@
>>> > +/*
>>> > + * (C) Copyright 2017 ockchip Electronics Co., Ltd
>>> > + *
>>> > + * SPDX-License-Identifier: GPL-2.0+
>>> > + */
>>> > +
>>> > +#include
>>> > +#include
>>> > +#include
>>> > +#include
>>> > +#include
>>> > +#include
>>> > +#include
>>> > +#include
>>> > +
>>> > +DECLARE_GLOBAL_DATA_PTR;
>>> > +
>>> > +__weak int rk_board_late_init(void)
>>> > +{
>>> > + return 0;
>>> > +}
>>> > +
>>> > +int board_late_init(void)
>>> > +{
>>> > + setenv("scan_dev_for_boot_part",
>>> > + "part list ${devtype} ${devnum} -bootable test;
>>> > "
>>> > + "if env exists test; then "
>>> > + "echo Found valid partition table; "
>>> > + "else "
>>> > +
Re: [U-Boot] [PATCH v4 00/20] rk3188 uboot support
Hi Heiko, On 18 February 2017 at 11:46, Heiko Stuebner wrote: > Hi, > > thanks to Kever finding the needle in the haystack (wrong resets > in sdram driver actually resetting the sdmmc controller) the rk3188 > can now actually load uboot into memory from spl ... yay . > > So this v4 does hopefully addresses all last review comments from > Simon and includes of course the newly received tags so far. > > > Heiko > > > Heiko Stuebner (21): > dm: allow limiting pre-reloc markings to spl or tpl > clk: rk3288: limit gpll and cpll init to SPL build > rockchip: rk3288: sdram: use constants in ddrconf table > rockchip: rk3288: sdram: style fixes from rk3188 sdram review > rockchip: Move bootrom helper compilation to a hidden option > rockchip: Move bootrom-related declarations to a header > rockchip: mkimage: Allow encoding of loader code in spl images > rockchip: mkimage: Add support rk3188 serial > rockchip: serial: Adapt rockchip of-platdata driver for rk3188 > rockchip: rk3188: Add header files for PMU and GRF > rockchip: rk3188: Add pinctrl driver > rockchip: rk3188: Add sysreset driver > rockchip: rk3188: Add rk3066/rk3188 clock bindings > rockchip: rk3188: Add clock driver > rockchip: rk3188: Add core devicetree files > rockchip: rk3188: Add core support > rockchip: rk3188: Add sdram driver > rockchip: rk3188: Add main, spl and tpl boards > rockchip: rk3188: Add Radxa Rock board > rockchip: rk3188: add README.rockchip paragraph describing sd boot > Add a temporary script that can create a bootimage for rk3188 > > arch/arm/dts/Makefile | 1 + > arch/arm/dts/rk3188-radxarock.dts | 382 + > arch/arm/dts/rk3188.dtsi| 601 ++ > arch/arm/dts/rk3xxx.dtsi| 417 ++ > arch/arm/include/asm/arch-rockchip/bootrom.h| 22 + > arch/arm/include/asm/arch-rockchip/cru_rk3188.h | 191 + > arch/arm/include/asm/arch-rockchip/ddr_rk3188.h | 25 + > arch/arm/include/asm/arch-rockchip/ddr_rk3288.h | 8 + > arch/arm/include/asm/arch-rockchip/grf_rk3188.h | 589 ++ > arch/arm/include/asm/arch-rockchip/pmu_rk3188.h | 36 + > arch/arm/mach-rockchip/Kconfig | 20 + > arch/arm/mach-rockchip/Makefile | 14 +- > arch/arm/mach-rockchip/rk3036-board-spl.c | 3 +- > arch/arm/mach-rockchip/rk3188-board-spl.c | 218 ++ > arch/arm/mach-rockchip/rk3188-board-tpl.c | 86 ++ > arch/arm/mach-rockchip/rk3188-board.c | 71 ++ > arch/arm/mach-rockchip/rk3188/Kconfig | 35 + > arch/arm/mach-rockchip/rk3188/Makefile | 11 + > arch/arm/mach-rockchip/rk3188/clk_rk3188.c | 33 + > arch/arm/mach-rockchip/rk3188/sdram_rk3188.c| 995 > > arch/arm/mach-rockchip/rk3188/syscon_rk3188.c | 55 ++ > arch/arm/mach-rockchip/rk3288-board-spl.c | 3 +- > arch/arm/mach-rockchip/rk3288/sdram_rk3288.c| 59 +- > board/radxa/rock/Kconfig| 15 + > board/radxa/rock/MAINTAINERS| 6 + > board/radxa/rock/Makefile | 7 + > board/radxa/rock/rock.c | 7 + > configs/rock_defconfig | 56 ++ > doc/README.rockchip | 26 + > doc/driver-model/README.txt | 4 + > drivers/clk/at91/pmc.c | 3 +- > drivers/clk/rockchip/Makefile | 1 + > drivers/clk/rockchip/clk_rk3188.c | 527 + > drivers/clk/rockchip/clk_rk3288.c | 2 + > drivers/core/root.c | 2 +- > drivers/core/util.c | 25 + > drivers/pinctrl/Kconfig | 9 + > drivers/pinctrl/pinctrl-uclass.c| 3 +- > drivers/pinctrl/rockchip/Makefile | 1 + > drivers/pinctrl/rockchip/pinctrl_rk3188.c | 611 +++ > drivers/serial/serial_rockchip.c| 19 +- > drivers/sysreset/Makefile | 1 + > drivers/sysreset/sysreset_rk3188.c | 47 ++ > include/configs/rk3188_common.h | 125 +++ > include/configs/rock.h | 30 + > include/dm/util.h | 26 + > include/dt-bindings/clock/rk3066a-cru.h | 32 + > include/dt-bindings/clock/rk3188-cru-common.h | 256 ++ > include/dt-bindings/clock/rk3188-cru.h | 48 ++ > mkuboot | 35 + > scripts/Makefile.spl| 7 +- > tools/dtoc/dtoc.py | 2 + > tools/rkcommon.c| 34 +- > tools/rkcommon.h| 22 + > tools/rkimage.c | 3 + > tools/rksd.c
Re: [U-Boot] [PATCH v3] armv8: spl: Call spl_relocate_stack_gd for ARMv8
On 22 February 2017 at 11:01, Philipp Tomsich wrote: > As part of the startup process for boards using the SPL, we need to > call spl_relocate_stack_gd. This is needed to set up malloc with its > DRAM buffer. > > Signed-off-by: Philipp Tomsich > Reviewed-by: Andre Przywara > Reviewed-by: Simon Glass > --- > arch/arm/lib/crt0_64.S | 13 +++-- > 1 file changed, 11 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S > index 19c6a98..a7cead5 100644 > --- a/arch/arm/lib/crt0_64.S > +++ b/arch/arm/lib/crt0_64.S > @@ -109,8 +109,17 @@ relocation_return: > */ > bl c_runtime_cpu_setup /* still call old routine */ > #endif /* !CONFIG_SPL_BUILD */ > - > -/* TODO: For SPL, call spl_relocate_stack_gd() to alloc stack relocation */ > +#if defined(CONFIG_SPL_BUILD) > + bl spl_relocate_stack_gd /* may return NULL */ > + /* Perform 'sp = (x0 != NULL) ? x0 : sp' while working > +* around the constraint that conditional moves can not > +* have 'sp' as an operand > +*/ nit: Comment style again > + mov x1, sp > + cmp x0, #0 > + cselx0, x0, x1, ne > + mov sp, x0 > +#endif > > /* > * Clear BSS section > -- > 1.9.1 > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/2] part_efi: document device-tree binding for part_efi configuration
On 22 February 2017 at 11:17, Philipp Tomsich wrote: > This moves the description of the /config node from README.fdt-control > into a separate file doc/device-tree-bindings/config.txt and adds the > documentation on the new u-boot,efi-partition-entries-offset property > (which overrides CONFIG_EFI_PARTITION_ENTRIES_OFF, if present). > > Signed-off-by: Philipp Tomsich > --- > doc/README.fdt-control | 16 > doc/device-tree-bindings/config.txt | 22 ++ > 2 files changed, 22 insertions(+), 16 deletions(-) > create mode 100644 doc/device-tree-bindings/config.txt Reviewed-by: Simon Glass (if you end up resending, this would be better as two separate patches) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/2] part_efi: support padding between the GPT header and partition entries
Hi Philipp,
On 22 February 2017 at 11:17, Philipp Tomsich
wrote:
> Some architectures require their SPL loader at a fixed address within
> the first 16KB of the disk. To avoid an overlap with the partition
> entries of the EFI partition table, the first safe offset (in bytes,
> from the start of the device) for the entries can be set through
> CONFIG_EFI_PARTITION_ENTRIES_OFF (via Kconfig)
>
> When formatting a device with an EFI partition table, we may need to
> leave a gap between the GPT header (always in LBA 1) and the partition
> entries. The GPT header already contains a field to specify the
> on-disk location, which has so far always been set to LBA 2. With this
> change, a configurable offset will be translated into a LBA address
> indicating where to put the entries.
>
> Now also allows an override via device-tree using a config-node (see
> doc/device-tree-bindings/config.txt for documentation).
>
> Tested (exporting an internal MMC formatted with this) against Linux,
> MacOS X and Windows.
>
> Signed-off-by: Philipp Tomsich
> ---
> disk/Kconfig| 13 +
> disk/part_efi.c | 50 ++
> 2 files changed, 59 insertions(+), 4 deletions(-)
Reviewed-by: Simon Glass
But please fix comment style below.
>
> diff --git a/disk/Kconfig b/disk/Kconfig
> index 16ff52d..8e328b4 100644
> --- a/disk/Kconfig
> +++ b/disk/Kconfig
> @@ -79,6 +79,19 @@ config EFI_PARTITION
> common when EFI is the bootloader. Note 2TB partition limit;
> see disk/part_efi.c
>
> +config EFI_PARTITION_ENTRIES_OFF
> +int "Offset (in bytes) of the EFI partition entries"
> + depends on EFI_PARTITION
> + default 0
> + help
> + Specify an earliest location (in bytes) where the partition
> + entries may be located. This is meant to allow "punching a
> + hole into a device" to create a gap for an SPL, its payload
> + and the U-Boot environment.
> +
> + If unsure, leave at 0 (which will locate the partition
> + entries at the first possible LBA following the GPT header).
> +
> config SPL_EFI_PARTITION
> bool "Enable EFI GPT partition table for SPL"
> depends on SPL && PARTITIONS
> diff --git a/disk/part_efi.c b/disk/part_efi.c
> index 893cbbd..fafca25 100644
> --- a/disk/part_efi.c
> +++ b/disk/part_efi.c
> @@ -13,6 +13,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -373,8 +374,8 @@ int write_gpt_table(struct blk_desc *dev_desc,
> if (blk_dwrite(dev_desc, 1, 1, gpt_h) != 1)
> goto err;
>
> - if (blk_dwrite(dev_desc, 2, pte_blk_cnt, gpt_e)
> - != pte_blk_cnt)
> + if (blk_dwrite(dev_desc, le64_to_cpu(gpt_h->partition_entry_lba),
> + pte_blk_cnt, gpt_e) != pte_blk_cnt)
> goto err;
>
> prepare_backup_gpt_header(gpt_h);
> @@ -498,6 +499,45 @@ int gpt_fill_pte(gpt_header *gpt_h, gpt_entry *gpt_e,
> return 0;
> }
>
> +static uint32_t partition_entries_offset(struct blk_desc *dev_desc)
> +{
> + uint32_t offset_blks = 2;
> + int config_offset;
> +
> +#if defined(CONFIG_EFI_PARTITION_ENTRIES_OFF)
> + /* Some architectures require their SPL loader at a fixed
First and last line of multi-line comment should not have any text:
/*
* Some arch...
* ...
* ...
*/
> +* address within the first 16KB of the disk. To avoid an
> +* overlap with the partition entries of the EFI partition
> +* table, the first safe offset (in bytes, from the start of
> +* the disk) for the entries can be set in
> +* CONFIG_EFI_PARTITION_ENTRIES_OFF.
> +*/
> + offset_blks =
> + PAD_TO_BLOCKSIZE(CONFIG_EFI_PARTITION_ENTRIES_OFF, dev_desc);
> +#endif
> +
> +#if defined(CONFIG_OF_CONTROL)
> + /* Allow the offset of the first partition entires (in bytes
> + from the start of the device) to be specified as a property
> + of the device tree '/config' node. */
Also here
> + config_offset = fdtdec_get_config_int(gd->fdt_blob,
> +
> "u-boot,efi-partition-entries-offset",
> + -EINVAL);
> + if (config_offset != -EINVAL)
> + offset_blks = PAD_TO_BLOCKSIZE(config_offset, dev_desc);
> +#endif
> +
> + debug("efi: partition entries offset (in blocks): %d\n", offset_blks);
> +
> + /* The earliest LBA this can be at is LBA#2 (i.e. right behind
> +* the (protective) MBR and the GPT header.
> +*/
> + if (offset_blks < 2)
> + offset_blks = 2;
> +
> + return offset_blks;
> +}
> +
> int gpt_fill_header(struct blk_desc *dev_desc, gpt_header *gpt_h,
> char *str_guid, int parts_count)
> {
> @@ -506,9 +546,11 @@ int gpt_fill_header(struct blk_desc *dev_desc,
> gpt_header *gpt_h,
>
Re: [U-Boot] [PATCH v2] dtoc: make ScanTree recurse into subnodes
On 22 February 2017 at 11:06, Philipp Tomsich
wrote:
>
> Previously, dtoc could only process the top-level nodes which led to
> device nodes in hierarchical trees to be ignored. E.g. the mmc0 node
> in the following example would be ignored, as only the soc node was
> processed:
>
> / {
> soc {
> mmc0 {
> /* ... */
> };
> };
> };
>
> This introduces a recursive helper method ScanNode, which is used by
> ScanTree to recursively parse the entire tree hierarchy.
>
> Signed-off-by: Philipp Tomsich
> ---
> tools/dtoc/dtoc.py | 19 ++-
> 1 file changed, 18 insertions(+), 1 deletion(-)
Reviewed-by: Simon Glass
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Re: [U-Boot] rockchip: rk3288: init malloc_base, limit, ptr before spl_init
Hi Eddie,
On 22 February 2017 at 19:04, Eddie Cai wrote:
> Hi Simon
>
> 2017-02-22 12:00 GMT+08:00 Simon Glass :
>>
>> Hi Eddie,
>>
>> On 21 February 2017 at 01:15, Eddie Cai wrote:
>> > Andrew F. Davis's below patch broke rk3288 based board. that is because
>> > we call
>> > spl_init in board_init_f which is at very early stage. What Andrew want
>> > to fix
>> > is calling spl_init very late. That patch will make malloc_base, limit,
>> > ptr not
>> > initualized in spl_init when we call spl_init in board_init_f. It seems
>> > impossible to meet two requirement in spl_init. So i simply init
>> > malloc_base,
>> > limit, ptr before spl_init.
>> >
>> > commit b3d2861eb20a795b99292b823c923935df26dfc6
>> > Author: Andrew F. Davis
>> > Date: Fri Jan 27 10:39:19 2017 -0600
>> >
>> > spl: Remove overwrite of relocated malloc limit
>> >
>> > Signed-off-by: Eddie Cai
>> > ---
>> > arch/arm/mach-rockchip/rk3288-board-spl.c | 10 ++
>> > 1 file changed, 10 insertions(+)
>> >
>> > diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c
>> > b/arch/arm/mach-rockchip/rk3288-board-spl.c
>> > index 930939a..1f3170d 100644
>> > --- a/arch/arm/mach-rockchip/rk3288-board-spl.c
>> > +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
>> > @@ -184,6 +184,16 @@ void board_init_f(ulong dummy)
>> > debug_uart_init();
>> > #endif
>> >
>> > +#if defined(CONFIG_SYS_MALLOC_F_LEN)
>> > +#ifdef CONFIG_MALLOC_F_ADDR
>> > + gd->malloc_base = CONFIG_MALLOC_F_ADDR;
>> > +#endif
>> > +#ifdef CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN
>> > + gd->malloc_limit = CONFIG_SYS_MALLOC_F_LEN;
>> > +#endif
>> > + gd->malloc_ptr = 0;
>> > +#endif
>> > +
>>
>> Yuck we should not repeat this code. Can we instead have two versions
>> of spl_init()? Perhaps call the one that always sets things up
>> spl_early_init() since it is called before board_init_r()?
>
> I search but did find spl_early_init in mainline U-Boot. I found exynos
> U-Boot for chromium os have spl_early_init. But it is far away from what we
> need. So i add one by myself.
Sorry I wasn't clear. Yes I meant to create a new one, like (and next
to) the existing one, pulling out any common code that you can.
>>
>>
>> > ret = spl_init();
>> > if (ret) {
>> > debug("spl_init() failed: %d\n", ret);
>> > --
>> > 2.7.4
>> >
>>
>> Regards,
>> Simon
>
>
Regards,
Simon
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Re: [U-Boot] [PATCH 3/7] clk: rockchip: add support for rk3328
+Tom Hi Kever, On 22 February 2017 at 02:45, Kever Yang wrote: > > Hi Simon, > > > On 02/22/2017 02:06 AM, Simon Glass wrote: >> >> Hi Kever, >> >> On 17 February 2017 at 01:07, Kever Yang wrote: >>> >>> Add rk3328 clock driver and cru structure definition. >>> >>> Signed-off-by: William Zhang >>> Signed-off-by: Kever Yang >>> --- >>> >>> arch/arm/include/asm/arch-rockchip/cru_rk3328.h | 65 +++ >>> drivers/clk/rockchip/Makefile | 1 + >>> drivers/clk/rockchip/clk_rk3328.c | 607 >>> >>> 3 files changed, 673 insertions(+) >>> create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3328.h >>> create mode 100644 drivers/clk/rockchip/clk_rk3328.c >>> >> [..] >> >>> + >>> +#define I2C_CLK_REG_MASK(bus) \ >>> + (CLK_I2C_DIV_CON_MASK << \ >>> + CLK_I2C ##bus## _DIV_CON_SHIFT | \ >>> + CLK_I2C_PLL_SEL_MASK << \ >>> + CLK_I2C ##bus## _PLL_SEL_SHIFT) >>> + >>> +#define (bus, clk_div) \ >>> +((clk_div - 1) << \ >>> +CLK_I2C ##bus## _DIV_CON_SHIFT | \ >>> +CLK_I2C_PLL_SEL_GPLL << \ >>> +CLK_I2C ##bus## _PLL_SEL_SHIFT) >>> + >>> +#define I2C_CLK_DIV_VALUE(con, bus) \ >>> +(con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \ >>> +CLK_I2C_DIV_CON_MASK; >> >> Can we drop these three and instead write them out below? > > > I don't know why you don't like this kind of MACRO, like the size_mb in sdram > driver, > we though this help people understand the C source and make the C source cold > looks much clean, > in some platform, maintainer may ask for this when there are multi controller > and can reuse > the same MACRO. > Anyway, I will make this fallback to normal shift/mask style in next version. > Let me try to explain this. In this code macros are created by pasting symbols together which means (for example) that it is not possible to find the definition of CLK_I2C 0_DIV_CON_SHIFT by searching the code. This can be very confusing for people trying to figure out what is going on. It is bad enough in a single file but gets worse when things migrate to header files. If you want to have a macro here, how about #define CLK_I2C DIV_CON_SHIFT(bus) instead? This can return the appropriate shift for the bus. The 'I2C_CLK_DIV_VALUE' macro is only used in rk3328_i2c_get_clk() and ends up creating repetitive code (all the macro logic happens in each case of the switch() , which the compiler hopefully can optimize, but who knows? In any case conceptually I do not think it simplifies the code. You end up unpicking the macros and printing out intermediate values, etc. I have definitely done my share of that. The rule of using shifts and masks in the code rather than hiding them originally came from Wolfgang and I have got used to it. One thing I have noticed is that with macros you can build up a tree of interdependent macros such that it is very hard to figure out what is actually going on, e.g. if you are looking for a bug. I am aware that the code style in coreboot and UEFI are different, although I am not an expert in either. Does that make sense? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] rockchip: rk3288: init malloc_base, limit, ptr before spl_init
Hi Simon
2017-02-22 12:00 GMT+08:00 Simon Glass :
> Hi Eddie,
>
> On 21 February 2017 at 01:15, Eddie Cai wrote:
> > Andrew F. Davis's below patch broke rk3288 based board. that is because
> we call
> > spl_init in board_init_f which is at very early stage. What Andrew want
> to fix
> > is calling spl_init very late. That patch will make malloc_base, limit,
> ptr not
> > initualized in spl_init when we call spl_init in board_init_f. It seems
> > impossible to meet two requirement in spl_init. So i simply init
> malloc_base,
> > limit, ptr before spl_init.
> >
> > commit b3d2861eb20a795b99292b823c923935df26dfc6
> > Author: Andrew F. Davis
> > Date: Fri Jan 27 10:39:19 2017 -0600
> >
> > spl: Remove overwrite of relocated malloc limit
> >
> > Signed-off-by: Eddie Cai
> > ---
> > arch/arm/mach-rockchip/rk3288-board-spl.c | 10 ++
> > 1 file changed, 10 insertions(+)
> >
> > diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c
> b/arch/arm/mach-rockchip/rk3288-board-spl.c
> > index 930939a..1f3170d 100644
> > --- a/arch/arm/mach-rockchip/rk3288-board-spl.c
> > +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
> > @@ -184,6 +184,16 @@ void board_init_f(ulong dummy)
> > debug_uart_init();
> > #endif
> >
> > +#if defined(CONFIG_SYS_MALLOC_F_LEN)
> > +#ifdef CONFIG_MALLOC_F_ADDR
> > + gd->malloc_base = CONFIG_MALLOC_F_ADDR;
> > +#endif
> > +#ifdef CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN
> > + gd->malloc_limit = CONFIG_SYS_MALLOC_F_LEN;
> > +#endif
> > + gd->malloc_ptr = 0;
> > +#endif
> > +
>
> Yuck we should not repeat this code. Can we instead have two versions
> of spl_init()? Perhaps call the one that always sets things up
> spl_early_init() since it is called before board_init_r()?
>
I search but did find spl_early_init in mainline U-Boot. I found exynos
U-Boot for chromium os have spl_early_init. But it is far away from what we
need. So i add one by myself.
>
> > ret = spl_init();
> > if (ret) {
> > debug("spl_init() failed: %d\n", ret);
> > --
> > 2.7.4
> >
>
> Regards,
> Simon
>
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[U-Boot] [U-Boot 2/2] rockchip: use spl_early_init instead of spl_init
use spl_early_init to avoid malloc_base, limit, ptr not initualized.
Signed-off-by: Eddie Cai
---
arch/arm/mach-rockchip/rk3288-board-spl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c
b/arch/arm/mach-rockchip/rk3288-board-spl.c
index 930939a..02ab5a4 100644
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
@@ -184,7 +184,7 @@ void board_init_f(ulong dummy)
debug_uart_init();
#endif
- ret = spl_init();
+ ret = spl_early_init();
if (ret) {
debug("spl_init() failed: %d\n", ret);
hang();
--
2.7.4
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[U-Boot] pull request: u-boot-uniphier/master
Hi Tom, Please pull the 4th round of UniPhier updates for v2017.03: - Fix regressions caused by the previous reworks - Add pin configuration support - Re-work SPL code - Update DRAM and PLL setup code - Enable needed configs, disable unneeded configs The following changes since commit b24cf8540a85a9bf97975aadd6a7542f166c78a3: video: mxsfb: Fix reset hang when videomode variable is not present (2017-02-22 21:47:59 +0100) are available in the git repository at: git://git.denx.de/u-boot-uniphier.git master for you to fetch changes up to bc647958047cd03193e19cd8c08a6771fea828b7: ARM: uniphier: set up charge pump current for MPLL of LD11 SoC (2017-02-23 09:00:16 +0900) Kotaro Hayashi (1): ARM: uniphier: add DRAM PHY clock duty adjustment for LD20 SoC Masahiro Yamada (22): ARM: uniphier: revive accidentally removed dcache_disable() ARM: uniphier: skip MEMCONF ch2 parsing if CH2_DISABLE bit is set ARM: uniphier: correct spelling of "invalid" ARM: uniphier: skip memreserve of unused DRAM bank of LD20 ARM: uniphier: print Support Card info very late ARM: uniphier: update README.uniphier for latest build instruction ARM: uniphier: remove DRAM base address from board parameters ARM: uniphier: enable generic EHCI driver for uniphier_v8_defconfig pinctrl: uniphier: support pin configuration ARM: uniphier: rename second stage loader name ARM: dts: uniphier: drop u-boot, dm-pre-reloc from system-bus pinctrl node ARM: uniphier: disable CONFIG_MTD_NOR_FLASH ARM: uniphier: move MMC code to a separate file ARM: uniphier: move spl_boot_mode() to a separate file ARM: uniphier: rework spl_boot_device() and related code ARM: uniphier: remove dram_nr_ch from board parameters ARM: uniphier: deassert RST_n of eMMC device for LD11/LD20 ARM: uniphier: disable CONFIG_SPL_DOS_PARTITION ARM: uniphier: enable CONFIG_CMD_GPT ARM: uniphier: enable CONFIG_CMD_CONFIG ARM: uniphier: add simple eMMC load APIs instead of ROM API ARM: uniphier: set up charge pump current for MPLL of LD11 SoC arch/arm/dts/uniphier-ld11-ref.dts | 4 - arch/arm/dts/uniphier-ld20-ref.dts | 4 - arch/arm/mach-uniphier/Makefile | 4 +- arch/arm/mach-uniphier/bcu/bcu-ld4.c| 2 +- arch/arm/mach-uniphier/bcu/bcu-sld3.c | 2 +- arch/arm/mach-uniphier/board_init.c | 1 + arch/arm/mach-uniphier/board_late_init.c| 4 +- arch/arm/mach-uniphier/boards.c | 42 +--- arch/arm/mach-uniphier/boot-device/Makefile | 19 ++ .../boot-mode-ld20.c => boot-device/boot-device-ld11.c} | 52 ++--- .../boot-mode-ld4.c => boot-device/boot-device-ld4.c} | 36 +--- .../boot-mode-pro5.c => boot-device/boot-device-pro5.c} | 36 +--- .../boot-mode-pxs2.c => boot-device/boot-device-pxs2.c} | 37 ++-- .../boot-mode-sld3.c => boot-device/boot-device-sld3.c} | 36 +--- arch/arm/mach-uniphier/boot-device/boot-device.c| 206 +++ arch/arm/mach-uniphier/boot-device/boot-device.h| 35 arch/arm/mach-uniphier/boot-device/spl_board.c | 262 + arch/arm/mach-uniphier/boot-mode/Makefile | 21 -- arch/arm/mach-uniphier/boot-mode/boot-device.h | 29 --- arch/arm/mach-uniphier/boot-mode/boot-mode.c| 140 - arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c | 59 -- arch/arm/mach-uniphier/boot-mode/spl_board.c| 125 arch/arm/mach-uniphier/clk/Makefile | 2 +- arch/arm/mach-uniphier/clk/clk-ld11.c | 8 +- arch/arm/mach-uniphier/clk/clk-ld20.c | 17 ++ arch/arm/mach-uniphier/clk/pll-base-ld20.c | 21 ++ arch/arm/mach-uniphier/clk/pll-ld11.c | 2 + arch/arm/mach-uniphier/clk/pll.h| 1 + arch/arm/mach-uniphier/dram/umc-ld11.c | 2 +- arch/arm/mach-uniphier/dram/umc-ld20.c | 25 ++- arch/arm/mach-uniphier/dram/umc-pxs2.c | 14 +- arch/arm/mach-uniphier/dram_init.c | 64 +++--- arch/arm/mach-uniphier/init.h | 9 +- arch/arm/mach-uniphier/memconf.c| 2 +- arch/arm/mach-uniphier/micro-support-card.c | 11 +- arch/arm/mach-uniphier/mmc-boot-mode.c | 34 arch/arm/mach-uniphier/mmc-first-dev.c | 46 + arch/arm/mach-uniphier/spl_board_init.c | 4 + configs/uniphier_ld11_defconfig
[U-Boot] [U-Boot 0/2] add spl_early_init to fix rk3288 board broken issue
Andrew F. Davis's below patch broke rk3288 based board. that is because we call spl_init in board_init_f which is at very early stage. What Andrew want to fix is calling spl_init very late. That patch will make malloc_base, limit, ptr not initualized in spl_init when we call spl_init in board_init_f. This patch set add spl_early_init. it can be called in board_init_f. So we can fix this issue by using spl_early_init. commit b3d2861eb20a795b99292b823c923935df26dfc6 Author: Andrew F. Davis Date: Fri Jan 27 10:39:19 2017 -0600 spl: Remove overwrite of relocated malloc limit Eddie Cai (2): spl: add spl_early_init rockchip: use spl_early_init instead of spl_init arch/arm/mach-rockchip/rk3288-board-spl.c | 2 +- common/spl/spl.c | 54 ++- include/asm-generic/global_data.h | 1 + include/spl.h | 12 ++- 4 files changed, 59 insertions(+), 10 deletions(-) -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-Boot 1/2] spl: add spl_early_init
Andrew F. Davis's below patch will make malloc_base, limit, ptr not initualized
in spl_init when we call spl_init in board_init_f. Add spl_early_init which can
be called in board_init_f to fix this issue.
commit b3d2861eb20a795b99292b823c923935df26dfc6
Author: Andrew F. Davis
Date: Fri Jan 27 10:39:19 2017 -0600
spl: Remove overwrite of relocated malloc limit
Signed-off-by: Eddie Cai
---
common/spl/spl.c | 54 +--
include/asm-generic/global_data.h | 1 +
include/spl.h | 12 -
3 files changed, 58 insertions(+), 9 deletions(-)
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 766fb3d..26bc9ef 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -170,21 +170,19 @@ __weak void __noreturn jump_to_image_no_args(struct
spl_image_info *spl_image)
image_entry();
}
-int spl_init(void)
+int spl_early_init(void)
{
int ret;
- debug("spl_init()\n");
-/*
- * with CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN we set malloc_base and
- * malloc_limit in spl_relocate_stack_gd
- */
-#if defined(CONFIG_SYS_MALLOC_F_LEN) && \
- !defined(CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN)
+ debug("spl_early_init()\n");
+
+#if defined(CONFIG_SYS_MALLOC_F_LEN)
#ifdef CONFIG_MALLOC_F_ADDR
gd->malloc_base = CONFIG_MALLOC_F_ADDR;
#endif
+#ifdef CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN
gd->malloc_limit = CONFIG_SYS_MALLOC_F_LEN;
+#endif
gd->malloc_ptr = 0;
#endif
if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) {
@@ -202,6 +200,46 @@ int spl_init(void)
return ret;
}
}
+ gd->flags |= GD_FLG_SPL_EARLY_INIT;
+
+ return 0;
+}
+
+int spl_init(void)
+{
+ int ret;
+
+ debug("spl_init()\n");
+/*
+ * with CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN we set malloc_base and
+ * malloc_limit in spl_relocate_stack_gd
+ */
+ if (!(gd->flags & GD_FLG_SPL_EARLY_INIT)) {
+#if defined(CONFIG_SYS_MALLOC_F_LEN) && \
+ !defined(CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN)
+#ifdef CONFIG_MALLOC_F_ADDR
+ gd->malloc_base = CONFIG_MALLOC_F_ADDR;
+#endif
+ gd->malloc_limit = CONFIG_SYS_MALLOC_F_LEN;
+ gd->malloc_ptr = 0;
+#endif
+
+ if (CONFIG_IS_ENABLED(OF_CONTROL) &&
!CONFIG_IS_ENABLED(OF_PLATDATA)) {
+ ret = fdtdec_setup();
+ if (ret) {
+ debug("fdtdec_setup() returned error %d\n",
ret);
+ return ret;
+ }
+ }
+ if (IS_ENABLED(CONFIG_SPL_DM)) {
+ /* With CONFIG_SPL_OF_PLATDATA, bring in all devices */
+ ret = dm_init_and_scan(!CONFIG_IS_ENABLED(OF_PLATDATA));
+ if (ret) {
+ debug("dm_init_and_scan() returned error %d\n",
ret);
+ return ret;
+ }
+ }
+ }
gd->flags |= GD_FLG_SPL_INIT;
return 0;
diff --git a/include/asm-generic/global_data.h
b/include/asm-generic/global_data.h
index e02863d..17ed3dc 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -127,5 +127,6 @@ typedef struct global_data {
#define GD_FLG_SKIP_RELOC 0x00800 /* Don't relocate */
#define GD_FLG_RECORD 0x01000 /* Record console */
#define GD_FLG_ENV_DEFAULT 0x02000 /* Default variable flag */
+#define GD_FLG_SPL_EARLY_INIT 0x04000 /* Default variable flag */
#endif /* __ASM_GENERIC_GBL_DATA_H */
diff --git a/include/spl.h b/include/spl.h
index bde4437..a89ac00 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -213,7 +213,7 @@ int spl_load_image_ext_os(struct spl_image_info *spl_image,
struct blk_desc *block_dev, int partition);
/**
- * spl_init() - Set up device tree and driver model in SPL if enabled
+ * spl_early_init() - Set up device tree and driver model in SPL if enabled
*
* Call this function in board_init_f() if you want to use device tree and
* driver model early, before board_init_r() is called. This function will
@@ -222,6 +222,16 @@ int spl_load_image_ext_os(struct spl_image_info *spl_image,
* If this is not called, then driver model will be inactive in SPL's
* board_init_f(), and no device tree will be available.
*/
+int spl_early_init(void);
+
+/**
+ * spl_init() - Set up device tree and driver model in SPL if enabled
+ *
+ * This function will be called from board_init_r() if not called earlier.
+ *
+ * If this is not called, then driver model will be inactive in SPL's
+ * board_init_f(), and no device tree will be available.
+ */
int spl_init(void);
#ifdef CONFIG_SPL_BOARD_INIT
--
2.7.4
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Re: [U-Boot] [PATCH 00/29] blackfin: Add driver-model and device tree suport
+Tom Hi, On 14 December 2016 at 20:27, Simon Glass wrote: > At present the only serial driver that is not converted to driver mode is > blackfin. As I recently obtained a suitable board from a kind donor I have > decided to convert the driver over, as the unpalatable alternative would > be to remove blackfin support from U-Boot. > > Blackfin's init sequence is someone non-standard. This series adjusts this > to fit more with how things are now done, adds device-tree support, a > serial driver and enables driver model on bf537-stamp. > > A few CONFIG options are dropped in this series also, as these were > noticed along the way. > > Future work could enhance the serial driver to support v4 hardware and > convert all boards to driver model. > > > Simon Glass (29): > blackfin: Drop CONFIG_SYS_MEMTEST_START/END > fdt: Allow the device tree to be set up by board init code > blackfin: Add a few useful linker symbols > blackfin: Drop the extra blank line in the link script > blackfin: Use compiler-generated symbols for BSS > blackfin: Clear the BSS in C code > blackfin: Add a memory region for pre-relocation data > blackfin: Use generic board to set the stack address > blackfin: Avoid using bd_info in print_cpuinfo() > blackfin: Avoiding using P3 in early init > blackfin: Allow cpu_init_f() to return > blackfin: Drop CONFIG_STACKBASE > tegra: Drop CONFIG_STACKBASE in favour of TEGRA_STACKBASE > sparc: Drop CONFIG_SYS_MALLOC_BASE > blackfin: Drop CONFIG_SYS_MALLOC_BASE > Drop CONFIG_SYS_MALLOC_END > blackfin: Call C code to relocate > blackfin: Don't set global_data again > blackfin: Set the RAM size separately from bd_info > blackfin: Set up bd_info later > blackfin: Copy the device tree out of BSS > blackfin: Allow use of CONFIG_OF_CONTROL > blackfin: bf537-stamp: Enable CONFIG_OF_CONTROL > dm: serial: Reset the watchdog when outputting characters > dm: serial: pxa: Drop pxa from the serial README > dm: serial: Update the serial README > dm: blackfin: Add a driver-model serial driver > blackfin: Set up the debug UART if enabled > blackfin: Enable driver-model on bf537-stamp > > arch/Kconfig| 1 + > arch/blackfin/Kconfig | 9 ++ > arch/blackfin/cpu/cpu.c | 69 +++-- > arch/blackfin/cpu/start.S | 35 +++ > arch/blackfin/cpu/u-boot.lds| 24 - > arch/blackfin/dts/Makefile | 18 > arch/blackfin/dts/bf537-stamp.dts | 11 +++ > arch/blackfin/include/asm/config.h | 12 --- > arch/blackfin/include/asm/serial1.h | 2 + > arch/blackfin/include/asm/u-boot.h | 5 + > arch/blackfin/lib/sections.c| 2 +- > cmd/bdinfo.c| 2 - > configs/bf537-stamp_defconfig | 8 ++ > doc/driver-model/serial-howto.txt | 11 +-- > drivers/serial/Kconfig | 8 ++ > drivers/serial/serial-uclass.c | 2 + > drivers/serial/serial_bfin.c| 192 > > include/configs/bf537-stamp.h | 1 + > include/configs/bf609-ezkit.h | 1 - > include/configs/gr_cpci_ax2000.h| 5 +- > include/configs/gr_ep2s60.h | 5 +- > include/configs/gr_xc3s_1500.h | 5 +- > include/configs/grsim.h | 5 +- > include/configs/grsim_leon2.h | 5 +- > include/configs/openrisc-generic.h | 3 - > include/configs/s32v234evb.h| 4 - > include/configs/tegra-common.h | 2 +- > include/configs/tegra114-common.h | 2 +- > include/configs/tegra124-common.h | 2 +- > include/configs/tegra186-common.h | 2 +- > include/configs/tegra20-common.h| 2 +- > include/configs/tegra210-common.h | 2 +- > include/configs/tegra30-common.h| 2 +- > lib/fdtdec.c| 31 +++--- > scripts/config_whitelist.txt| 3 - > 35 files changed, 360 insertions(+), 133 deletions(-) > create mode 100644 arch/blackfin/dts/Makefile > create mode 100644 arch/blackfin/dts/bf537-stamp.dts > > -- > 2.8.0.rc3.226.g39d4020 > Any reviews on this? Will someone pick it up? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] net: Kconfig:make PHY_GIGE and individual Micrel PHYs selectable
Hi, On Wed, Feb 22, 2017 at 09:58:42PM +0100, Philipp Tomsich wrote: > This changeset moves two configuration options into Kconfig: > * PHY_GIGE, indicates that a controller (with an appropriate PHY) is >Gigabit capable and enables extra support in the miiutil for >parsing the status of Gigabit PHYs > * individual configuration options for MICREL_KSZ9021 and >MICREL_KSZ9031 GbE PHYs, which previously had to enabled through >a board-specific config file > > Signed-off-by: Philipp Tomsich > --- > drivers/net/Kconfig | 7 +++ > drivers/net/phy/Kconfig | 10 ++ > 2 files changed, 17 insertions(+) > > diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig > index 078d5a8..845df09 100644 > --- a/drivers/net/Kconfig > +++ b/drivers/net/Kconfig > @@ -22,6 +22,12 @@ menuconfig NETDEVICES > > if NETDEVICES > > +config PHY_GIGE > +bool The indentation is wrong here (spaces instead of tabs), and it would be great if you could add a label, so that we can select in in menuconfig. > + help > + Enables support for parsing the status output and > + configuring GbE PHYs (e.g. via miiphyutil.c) > + > config AG7XXX > bool "Atheros AG7xxx Ethernet MAC support" > depends on DM_ETH && ARCH_ATH79 > @@ -165,6 +171,7 @@ config SUN8I_EMAC > bool "Allwinner Sun8i Ethernet MAC support" > depends on DM_ETH > select PHYLIB > + select PHY_GIGE > help >This driver supports the Allwinner based SUN8I/SUN50I Ethernet > MAC. > It can be found in H3/A64/A83T based SoCs and compatible with both > diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig > index 1d514e9..0941383 100644 > --- a/drivers/net/phy/Kconfig > +++ b/drivers/net/phy/Kconfig > @@ -45,6 +45,16 @@ config PHY_MARVELL > config PHY_MICREL > bool "Micrel Ethernet PHYs support" > > +if PHY_MICREL > + > +config PHY_MICREL_KSZ9021 > +bool "Micrel KSZ9021 family support" > + > +config PHY_MICREL_KSZ9031 > +bool "Micrel KSZ9031 family support" There's the same indentation issues here, and having some help notice would be great. Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] arm: mach-omap2: Flush cache after FIT post-processing image
After we authenticate/decrypt an image we need to flush the caches
as they may still contain bits of the encrypted image. This will
cause failures if we attempt to jump to this image.
Reported-by: Yogesh Siraswar
Signed-off-by: Andrew F. Davis
---
arch/arm/mach-omap2/sec-common.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-omap2/sec-common.c b/arch/arm/mach-omap2/sec-common.c
index c5a000ac3a..0fa8db05fe 100644
--- a/arch/arm/mach-omap2/sec-common.c
+++ b/arch/arm/mach-omap2/sec-common.c
@@ -120,6 +120,12 @@ int secure_boot_verify_image(void **image, size_t *size)
result = secure_rom_call(
API_HAL_KM_VERIFYCERTIFICATESIGNATURE_INDEX, 0, 0,
4, cert_addr, cert_size, sig_addr, 0x);
+
+ /* Perform cache writeback on output buffer */
+ flush_dcache_range(
+ (u32)*image,
+ (u32)*image + roundup(*size, ARCH_DMA_MINALIGN));
+
auth_exit:
if (result != 0) {
printf("Authentication failed!\n");
--
2.11.0
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Re: [U-Boot] [PATCH] ARM: uniphier: revive accidentally removed dcache_disable()
2017-02-20 14:23 GMT+09:00 Masahiro Yamada :
> Commit a8e6300d483d ("ARM: uniphier: refactor spl_init_board()")
> accidentally dropped dcache_disable() call. Since then, the SPL of
> LD11 and LD20 failed to load U-Boot proper.
>
> Fixes: a8e6300d483d ("ARM: uniphier: refactor spl_init_board()")
> Signed-off-by: Masahiro Yamada
Applied to u-boot-uniphier.
--
Best Regards
Masahiro Yamada
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Re: [U-Boot] [PATCH] ARM: uniphier: enable CONFIG_CMD_CONFIG
2017-02-21 15:09 GMT+09:00 Masahiro Yamada : > This command is useful to see which config options are enabled on > the running U-Boot image. > > Signed-off-by: Masahiro Yamada Applied to u-boot-uniphier. -- Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: uniphier: correct spelling of "invalid"
2017-02-20 12:09 GMT+09:00 Masahiro Yamada : > Signed-off-by: Masahiro Yamada Applied to u-boot-uniphier. -- Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: uniphier: deassert RST_n of eMMC device for LD11/LD20
2017-02-17 16:17 GMT+09:00 Masahiro Yamada : > For LD11 and LD20 SoCs, the RST_n pin is asserted by default. If > the EXT_CSD[162], bit[1:0] (RST_n_ENABLE) is fused, the eMMC device > would stay in the reset state until its RST_n pin is deasserted by > software. > > Currently, this is cared by an ad-hoc way because the eMMC hardware > reset provider is not supported in U-Boot for now. This code should > be re-written once the "mmc-pwrseq-emmc" binding is supported. > > Signed-off-by: Masahiro Yamada Applied to u-boot-uniphier. -- Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: uniphier: print Support Card info very late
2017-02-20 17:32 GMT+09:00 Masahiro Yamada :
> Since commit 26b09c022ab6 ("ARM: uniphier: move SBC and Support Card
> init code to U-Boot proper"), the System Bus is initialized by
> board_init(). The show_board_info() is called from board_init_f()
> by default, so the revision register of the Micro Support Card may
> not be accessed at this point. Show its revision after the System
> Bus is initialized.
>
> Signed-off-by: Masahiro Yamada
Applied to u-boot-uniphier.
--
Best Regards
Masahiro Yamada
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Re: [U-Boot] [PATCH] ARM: uniphier: skip memreserve of unused DRAM bank of LD20
2017-02-20 17:13 GMT+09:00 Masahiro Yamada :
> Now the "for" loop here iterates on the detected memory banks.
> It must skip unused DRAM banks.
>
> Fixes: c995f3a3c526 ("ARM: uniphier: use gd->bd->bi_dram for memory reserve
> on LD20 SoC")
> Signed-off-by: Masahiro Yamada
Applied to u-boot-uniphier.
--
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Masahiro Yamada
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Re: [U-Boot] [PATCH] ARM: uniphier: skip MEMCONF ch2 parsing if CH2_DISABLE bit is set
2017-02-20 12:10 GMT+09:00 Masahiro Yamada : > If SG_MEMCONF_CH2_DISABLE bit is set, the DRAM channel 2 is unused. > The register settings for the ch2 should be ignored. > > Signed-off-by: Masahiro Yamada Applied to u-boot-uniphier. -- Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: uniphier: disable CONFIG_SPL_DOS_PARTITION
2017-02-17 16:17 GMT+09:00 Masahiro Yamada : > The SPL for UniPhier platform does not recognize any partitions. > Do not compile unneeded features. > > Signed-off-by: Masahiro Yamada > --- Applied to u-boot-uniphier. -- Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: uniphier: remove dram_nr_ch from board parameters
2017-02-16 15:59 GMT+09:00 Masahiro Yamada : > This parameter is redundant because we can know the number of > channels by checking if dram_ch[2].size is zero. > > Signed-off-by: Masahiro Yamada Applied to u-boot-uniphier. -- Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: uniphier: enable CONFIG_CMD_GPT
2017-02-17 16:17 GMT+09:00 Masahiro Yamada : > Enable CONFIG_CMD_GPT, keeping CONFIG_SPL_EFI_PARTITION because the > SPL for UniPhier platform does not recognize any partitions. > > Signed-off-by: Masahiro Yamada > Applied to u-boot-uniphier. -- Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] ARM: uniphier: move MMC code to a separate file
2017-02-14 1:24 GMT+09:00 Masahiro Yamada : > Currently, arch/arm/mach-uniphier/boot-mode/boot-mode.c is messed up > with unrelated code; there is no reason why the "mmcsetn" command > must be placed in this file. > > Split out the MMC code into arch/arm/mach-uniphier/mmc-first-dev.c. > > Signed-off-by: Masahiro Yamada Series, applied to u-boot-uniphier. -- Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Makefile: print warning if CONFIG_SYS_EXTRA_OPTIONS is used
On Tue, Feb 21, 2017 at 08:58:55PM -0700, Simon Glass wrote: > Hi, > > On 21 February 2017 at 16:16, Maxime Ripard > wrote: > > On Sat, Feb 18, 2017 at 03:24:53PM +0900, Masahiro Yamada wrote: > >> The prompt of this option is marked "DEPRECATED" in capital letters, > >> and its help clearly says: > >> This option was prepared for the smooth migration from the old > >> configuration to Kconfig. Since this option will be removed sometime, > >> new boards should not use this option. > >> > >> However, we have had almost no progress on this. In fact, this > >> option is often abused for fresh porting, and more and more new > >> defconfigs with it are coming in (for example, SUNXI boards). > > > > That's not entirely true. We've added more defconfig, but with the > > same set of options we've always had, and are shared by everyone > > (CONS_INDEX, RGMII). > > > > So this patch, in effect, gives the signal that it's better to have a > > proliferation of board-specific headers in include/configs, over using > > SYS_EXTRA until most of the generic functions are merged? > > I suppose whoever adds the next board gets to do the conversion? That seems a bit unfair to ask someone that barely got into U-Boot to enable his new shiny sunxi board to convert the old Freescale's PPC defconfig in the process. Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Makefile: print warning if CONFIG_SYS_EXTRA_OPTIONS is used
On Wed, Feb 22, 2017 at 11:23:56AM -0500, Tom Rini wrote: > On Wed, Feb 22, 2017 at 11:53:05AM +0900, Masahiro Yamada wrote: > > 2017-02-22 8:16 GMT+09:00 Maxime Ripard : > > > On Sat, Feb 18, 2017 at 03:24:53PM +0900, Masahiro Yamada wrote: > > >> The prompt of this option is marked "DEPRECATED" in capital letters, > > >> and its help clearly says: > > >> This option was prepared for the smooth migration from the old > > >> configuration to Kconfig. Since this option will be removed sometime, > > >> new boards should not use this option. > > >> > > >> However, we have had almost no progress on this. In fact, this > > >> option is often abused for fresh porting, and more and more new > > >> defconfigs with it are coming in (for example, SUNXI boards). > > > > > > That's not entirely true. We've added more defconfig, but with the > > > same set of options we've always had, and are shared by everyone > > > (CONS_INDEX, RGMII). > > > > > > So this patch, in effect, gives the signal that it's better to have a > > > proliferation of board-specific headers in include/configs, over using > > > SYS_EXTRA until most of the generic functions are merged? > > > > No. > > > > I am saying to add > > CONFIG_CONS_INDEX=2 > > CONFIG_RGMII=y > > > > instead of > > > > CONFIG_SYS_EXTRA_OPTIONS=CONS_INDEX=2,RGMII" > > > > > > Why proliferation of board-specific headers? > > The issue here is that we have a handful of options that need converting > still, and are not "easy". For CONS_INDEX we need to find the right > generic location for this to be and migrate, and remove the few > instances of board-centric versions of the question. > > I agree with the sentiment of the original patch but I want to see how > many of the current options can be knocked out easily. WRT sunxi, I > posted moving two of them, and RGMII will happen as part of the general > move of all of the network drivers over. > > SATAPWR and MACPWR will take a little more thinking on, to figure out. > Do these values exist within the normal device tree in some way already > for example? Thanks! They do, but through intermediate regulators, and I'm not sure that's supported right now. An easier fix would be to simply move those options as strings to Kconfig, and call sunxi_name_to_gpio on those. Mylene started to work on it afaik, I added her in Cc. Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/3] defconfigs: dra7xx_hs_evm: Sync HS and non-HS defconfigs
Additions have been made to the non-HS defconfig without the same being made to the HS defconfig, sync them. Signed-off-by: Andrew F. Davis --- configs/dra7xx_hs_evm_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index 244940cd6c..0768ce51cc 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -9,6 +9,7 @@ CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x0200 CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c0 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y +CONFIG_ARMV7_LPAE=y CONFIG_SPL_STACK_R_ADDR=0x8200 CONFIG_DEFAULT_DEVICE_TREE="dra7-evm" CONFIG_FIT=y -- 2.11.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Makefile: print warning if CONFIG_SYS_EXTRA_OPTIONS is used
On Wed, Feb 22, 2017 at 11:53:05AM +0900, Masahiro Yamada wrote: > 2017-02-22 8:16 GMT+09:00 Maxime Ripard : > > On Sat, Feb 18, 2017 at 03:24:53PM +0900, Masahiro Yamada wrote: > >> The prompt of this option is marked "DEPRECATED" in capital letters, > >> and its help clearly says: > >> This option was prepared for the smooth migration from the old > >> configuration to Kconfig. Since this option will be removed sometime, > >> new boards should not use this option. > >> > >> However, we have had almost no progress on this. In fact, this > >> option is often abused for fresh porting, and more and more new > >> defconfigs with it are coming in (for example, SUNXI boards). > > > > That's not entirely true. We've added more defconfig, but with the > > same set of options we've always had, and are shared by everyone > > (CONS_INDEX, RGMII). > > > > So this patch, in effect, gives the signal that it's better to have a > > proliferation of board-specific headers in include/configs, over using > > SYS_EXTRA until most of the generic functions are merged? > > No. > > I am saying to add > CONFIG_CONS_INDEX=2 > CONFIG_RGMII=y > > instead of > > CONFIG_SYS_EXTRA_OPTIONS=CONS_INDEX=2,RGMII" > > Why proliferation of board-specific headers? Because of all the other platforms that would need to be migrated in the process. If what you suggest is just to remove all the defconfig that have that kind of option, I'll just move to what everyone else does: have it in my header. Because that's just the path of least resistance. But that just seems counter-productive. Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 6/6] sun50i: dts: update DTS to avoid warnings
> On 23 Feb 2017, at 00:20, Maxime Ripard
> wrote:
>
> On Wed, Feb 22, 2017 at 09:47:32PM +0100, Philipp Tomsich wrote:
>> +<<< HEAD
>> allwinner,drive = ;
>> allwinner,pull = ;
>> +===
>> +drive-strength = < 30 >;
>> +bias-pull-up;
>> };
>>
>> -i2c0_pins: i2c0_pins {
>> +mmc2_8bit_pins: mmc2-8bit {
>> +allwinner,pins = "PC5", "PC6", "PC8",
>> + "PC9", "PC10", "PC11",
>> + "PC12", "PC13", "PC14",
>> + "PC15", "PC16";
>> +allwinner,function = "mmc2";
>> +drive-strength = < 30 >;
>> +bias-pull-up;
>> +>>> 20221b3... [f] dts warnings
>
> Hmmm, are you sure about those ? :)
I can’t believe this slipped through. I think I need more sleep.
At least the patch-format wasn’t such a mess this time around…
Cheers,
Philipp.
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Re: [U-Boot] [PATCH v2 4/6] defconfig: lynx: enable CONFIG_DM_ALLOW_MULTIPLE_DRIVERS
On Wed, Feb 22, 2017 at 09:47:30PM +0100, Philipp Tomsich wrote: > Now that we have the new functionality to allow multiple drivers to > bind for a single node, we want to enable it for the A64-uQ7. > > Signed-off-by: Philipp Tomsich > --- > configs/lynx_defconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/configs/lynx_defconfig b/configs/lynx_defconfig > index 7b773f1..0fba279 100644 > --- a/configs/lynx_defconfig > +++ b/configs/lynx_defconfig > @@ -2,6 +2,7 @@ CONFIG_ARM=y > CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y > CONFIG_ARCH_SUNXI=y > CONFIG_MACH_SUN50I=y > +CONFIG_DM_ALLOW_MULTIPLE_DRIVERS=y I guess it would be better to just put the default value in Kconfig as MACH_SUN50I or even ARCH_SUNXI to enable it for all the boards Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] defconfigs: am43xx_hs_evm: Sync HS and non-HS defconfigs
Additions have been made to the non-HS defconfig without the same being made to the HS defconfig, sync them. Signed-off-by: Andrew F. Davis --- configs/am43xx_hs_evm_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig index 8bb1b3535a..939df44fae 100644 --- a/configs/am43xx_hs_evm_defconfig +++ b/configs/am43xx_hs_evm_defconfig @@ -10,7 +10,7 @@ CONFIG_FIT=y CONFIG_FIT_IMAGE_POST_PROCESS=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y -CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1, NAND" +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,NAND" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y @@ -41,6 +41,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ISO_PARTITION=y CONFIG_OF_CONTROL=y +CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm" CONFIG_DM=y # CONFIG_BLK is not set CONFIG_DFU_MMC=y @@ -53,6 +54,7 @@ CONFIG_DM_MMC=y CONFIG_MMC_OMAP_HS=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_DM_ETH=y CONFIG_DM_SERIAL=y -- 2.11.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/3] defconfigs: am57xx_hs_evm: Sync HS and non-HS defconfigs
Additions have been made to the non-HS defconfig without the same being made to the HS defconfig, sync them. Signed-off-by: Andrew F. Davis --- configs/am57xx_hs_evm_defconfig | 7 +++ 1 file changed, 7 insertions(+) diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig index 7e84ccddf3..b5f54c3a13 100644 --- a/configs/am57xx_hs_evm_defconfig +++ b/configs/am57xx_hs_evm_defconfig @@ -8,6 +8,7 @@ CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x0200 CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c0 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y +CONFIG_ARMV7_LPAE=y CONFIG_SPL_STACK_R_ADDR=0x8200 CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15" CONFIG_FIT=y @@ -48,6 +49,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y @@ -55,6 +57,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ISO_PARTITION=y CONFIG_OF_CONTROL=y +CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am572x-idk am571x-idk" CONFIG_DM=y # CONFIG_BLK is not set CONFIG_DFU_MMC=y @@ -68,6 +71,10 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_PALMAS=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PALMAS=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y -- 2.11.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/3] Sync HS and non-HS defconfigs
Hi all, The HS and non-HS versions of TI boards are very similar but currently need separate defconfigs, these should be almost identical outside of the security additions. When they track out of sync it is normally not a problem, but a couple of these changes are now important and so lets sync them up. Thanks, Andrew Andrew F. Davis (3): defconfigs: am43xx_hs_evm: Sync HS and non-HS defconfigs defconfigs: am57xx_hs_evm: Sync HS and non-HS defconfigs defconfigs: dra7xx_hs_evm: Sync HS and non-HS defconfigs configs/am43xx_hs_evm_defconfig | 4 +++- configs/am57xx_hs_evm_defconfig | 7 +++ configs/dra7xx_hs_evm_defconfig | 1 + 3 files changed, 11 insertions(+), 1 deletion(-) -- 2.11.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 6/6] sun50i: dts: update DTS to avoid warnings
On Wed, Feb 22, 2017 at 09:47:32PM +0100, Philipp Tomsich wrote:
> +<<< HEAD
> allwinner,drive = ;
> allwinner,pull = ;
> +===
> + drive-strength = < 30 >;
> + bias-pull-up;
> };
>
> - i2c0_pins: i2c0_pins {
> + mmc2_8bit_pins: mmc2-8bit {
> + allwinner,pins = "PC5", "PC6", "PC8",
> + "PC9", "PC10", "PC11",
> + "PC12", "PC13", "PC14",
> + "PC15", "PC16";
> + allwinner,function = "mmc2";
> + drive-strength = < 30 >;
> + bias-pull-up;
> +>>> 20221b3... [f] dts warnings
Hmmm, are you sure about those ? :)
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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Re: [U-Boot] [PATCH v2 1/6] sunxi: add pinctrl (UCLASS_PINCTRL) support for sunxi
On Wed, Feb 22, 2017 at 09:47:27PM +0100, Philipp Tomsich wrote:
> This change adds a full device-model pinctrl driver for sunxi (tested with
> sun50iw1p1) based on the support available in Linux.
>
> Details are:
> * implements a driver for pinctrl devices and assigns sun50i-a64-pinctrl
>and sun50i-a64-r-pinctrl to it
> * dynamically creates the driver_data for a sunxi_gpio (see sunxi_gpio.c)
>driver and binds it to the same device-tree node
> * lifts and reuses the pinctrl-sunxi.h and pinctrl-sun50i-a64.c files from
>Linux (thanks to Maxime and Andre) and adds a pinctrl-sun50i-a64-r.c (to
>be picked up for inclusion into Linux again)
>
> Signed-off-by: Philipp Tomsich
> ---
> arch/arm/include/asm/arch-sunxi/gpio-internal.h| 19 +
> .../pinctrl/allwinner,pinctrl.txt | 65 +++
> drivers/gpio/sunxi_gpio.c | 15 +-
> drivers/pinctrl/Kconfig| 10 +
> drivers/pinctrl/Makefile | 2 +
> drivers/pinctrl/sunxi/Makefile | 10 +
> drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c | 92
> drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c | 577
> +
> drivers/pinctrl/sunxi/pinctrl-sunxi.c | 317 +++
> drivers/pinctrl/sunxi/pinctrl-sunxi.h | 311 +++
> 10 files changed, 1411 insertions(+), 7 deletions(-)
> create mode 100644 arch/arm/include/asm/arch-sunxi/gpio-internal.h
> create mode 100644 doc/device-tree-bindings/pinctrl/allwinner,pinctrl.txt
> create mode 100644 drivers/pinctrl/sunxi/Makefile
> create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
> create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c
> create mode 100644 drivers/pinctrl/sunxi/pinctrl-sunxi.c
> create mode 100644 drivers/pinctrl/sunxi/pinctrl-sunxi.h
>
> diff --git a/arch/arm/include/asm/arch-sunxi/gpio-internal.h
> b/arch/arm/include/asm/arch-sunxi/gpio-internal.h
> new file mode 100644
> index 000..4dcdd34
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-sunxi/gpio-internal.h
> @@ -0,0 +1,19 @@
> +/*
> + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +
> +#ifndef _SUNXI_GPIO_INTERNAL_H
> +#define _SUNXI_GPIO_INTERNAL_H
> +
> +/* This data structure is shared between the sunxi_gpio driver and
> + * the sunxi_pinctrl driver.
> + */
> +struct sunxi_gpio_soc_data {
> + int start;
> + int no_banks;
> +};
> +
> +#endif
> diff --git a/doc/device-tree-bindings/pinctrl/allwinner,pinctrl.txt
> b/doc/device-tree-bindings/pinctrl/allwinner,pinctrl.txt
> new file mode 100644
> index 000..946831f
> --- /dev/null
> +++ b/doc/device-tree-bindings/pinctrl/allwinner,pinctrl.txt
> @@ -0,0 +1,65 @@
> +* Allwinner Pinmux Controller
> +
> +Allwinner integrates multiple banks (of 32 pins each) of pin-muxing,
> +GPIO functionality and (optional) external interrupt functionality
> +into a single controller.
> +
> +For each configurable pad (certain driver-cells, such as the IO from
> +integrated USB PHYs or DRAM, have a fixed function and can not be
> +configured), the muxing options (input, output or one of the several
> +functions) can be selected.
> +
> +Properties for the pinctrl node:
> + - compatible: should be "allwinner,sun50i-pinctrl"
There's a typo here, the compatible is sun50i-a64-pinctrl
> + - reg: address and length of the register set for the device.
> + - interrupts: interrupt for the device
> + - clocks: A phandle to the reference clock for this device
(and ideally, this would take three clocks: the bus gate + the two
oscillators).
> +
> +Properties for the pinconfig sub-nodes:
> + - allwinner,pins: a list of pins (e.g. "PH2", "PH3") to configure
> + - allwinner,function: the name of pinmux function (e.g. "mmc2")
allwinner,pins and allwinner,function are also deprecated in favour of
pins and function.
> + - drive-strength: a drive-stength setting of 10, 20, 30 or 40 mA
> + - bias-pull-up
> + - bias-pull-down
> + - bias-disable (default)
The default is not bias-disable, but to keep the current configuration
> +
> +Deprecated properties for the pinconfig sub-nodes:
> + - allwinner,drive: one of , ,
> + or
> + - allwinner,pull: one of ,
> +or
> +
> +Example:
> +
> + pio: pinctrl@1c20800 {
> + compatible = "allwinner,sun50i-a64-pinctrl";
> + reg = <0x01c20800 0x400>;
> +
> + interrupts = ,
> + ,
> + ;
> + clocks = <&bus_gates 69>;
> +
> + gpio-controller;
> + #gpio-cells = <3>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + uart0_pins_a: uart0_pins_a {
> + allwinner,pins = "PB8", "PB9";
> +
Re: [U-Boot] [PATCH] spi: cadence_qspi_apb: Add trigger-base DT bindings from Linux
On 02/22/2017 06:37 PM, Rush, Jason A. wrote:
> Marek Vasut wrote:
>> On 02/21/2017 05:50 PM, Rush, Jason A. wrote:
>>> The socfpga arch uses a different value for the indaddrtrig reg than
>>> the ahbbase address. Adopting the Linux DT bindings separates the
>>> ahbbase and trigger-base addresses, allowing the trigger-base to be+
>>> set correctly on the socfpga arch.
>>>
>>> Tested on Terasic SoCkit dev board (Altera Cyclone V)
>>>
>>> Signed-off-by: Jason A. Rush
>>> ---
>>> arch/arm/dts/socfpga.dtsi | 1 +
>>> drivers/spi/cadence_qspi.c | 2 ++
>>> drivers/spi/cadence_qspi.h | 1 +
>>> drivers/spi/cadence_qspi_apb.c | 4 ++--
>>> 4 files changed, 6 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
>>> index 8588221e57..2aff0c2419 100644
>>> --- a/arch/arm/dts/socfpga.dtsi
>>> +++ b/arch/arm/dts/socfpga.dtsi
>>> @@ -644,6 +644,7 @@
>>> clocks = <&qspi_clk>;
>>> ext-decoder = <0>; /* external decoder */
>>> num-cs = <4>;
>>> + trigger-base = <0x>;
>>
>> Can you separate the DT patch from the driver patch ? Also, can you check
>> the other users of the CQSPI driver to see if they define the
>> trigger base ?
>>
>
> Yes, I will separate into two patches.
Thanks
> I default the trigger_base to the same value as the ahbbase if the
> trigger-base
> was not defined in the DT. That way, the driver code works as before for
> architectures that expect the trigger_base to equal the value of the ahbbase.
> (e.g. TI K2G SoC). I updated only the Altera SoC dtsi file since that
> architecture
> needs a different value for the trigger_base.
In fact, the Linux DT bindings have the following and no AHB base, so
please stick to that:
- cdns,trigger-address : 32-bit indirect AHB trigger address.
For details, see
Documentation/devicetree/bindings/mtd/cadence-quadspi.txt in Linux 4.8
or so and newer.
> Should I change this behavior to default the value to 0x0, and patch the 3
> dts/dtsi
> files that use the cadence driver to explicitly include the trigger-base?
Yeah, looks sensible.
>>
>>> fifo-depth = <128>;
>>> sram-size = <128>;
>>> bus-num = <2>;
>>> diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
>>> index 9a6e41f330..a18b331f6c 100644
>>> --- a/drivers/spi/cadence_qspi.c
>>> +++ b/drivers/spi/cadence_qspi.c
>>> @@ -296,6 +296,8 @@ static int cadence_spi_ofdata_to_platdata(struct
>>> udevice *bus)
>>>
>>> plat->regbase = (void *)data[0];
>>> plat->ahbbase = (void *)data[2];
>>> + plat->trigger_base = (void *)fdtdec_get_int(blob, node, "trigger-base",
>>> + (int)plat->ahbbase);
>>
>> Probably get u32 , but what about 64-bit systems ? Don't we have some
>> fdtdec_get.*addr ?
>
> You're right, this should be a u32. I don't think I should have made
> trigger_base
> a void* in the first place, but instead it should be a u32. Looking at the
> Linux
> kernel, which I just realized they call it trigger_address not trigger_base,
> it is just
> a 32-bit value that is written into a 32-bit wide register, not an iomem
> memory
> mapped pointer.
Ah right, the reg is 32bit . Is it possible that on aargh64, someone
will pass 64bit trigger base in ?
> What if I change it to a u32 and rename it to trigger_address (which I should
> have done the first time)? That would align us correctly with the Linux
> kernel.
See above /wrt the naming. void __iomem * works on both 32 and 64bit
systems, so I'd prefer to see that.
>>
>>> plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128);
>>>
>>> /* All other paramters are embedded in the child node */ diff --git
>>> a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index
>>> d1927a4003..394820f308 100644
>>> --- a/drivers/spi/cadence_qspi.h
>>> +++ b/drivers/spi/cadence_qspi.h
>>> @@ -18,6 +18,7 @@ struct cadence_spi_platdata {
>>> unsigned intmax_hz;
>>> void*regbase;
>>> void*ahbbase;
>>
>> Can you remove the AHB base ? I think it's no longer used.
>
> ahbbase is still used in cadence_qspi_apb.c, it's the register that the QSPI
> data
> is read from, so it's still needed.
Aaaah, and looking at the Linux bindings, there it comes from the reg
property. OK, so much for the bloody confusing naming. If you feel like
cleaning this up, separate patch is welcome, if not ... oh well.
>> Also, I think this should be void __iomem * here , also for regbase .
>>
>
> This is probably true, regbase and ahbbase should both be __iomem *, but
> that feels like a different clean-up patch. If you'd like me to, I could
> update
> both of these as part of this patch though.
Yeah, that'd be brilliant if you could clean this bit too. Thanks!
>>
>>> + void*trigger_base;
>>>
>>> u32 page_size;
>>> u3
Re: [U-Boot] [PATCH v1 2/2] sun8i: enable support for the Micrel KSZ9031 with SUN8I_EMAC
Maxime, > On 22 Feb 2017, at 20:00, Maxime Ripard > wrote: > > On Wed, Feb 22, 2017 at 03:45:41PM +0100, Dr. Philipp Tomsich wrote: >> Maxime, >> >>> On 21 Feb 2017, at 21:35, Dr. Philipp Tomsich >>> wrote: >>> >>> Maxime, >>> On 21 Feb 2017, at 20:56, Maxime Ripard wrote: On Fri, Feb 17, 2017 at 06:47:55PM +0100, Philipp Tomsich wrote: > #ifdef CONFIG_SUN8I_EMAC > #define CONFIG_PHY_GIGE /* GMAC can use gigabit PHY > */ > +#define CONFIG_PHY_MICREL > +#define CONFIG_PHY_MICREL_KSZ9031 /* used on A64-uQ7 > */ > #endif Same thing here, and that way you could enable it only on the board defconfig. >> >> I’d really like to keep this for all SUN8I_EMAC configurations, as we >> need the PHY support to initialise the pad timing parameters from the >> DTS. If these are not initialised, then RGMII (i.e. Gigabit) will not work. > > I'm not really discussing whether it is needed or not. The discussion is moot anyway, as I had this change already committed for v2 this afternoon. >> As we are moving towards a ‘universal’ U-Boot binary for sun50i and >> try to put all board specific info into the DTS, I’d like to keep this in >> sunxi-common.h to ensure that nobody rebuild without it and then >> has issues on our boards. > > I'm not buying the whole universal U-Boot binary thing, but that's > really not related to the discussion. sunxi-common.h should be > reduced, not expanded to cover new stuff, in favor of Kconfig. I’ve just put v2 onto the list and only touch the SUN8I_EMAC in v2. The same should be done for SUNXI_GMAC and we’ll cycle back to it, once the DM stuff is done (so we can update our A31 support to it and release any pending changes left over from the A31-uQ7). Regards, Philipp. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] net: Kconfig:make PHY_GIGE and individual Micrel PHYs selectable
This changeset moves two configuration options into Kconfig: * PHY_GIGE, indicates that a controller (with an appropriate PHY) is Gigabit capable and enables extra support in the miiutil for parsing the status of Gigabit PHYs * individual configuration options for MICREL_KSZ9021 and MICREL_KSZ9031 GbE PHYs, which previously had to enabled through a board-specific config file Signed-off-by: Philipp Tomsich --- drivers/net/Kconfig | 7 +++ drivers/net/phy/Kconfig | 10 ++ 2 files changed, 17 insertions(+) diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 078d5a8..845df09 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -22,6 +22,12 @@ menuconfig NETDEVICES if NETDEVICES +config PHY_GIGE +bool + help + Enables support for parsing the status output and + configuring GbE PHYs (e.g. via miiphyutil.c) + config AG7XXX bool "Atheros AG7xxx Ethernet MAC support" depends on DM_ETH && ARCH_ATH79 @@ -165,6 +171,7 @@ config SUN8I_EMAC bool "Allwinner Sun8i Ethernet MAC support" depends on DM_ETH select PHYLIB + select PHY_GIGE help This driver supports the Allwinner based SUN8I/SUN50I Ethernet MAC. It can be found in H3/A64/A83T based SoCs and compatible with both diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 1d514e9..0941383 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -45,6 +45,16 @@ config PHY_MARVELL config PHY_MICREL bool "Micrel Ethernet PHYs support" +if PHY_MICREL + +config PHY_MICREL_KSZ9021 +bool "Micrel KSZ9021 family support" + +config PHY_MICREL_KSZ9031 +bool "Micrel KSZ9031 family support" + +endif # PHY_MICREL + config PHY_MSCC bool "Microsemi Corp Ethernet PHYs support" -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-video/master
On Wed, Feb 22, 2017 at 09:56:43PM +0100, Anatolij Gustschin wrote: > Hi Tom, > > The following changes since commit 4d6f9e0d21bb223ace577030ef69b8fbbd98f678: > > Merge git://git.denx.de/u-boot-x86 (2017-02-22 10:27:37 -0500) > > are available in the git repository at: > > git://git.denx.de/u-boot-video.git master > > for you to fetch changes up to b24cf8540a85a9bf97975aadd6a7542f166c78a3: > > video: mxsfb: Fix reset hang when videomode variable is not present > (2017-02-22 21:47:59 +0100) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] net: Kconfig: select PHY_GIGE for SUN8I_EMAC
This now moves the PHY_GIGE, PHY_MICREL_KSZ9021 and PHY_MICREL_KSZ9031 into Kconfig, so we can select them from our defconfig. For SUN8I, we select PHY_GIGE automatically. Signed-off-by: Philipp Tomsich Philipp Tomsich (1): net: Kconfig:make PHY_GIGE and individual Micrel PHYs selectable drivers/net/Kconfig | 7 +++ drivers/net/phy/Kconfig | 10 ++ 2 files changed, 17 insertions(+) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] net: Kconfig: select PHY_GIGE for SUN8I_EMAC
This now moves the PHY_GIGE, PHY_MICREL_KSZ9021 and PHY_MICREL_KSZ9031 into Kconfig, so we can select them from our defconfig. For SUN8I, we select PHY_GIGE automatically. The same goes for SUNXI_GMAC. Philipp Tomsich (1): net: Kconfig:make PHY_GIGE and individual Micrel PHYs selectable drivers/net/Kconfig | 7 +++ drivers/net/phy/Kconfig | 10 ++ 2 files changed, 17 insertions(+) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Please pull u-boot-video/master
Hi Tom, The following changes since commit 4d6f9e0d21bb223ace577030ef69b8fbbd98f678: Merge git://git.denx.de/u-boot-x86 (2017-02-22 10:27:37 -0500) are available in the git repository at: git://git.denx.de/u-boot-video.git master for you to fetch changes up to b24cf8540a85a9bf97975aadd6a7542f166c78a3: video: mxsfb: Fix reset hang when videomode variable is not present (2017-02-22 21:47:59 +0100) Fabio Estevam (1): video: mxsfb: Fix reset hang when videomode variable is not present drivers/video/mxsfb.c | 3 +++ 1 file changed, 3 insertions(+) Please pull. Thanks! Anatolij ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 0/6] sunxi: DM pinctrl implementation
Here's v2, which incorporates the feedback from Maxime and ChenYu into a more complete and less intrusive version. The most elegant solution to our problem with pinctrl & gpio, which will also work equally well for ccu and reset, is to have the device model bind multiple drivers to a single node: for this reason, one patch of the series touches the device-model core. To provide a bit more context, I've also include the change showing how this is enabled in our defconfig (i.e. a diff against our defconfig, even though the defconfig has not been submitted yet). Changes in v2: * two variants to reuse the sunxi_gpio layer: - create a matching soc_data for sunxi_gpio and rebind - have the device-model do this for us * got rid of the gpio-banks and gpiobridge drivers Philipp Tomsich (6): sunxi: add pinctrl (UCLASS_PINCTRL) support for sunxi dm: core: Allow multiple drivers to bind for a single node sunxi: CONFIG_DM_ALLOW_MULTIPLE_DRIVERS for gpio/pinctrl binding defconfig: lynx: enable CONFIG_DM_ALLOW_MULTIPLE_DRIVERS sun50i: dts: add r_pio node and pinconfig entries into r_pio and pio sun50i: dts: update DTS to avoid warnings arch/arm/dts/sun50i-a64.dtsi | 62 ++- arch/arm/include/asm/arch-sunxi/gpio-internal.h| 19 + configs/lynx_defconfig | 1 + .../pinctrl/allwinner,pinctrl.txt | 65 +++ drivers/core/Kconfig | 14 + drivers/core/lists.c | 12 +- drivers/gpio/sunxi_gpio.c | 15 +- drivers/pinctrl/Kconfig| 10 + drivers/pinctrl/Makefile | 2 + drivers/pinctrl/sunxi/Makefile | 10 + drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c | 92 drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c | 577 + drivers/pinctrl/sunxi/pinctrl-sunxi.c | 321 drivers/pinctrl/sunxi/pinctrl-sunxi.h | 311 +++ 14 files changed, 1479 insertions(+), 32 deletions(-) create mode 100644 arch/arm/include/asm/arch-sunxi/gpio-internal.h create mode 100644 doc/device-tree-bindings/pinctrl/allwinner,pinctrl.txt create mode 100644 drivers/pinctrl/sunxi/Makefile create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c create mode 100644 drivers/pinctrl/sunxi/pinctrl-sunxi.c create mode 100644 drivers/pinctrl/sunxi/pinctrl-sunxi.h -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/6] sunxi: add pinctrl (UCLASS_PINCTRL) support for sunxi
This change adds a full device-model pinctrl driver for sunxi (tested with
sun50iw1p1) based on the support available in Linux.
Details are:
* implements a driver for pinctrl devices and assigns sun50i-a64-pinctrl
and sun50i-a64-r-pinctrl to it
* dynamically creates the driver_data for a sunxi_gpio (see sunxi_gpio.c)
driver and binds it to the same device-tree node
* lifts and reuses the pinctrl-sunxi.h and pinctrl-sun50i-a64.c files from
Linux (thanks to Maxime and Andre) and adds a pinctrl-sun50i-a64-r.c (to
be picked up for inclusion into Linux again)
Signed-off-by: Philipp Tomsich
---
arch/arm/include/asm/arch-sunxi/gpio-internal.h| 19 +
.../pinctrl/allwinner,pinctrl.txt | 65 +++
drivers/gpio/sunxi_gpio.c | 15 +-
drivers/pinctrl/Kconfig| 10 +
drivers/pinctrl/Makefile | 2 +
drivers/pinctrl/sunxi/Makefile | 10 +
drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c | 92
drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c | 577 +
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 317 +++
drivers/pinctrl/sunxi/pinctrl-sunxi.h | 311 +++
10 files changed, 1411 insertions(+), 7 deletions(-)
create mode 100644 arch/arm/include/asm/arch-sunxi/gpio-internal.h
create mode 100644 doc/device-tree-bindings/pinctrl/allwinner,pinctrl.txt
create mode 100644 drivers/pinctrl/sunxi/Makefile
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sunxi.c
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sunxi.h
diff --git a/arch/arm/include/asm/arch-sunxi/gpio-internal.h
b/arch/arm/include/asm/arch-sunxi/gpio-internal.h
new file mode 100644
index 000..4dcdd34
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/gpio-internal.h
@@ -0,0 +1,19 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+
+#ifndef _SUNXI_GPIO_INTERNAL_H
+#define _SUNXI_GPIO_INTERNAL_H
+
+/* This data structure is shared between the sunxi_gpio driver and
+ * the sunxi_pinctrl driver.
+ */
+struct sunxi_gpio_soc_data {
+ int start;
+ int no_banks;
+};
+
+#endif
diff --git a/doc/device-tree-bindings/pinctrl/allwinner,pinctrl.txt
b/doc/device-tree-bindings/pinctrl/allwinner,pinctrl.txt
new file mode 100644
index 000..946831f
--- /dev/null
+++ b/doc/device-tree-bindings/pinctrl/allwinner,pinctrl.txt
@@ -0,0 +1,65 @@
+* Allwinner Pinmux Controller
+
+Allwinner integrates multiple banks (of 32 pins each) of pin-muxing,
+GPIO functionality and (optional) external interrupt functionality
+into a single controller.
+
+For each configurable pad (certain driver-cells, such as the IO from
+integrated USB PHYs or DRAM, have a fixed function and can not be
+configured), the muxing options (input, output or one of the several
+functions) can be selected.
+
+Properties for the pinctrl node:
+ - compatible: should be "allwinner,sun50i-pinctrl"
+ - reg: address and length of the register set for the device.
+ - interrupts: interrupt for the device
+ - clocks: A phandle to the reference clock for this device
+
+Properties for the pinconfig sub-nodes:
+ - allwinner,pins: a list of pins (e.g. "PH2", "PH3") to configure
+ - allwinner,function: the name of pinmux function (e.g. "mmc2")
+ - drive-strength: a drive-stength setting of 10, 20, 30 or 40 mA
+ - bias-pull-up
+ - bias-pull-down
+ - bias-disable (default)
+
+Deprecated properties for the pinconfig sub-nodes:
+ - allwinner,drive: one of , ,
+ or
+ - allwinner,pull: one of ,
+ or
+
+Example:
+
+ pio: pinctrl@1c20800 {
+ compatible = "allwinner,sun50i-a64-pinctrl";
+ reg = <0x01c20800 0x400>;
+
+ interrupts = ,
+,
+;
+ clocks = <&bus_gates 69>;
+
+ gpio-controller;
+ #gpio-cells = <3>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0_pins_a: uart0_pins_a {
+ allwinner,pins = "PB8", "PB9";
+ allwinner,function = "uart0";
+ allwinner,drive = ;
+ allwinner,pull = ;
+ };
+
+ uart0_pins_b: uart0_pins_b {
+ allwinner,pins = "PF2", "PF3";
+ allwinner,function = "uart0";
+ allwinner,drive = ;
+ allwinner,pull = ;
+ };
+ };
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index 2b7bc7f..fd0c1ac 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_g
[U-Boot] [PATCH v2 2/6] dm: core: Allow multiple drivers to bind for a single node
Currently, driver binding stops once it encounters the first
compatible driver that doesn't refuse to bind. However, there are
cases where a single node will need to be handled by multiple driver
classes. For those cases we provide a configurable option to continue
to bind after the first driver has been found.
The first use cases for this are from the DM conversion of the sunxi
(Allwinner) architecture:
* pinctrl (UCLASS_PINCTRL) and gpio (UCLASS_GPIO) drivers need to
bind against a single node
* clock (UCLASS_CLK) and reset (UCLASS_RESET) drivers also need to
bind against a single node
Signed-off-by: Philipp Tomsich
---
drivers/core/Kconfig | 14 ++
drivers/core/lists.c | 12 +++-
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index 8749561..913101c 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -31,6 +31,20 @@ config DM_WARN
This will cause dm_warn() to be compiled out - it will do nothing
when called.
+config DM_ALLOW_MULTIPLE_DRIVERS
+bool "Allow multiple drivers to bind for one node"
+ depends on DM
+ default n
+ help
+ The driver model in U-Boot originally did not allow multiple
+ drivers to bind for a single device node.
+
+ If enabled, multiple drivers can now bind for a single node
+ by using the same compatible string for matching: lists_bind_fdt()
+ will assume that binding multiple drivers is desirable, if the
+ caller does not request the pointer to the udevice structure to
+ be returned (i.e. if devp is NULL).
+
config DM_DEVICE_REMOVE
bool "Support device removal"
depends on DM
diff --git a/drivers/core/lists.c b/drivers/core/lists.c
index 23b6ba7..52efe69 100644
--- a/drivers/core/lists.c
+++ b/drivers/core/lists.c
@@ -166,7 +166,11 @@ int lists_bind_fdt(struct udevice *parent, const void
*blob, int offset,
dm_dbg(" - attempt to match compatible string '%s'\n",
compat);
- for (entry = driver; entry != driver + n_ents; entry++) {
+ entry = driver;
+#if defined(CONFIG_DM_ALLOW_MULTIPLE_DRIVERS)
+ allow_more_matches:
+#endif
+ for (; entry != driver + n_ents; entry++) {
ret = driver_check_compatible(entry->of_match, &id,
compat);
if (!ret)
@@ -190,6 +194,12 @@ int lists_bind_fdt(struct udevice *parent, const void
*blob, int offset,
found = true;
if (devp)
*devp = dev;
+#if defined(CONFIG_DM_ALLOW_MULTIPLE_DRIVERS)
+ else {
+ entry++;
+ goto allow_more_matches;
+ }
+#endif
}
break;
}
--
1.9.1
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[U-Boot] [PATCH v2 6/6] sun50i: dts: update DTS to avoid warnings
Nodes that don't contain a reg-entry should not have an @xxx name
attached. To silence the dt-compiler warnings, we update the DTS.
Signed-off-by: Philipp Tomsich
---
arch/arm/dts/sun50i-a64.dtsi | 57
1 file changed, 36 insertions(+), 21 deletions(-)
diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi
index 54b68e0..4911d6a 100644
--- a/arch/arm/dts/sun50i-a64.dtsi
+++ b/arch/arm/dts/sun50i-a64.dtsi
@@ -88,7 +88,7 @@
method = "smc";
};
- memory {
+ memory: memory@4000 {
device_type = "memory";
reg = <0x4000 0>;
};
@@ -378,84 +378,84 @@
interrupt-controller;
#interrupt-cells = <3>;
- uart0_pins_a: uart0_pins_a {
+ uart0_pins_a: uart0-pins-a {
allwinner,pins = "PB8", "PB9";
allwinner,function = "uart0";
allwinner,drive = ;
allwinner,pull = ;
};
- uart0_pins_b: uart0@1 {
+ uart0_pins_b: uart0-pins-b {
allwinner,pins = "PF2", "PF3";
allwinner,function = "uart0";
allwinner,drive = ;
allwinner,pull = ;
};
- uart1_2pins: uart1_2@0 {
+ uart1_2pins: uart1-2pins {
allwinner,pins = "PG6", "PG7";
allwinner,function = "uart1";
allwinner,drive = ;
allwinner,pull = ;
};
- uart1_4pins: uart1_4@0 {
+ uart1_4pins: uart1-4pins {
allwinner,pins = "PG6", "PG7", "PG8", "PG9";
allwinner,function = "uart1";
allwinner,drive = ;
allwinner,pull = ;
};
- uart2_2pins: uart2_2@0 {
+ uart2_2pins: uart2-2pins {
allwinner,pins = "PB0", "PB1";
allwinner,function = "uart2";
allwinner,drive = ;
allwinner,pull = ;
};
- uart2_4pins: uart2_4@0 {
+ uart2_4pins: uart2-4pins {
allwinner,pins = "PB0", "PB1", "PB2", "PB3";
allwinner,function = "uart2";
allwinner,drive = ;
allwinner,pull = ;
};
- uart3_pins_a: uart3@0 {
+ uart3_pins_a: uart3-pins-a {
allwinner,pins = "PD0", "PD1";
allwinner,function = "uart3";
allwinner,drive = ;
allwinner,pull = ;
};
- uart3_2pins_b: uart3_2@1 {
+ uart3_2pins_b: uart3-2pins-b {
allwinner,pins = "PH4", "PH5";
allwinner,function = "uart3";
allwinner,drive = ;
allwinner,pull = ;
};
- uart3_4pins_b: uart3_4@1 {
+ uart3_4pins_b: uart3-4pins-b {
allwinner,pins = "PH4", "PH5", "PH6", "PH7";
allwinner,function = "uart3";
allwinner,drive = ;
allwinner,pull = ;
};
- uart4_2pins: uart4_2@0 {
+ uart4_2pins: uart4-2pins {
allwinner,pins = "PD2", "PD3";
allwinner,function = "uart4";
allwinner,drive = ;
allwinner,pull = ;
};
- uart4_4pins: uart4_4@0 {
+ uart4_4pins: uart4-4pins {
allwinner,pins = "PD2", "PD3", "PD4", "PD5";
allwinner,function = "uart4";
allwinner,drive = ;
allwinner,pull = ;
};
- mmc0_pins: mmc0@0 {
+ mmc0_pins: mmc0-pins {
allwinner,pins = "PF0", "PF1", "PF2", "PF3",
[U-Boot] [PATCH v2 4/6] defconfig: lynx: enable CONFIG_DM_ALLOW_MULTIPLE_DRIVERS
Now that we have the new functionality to allow multiple drivers to bind for a single node, we want to enable it for the A64-uQ7. Signed-off-by: Philipp Tomsich --- configs/lynx_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/lynx_defconfig b/configs/lynx_defconfig index 7b773f1..0fba279 100644 --- a/configs/lynx_defconfig +++ b/configs/lynx_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN50I=y +CONFIG_DM_ALLOW_MULTIPLE_DRIVERS=y CONFIG_PINCTRL=y CONFIG_SUNXI_PINCTRL=y CONFIG_CLK=y -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 3/6] sunxi: CONFIG_DM_ALLOW_MULTIPLE_DRIVERS for gpio/pinctrl binding
Our gpio and pinctrl driver need to be bound against the same
node. While this can be done by hand (i.e. explicitly looking up the
driver, creating the driver-data and binding the device), it is much
easier done when the new option for the binding of multiple drivers
against a single node is configured.
Signed-off-by: Philipp Tomsich
---
drivers/gpio/sunxi_gpio.c | 4 ++--
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 8 ++--
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index fd0c1ac..cbec1b9 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -349,7 +349,7 @@ static const struct udevice_id sunxi_gpio_ids[] = {
ID("allwinner,sun8i-a83t-pinctrl", a_all),
ID("allwinner,sun8i-h3-pinctrl",a_all),
ID("allwinner,sun9i-a80-pinctrl", a_all),
-#if !defined(CONFIG_SUNXI_PINCTRL)
+#if !defined(CONFIG_SUNXI_PINCTRL) || defined(CONFIG_DM_ALLOW_MULTIPLE_DRIVERS)
/* This is not strictly correct for the A64, as it is missing
* bank 'A'. Yet, the register layout in the pinctrl block is
* backward compatible and any accesses to the registers that
@@ -362,7 +362,7 @@ static const struct udevice_id sunxi_gpio_ids[] = {
ID("allwinner,sun8i-a83t-r-pinctrl",l_1),
ID("allwinner,sun8i-h3-r-pinctrl", l_1),
ID("allwinner,sun9i-a80-r-pinctrl", l_3),
-#if !defined(CONFIG_SUNXI_PINCTRL)
+#if !defined(CONFIG_SUNXI_PINCTRL) || defined(CONFIG_DM_ALLOW_MULTIPLE_DRIVERS)
ID("allwinner,sun50i-a64-r-pinctrl",l_1),
#endif
{ }
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 4640cee..445707e 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -14,7 +14,9 @@
#include
#include
#include
+#if defined(CONFIG_DM_GPIO) && !defined(CONFIG_DM_ALLOW_MULTIPLE_DRIVERS)
#include
+#endif
#include
#include
#include
@@ -27,7 +29,7 @@ DECLARE_GLOBAL_DATA_PTR;
struct sunxi_pctrl_priv {
void *base;
-#if defined(CONFIG_DM_GPIO)
+#if defined(CONFIG_DM_GPIO) && !defined(CONFIG_DM_ALLOW_MULTIPLE_DRIVERS)
struct sunxi_gpio_soc_data gpio_soc_data;
struct udevice *gpio_dev;
#endif
@@ -217,6 +219,7 @@ static int sunxi_pctrl_set_state(struct udevice *dev,
struct udevice *config)
return 0;
}
+#if defined(CONFIG_DM_GPIO) && !defined(CONFIG_DM_ALLOW_MULTIPLE_DRIVERS)
static inline void soc_data_from_desc(const struct sunxi_pinctrl_desc *data,
struct sunxi_gpio_soc_data *soc_data)
{
@@ -236,10 +239,11 @@ static inline void soc_data_from_desc(const struct
sunxi_pinctrl_desc *data,
soc_data->start = low;
soc_data->no_banks = high - low + 1;
}
+#endif
static int sunxi_pctrl_bind_gpio(struct udevice *dev)
{
-#if defined(CONFIG_DM_GPIO)
+#if defined(CONFIG_DM_GPIO) && !defined(CONFIG_DM_ALLOW_MULTIPLE_DRIVERS)
struct sunxi_pctrl_priv *priv = dev_get_priv(dev);
const struct sunxi_pinctrl_desc *data =
(struct sunxi_pinctrl_desc *)dev_get_driver_data(dev);
--
1.9.1
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[U-Boot] [PATCH v2 5/6] sun50i: dts: add r_pio node and pinconfig entries into r_pio and pio
To sync up with use of a pinctrl-driver, this updates the DTS.
Signed-off-by: Philipp Tomsich
---
arch/arm/dts/sun50i-a64.dtsi | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi
index 24406d0..54b68e0 100644
--- a/arch/arm/dts/sun50i-a64.dtsi
+++ b/arch/arm/dts/sun50i-a64.dtsi
@@ -376,9 +376,9 @@
gpio-controller;
#gpio-cells = <3>;
interrupt-controller;
- #interrupt-cells = <2>;
+ #interrupt-cells = <3>;
- uart0_pins_a: uart0@0 {
+ uart0_pins_a: uart0_pins_a {
allwinner,pins = "PB8", "PB9";
allwinner,function = "uart0";
allwinner,drive = ;
@@ -532,10 +532,9 @@
reg = <0x01f02c00 0x400>;
interrupts = ;
gpio-controller;
+ #gpio-cells = <3>;
interrupt-controller;
#interrupt-cells = <3>;
- #size-cells = <0>;
- #gpio-cells = <3>;
};
ahb_rst: reset@1c202c0 {
--
1.9.1
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Re: [U-Boot] Please pull u-boot-x86
On Tue, Feb 21, 2017 at 03:21:47PM +0800, Bin Meng wrote: > Hi Tom, > > The following changes since commit 66c246cce7c66019a93ff7105157c3e2126dd277: > > ARM: DRA7xx: Fix memory allocation overflow (2017-02-17 17:24:35 -0500) > > are available in the git repository at: > > git://git.denx.de/u-boot-x86.git > > for you to fetch changes up to 308c75e08deac2933fbc63a1e9521343e710279c: > > x86: Intel MID platforms has no microcode update (2017-02-21 15:10:56 +0800) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Drop CONFIG_ENABLE_VBOOT
On Fri, Feb 17, 2017 at 07:48:09PM -0500, Tom Rini wrote: > This is no longer used anywhere. > > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v1 2/2] sun8i: enable support for the Micrel KSZ9031 with SUN8I_EMAC
On Wed, Feb 22, 2017 at 03:45:41PM +0100, Dr. Philipp Tomsich wrote: > Maxime, > > > On 21 Feb 2017, at 21:35, Dr. Philipp Tomsich > > wrote: > > > > Maxime, > > > >> On 21 Feb 2017, at 20:56, Maxime Ripard > >> wrote: > >> > >> On Fri, Feb 17, 2017 at 06:47:55PM +0100, Philipp Tomsich wrote: > >>> #ifdef CONFIG_SUN8I_EMAC > >>> #define CONFIG_PHY_GIGE /* GMAC can use gigabit PHY > >>> */ > >>> +#define CONFIG_PHY_MICREL > >>> +#define CONFIG_PHY_MICREL_KSZ9031 /* used on A64-uQ7 > >>> */ > >>> #endif > >> > >> Same thing here, and that way you could enable it only on the board > >> defconfig. > > I’d really like to keep this for all SUN8I_EMAC configurations, as we > need the PHY support to initialise the pad timing parameters from the > DTS. If these are not initialised, then RGMII (i.e. Gigabit) will not work. I'm not really discussing whether it is needed or not. > As we are moving towards a ‘universal’ U-Boot binary for sun50i and > try to put all board specific info into the DTS, I’d like to keep this in > sunxi-common.h to ensure that nobody rebuild without it and then > has issues on our boards. I'm not buying the whole universal U-Boot binary thing, but that's really not related to the discussion. sunxi-common.h should be reduced, not expanded to cover new stuff, in favor of Kconfig. Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] arm: am57xx: Update bootloader partition size
On Wed, Feb 22, 2017 at 5:00 AM, Bajjuri, Praneeth wrote: > > > On 2/21/2017 3:48 PM, Felipe Balbi wrote: >> >> Hi, >> >> Sam Protsenko writes: >>> >>> On Tue, Feb 21, 2017 at 10:35 PM, Felipe Balbi >>> wrote: Hi, Sam Protsenko writes: > > From: Praneeth Bajjuri > > The current size of u-boot is already ~840 KiB. > > This patch is to increase bootloader partition size up to 1 MiB > and thereby fix flashing error like below: > > sending 'bootloader' (840 KB)... > OKAY [ 0.048s] > writing 'bootloader'... > FAILED (remote: too large for partition) > > Signed-off-by: Sam Protsenko Missing Praneeth's Signed-off-by? >>> Yes. But not sure If I should resend. >>> >>> Tom, will you please add Praneeth's Signed-off-by line when applying >>> patch? >> >> Only if Praneeth agrees, right ? ;-) > > agreed and ok with me > thanks felipe , sam Tom, Please apply this one. Thanks. >> >> > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] sun8i_emac: configure PHY reset GPIO via DM
This ports the support for configuring a GPIO for resetting the
Ethernet PHY (incl. such details as the reset polarity and
pulse-length) from the Designware driver.
X-AffectedPlatforms: A64-uQ7
Signed-off-by: Philipp Tomsich
---
drivers/net/sun8i_emac.c | 86
1 file changed, 80 insertions(+), 6 deletions(-)
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index 5094dd8..ef9992f 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -21,6 +21,9 @@
#include
#include
#include
+#ifdef CONFIG_DM_GPIO
+#include
+#endif
#define MDIO_CMD_MII_BUSY BIT(0)
#define MDIO_CMD_MII_WRITE BIT(1)
@@ -134,11 +137,22 @@ struct emac_eth_dev {
phys_addr_t sysctl_reg;
struct phy_device *phydev;
struct mii_dev *bus;
+#ifdef CONFIG_DM_GPIO
+ struct gpio_desc reset_gpio;
+#endif
+};
+
+
+struct sun8i_eth_pdata {
+ struct eth_pdata eth_pdata;
+ u32 reset_delays[3];
};
+
static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
{
- struct emac_eth_dev *priv = bus->priv;
+ struct udevice *dev = bus->priv;
+ struct emac_eth_dev *priv = dev_get_priv(dev);
ulong start;
u32 miiaddr = 0;
int timeout = CONFIG_MDIO_TIMEOUT;
@@ -169,7 +183,8 @@ static int sun8i_mdio_read(struct mii_dev *bus, int addr,
int devad, int reg)
static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
u16 val)
{
- struct emac_eth_dev *priv = bus->priv;
+ struct udevice *dev = bus->priv;
+ struct emac_eth_dev *priv = dev_get_priv(dev);
ulong start;
u32 miiaddr = 0;
int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
@@ -610,7 +625,41 @@ static void sun8i_emac_board_setup(struct emac_eth_dev
*priv)
setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC));
}
-static int sun8i_mdio_init(const char *name, struct emac_eth_dev *priv)
+#if defined(CONFIG_DM_GPIO)
+static int sun8i_mdio_reset(struct mii_dev *bus)
+{
+ struct udevice *dev = bus->priv;
+ struct emac_eth_dev *priv = dev_get_priv(dev);
+ struct sun8i_eth_pdata *pdata = dev_get_platdata(dev);
+ int ret;
+
+ if (!dm_gpio_is_valid(&priv->reset_gpio))
+ return 0;
+
+ /* reset the phy */
+ ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+ if (ret)
+ return ret;
+
+ udelay(pdata->reset_delays[0]);
+
+ ret = dm_gpio_set_value(&priv->reset_gpio, 1);
+ if (ret)
+ return ret;
+
+ udelay(pdata->reset_delays[1]);
+
+ ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+ if (ret)
+ return ret;
+
+ udelay(pdata->reset_delays[2]);
+
+ return 0;
+}
+#endif
+
+static int sun8i_mdio_init(const char *name, struct udevice *priv)
{
struct mii_dev *bus = mdio_alloc();
@@ -623,6 +672,9 @@ static int sun8i_mdio_init(const char *name, struct
emac_eth_dev *priv)
bus->write = sun8i_mdio_write;
snprintf(bus->name, sizeof(bus->name), name);
bus->priv = (void *)priv;
+#if defined(CONFIG_DM_GPIO)
+ bus->reset = sun8i_mdio_reset;
+#endif
return mdio_register(bus);
}
@@ -702,7 +754,7 @@ static int sun8i_emac_eth_probe(struct udevice *dev)
sun8i_emac_board_setup(priv);
sun8i_emac_set_syscon(priv);
- sun8i_mdio_init(dev->name, priv);
+ sun8i_mdio_init(dev->name, dev);
priv->bus = miiphy_get_dev_by_name(dev->name);
return sun8i_phy_init(priv, dev);
@@ -719,11 +771,16 @@ static const struct eth_ops sun8i_emac_eth_ops = {
static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
+ struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
struct emac_eth_dev *priv = dev_get_priv(dev);
const char *phy_mode;
int node = dev_of_offset(dev);
int offset = 0;
+#ifdef CONFIG_DM_GPIO
+ int reset_flags = GPIOD_IS_OUT;
+ int ret = 0;
+#endif
pdata->iobase = dev_get_addr_name(dev, "emac");
priv->sysctl_reg = dev_get_addr_name(dev, "syscon");
@@ -768,6 +825,23 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct
udevice *dev)
if (!priv->use_internal_phy)
parse_phy_pins(dev);
+#ifdef CONFIG_DM_GPIO
+ if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
+ "snps,reset-active-low"))
+ reset_flags |= GPIOD_ACTIVE_LOW;
+
+ ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
+ &priv->reset_gpio, reset_flags);
+
+ if (ret == 0) {
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
+ "snps,reset-delays-us",
+
[U-Boot] [PATCH v2] sun8i_emac: configure PHY reset GPIO via DM
This ports the logic for having a GPIO as a reset-output for the mdio_reset function over from designware.c to the (closely related) sun8i_emac driver. Changes in v2: * use the "snps,"-namespace, as the same node binds to the stmmac (i.e. designware) driver on Linux and the Linux DTS is leading Philipp Tomsich (1): sun8i_emac: configure PHY reset GPIO via DM drivers/net/sun8i_emac.c | 86 1 file changed, 80 insertions(+), 6 deletions(-) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 0/2] part_efi: support padding between the GPT header and partition entries
Some architectures require their SPL loader at a fixed address within the first 16KB of the disk. To avoid an overlap with the partition entries of the EFI partition table, the first safe offset (in bytes, from the start of the device) for the entries can be set through CONFIG_EFI_PARTITION_ENTRIES_OFF. For easier readability, I kept the functional changes separate from the update of the device-tree-bindings documentation. Changes in v2: * CONFIG_EFI_PARTITION_ENTRIES_OFF is configurable via Kconfig * added clamping to ensure that the parititions are never put into the first to LBAs of a device * documented the new /config property (and moved the documentation of /config properties into a separate file per Simon's review comment) Philipp Tomsich (2): part_efi: support padding between the GPT header and partition entries part_efi: document device-tree binding for part_efi configuration disk/Kconfig| 13 ++ disk/part_efi.c | 50 ++--- doc/README.fdt-control | 16 doc/device-tree-bindings/config.txt | 22 4 files changed, 81 insertions(+), 20 deletions(-) create mode 100644 doc/device-tree-bindings/config.txt -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/2] part_efi: support padding between the GPT header and partition entries
Some architectures require their SPL loader at a fixed address within
the first 16KB of the disk. To avoid an overlap with the partition
entries of the EFI partition table, the first safe offset (in bytes,
from the start of the device) for the entries can be set through
CONFIG_EFI_PARTITION_ENTRIES_OFF (via Kconfig)
When formatting a device with an EFI partition table, we may need to
leave a gap between the GPT header (always in LBA 1) and the partition
entries. The GPT header already contains a field to specify the
on-disk location, which has so far always been set to LBA 2. With this
change, a configurable offset will be translated into a LBA address
indicating where to put the entries.
Now also allows an override via device-tree using a config-node (see
doc/device-tree-bindings/config.txt for documentation).
Tested (exporting an internal MMC formatted with this) against Linux,
MacOS X and Windows.
Signed-off-by: Philipp Tomsich
---
disk/Kconfig| 13 +
disk/part_efi.c | 50 ++
2 files changed, 59 insertions(+), 4 deletions(-)
diff --git a/disk/Kconfig b/disk/Kconfig
index 16ff52d..8e328b4 100644
--- a/disk/Kconfig
+++ b/disk/Kconfig
@@ -79,6 +79,19 @@ config EFI_PARTITION
common when EFI is the bootloader. Note 2TB partition limit;
see disk/part_efi.c
+config EFI_PARTITION_ENTRIES_OFF
+int "Offset (in bytes) of the EFI partition entries"
+ depends on EFI_PARTITION
+ default 0
+ help
+ Specify an earliest location (in bytes) where the partition
+ entries may be located. This is meant to allow "punching a
+ hole into a device" to create a gap for an SPL, its payload
+ and the U-Boot environment.
+
+ If unsure, leave at 0 (which will locate the partition
+ entries at the first possible LBA following the GPT header).
+
config SPL_EFI_PARTITION
bool "Enable EFI GPT partition table for SPL"
depends on SPL && PARTITIONS
diff --git a/disk/part_efi.c b/disk/part_efi.c
index 893cbbd..fafca25 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -373,8 +374,8 @@ int write_gpt_table(struct blk_desc *dev_desc,
if (blk_dwrite(dev_desc, 1, 1, gpt_h) != 1)
goto err;
- if (blk_dwrite(dev_desc, 2, pte_blk_cnt, gpt_e)
- != pte_blk_cnt)
+ if (blk_dwrite(dev_desc, le64_to_cpu(gpt_h->partition_entry_lba),
+ pte_blk_cnt, gpt_e) != pte_blk_cnt)
goto err;
prepare_backup_gpt_header(gpt_h);
@@ -498,6 +499,45 @@ int gpt_fill_pte(gpt_header *gpt_h, gpt_entry *gpt_e,
return 0;
}
+static uint32_t partition_entries_offset(struct blk_desc *dev_desc)
+{
+ uint32_t offset_blks = 2;
+ int config_offset;
+
+#if defined(CONFIG_EFI_PARTITION_ENTRIES_OFF)
+ /* Some architectures require their SPL loader at a fixed
+* address within the first 16KB of the disk. To avoid an
+* overlap with the partition entries of the EFI partition
+* table, the first safe offset (in bytes, from the start of
+* the disk) for the entries can be set in
+* CONFIG_EFI_PARTITION_ENTRIES_OFF.
+*/
+ offset_blks =
+ PAD_TO_BLOCKSIZE(CONFIG_EFI_PARTITION_ENTRIES_OFF, dev_desc);
+#endif
+
+#if defined(CONFIG_OF_CONTROL)
+ /* Allow the offset of the first partition entires (in bytes
+ from the start of the device) to be specified as a property
+ of the device tree '/config' node. */
+ config_offset = fdtdec_get_config_int(gd->fdt_blob,
+
"u-boot,efi-partition-entries-offset",
+ -EINVAL);
+ if (config_offset != -EINVAL)
+ offset_blks = PAD_TO_BLOCKSIZE(config_offset, dev_desc);
+#endif
+
+ debug("efi: partition entries offset (in blocks): %d\n", offset_blks);
+
+ /* The earliest LBA this can be at is LBA#2 (i.e. right behind
+* the (protective) MBR and the GPT header.
+*/
+ if (offset_blks < 2)
+ offset_blks = 2;
+
+ return offset_blks;
+}
+
int gpt_fill_header(struct blk_desc *dev_desc, gpt_header *gpt_h,
char *str_guid, int parts_count)
{
@@ -506,9 +546,11 @@ int gpt_fill_header(struct blk_desc *dev_desc, gpt_header
*gpt_h,
gpt_h->header_size = cpu_to_le32(sizeof(gpt_header));
gpt_h->my_lba = cpu_to_le64(1);
gpt_h->alternate_lba = cpu_to_le64(dev_desc->lba - 1);
- gpt_h->first_usable_lba = cpu_to_le64(34);
gpt_h->last_usable_lba = cpu_to_le64(dev_desc->lba - 34);
- gpt_h->partition_entry_lba = cpu_to_le64(2);
+ gpt_h->partition_entry_lba =
+ cpu_to_le64(partition_entries_offset(dev_desc));
+ gpt_h->first_usable_lba =
+
[U-Boot] [PATCH v2 2/2] part_efi: document device-tree binding for part_efi configuration
This moves the description of the /config node from README.fdt-control into a separate file doc/device-tree-bindings/config.txt and adds the documentation on the new u-boot,efi-partition-entries-offset property (which overrides CONFIG_EFI_PARTITION_ENTRIES_OFF, if present). Signed-off-by: Philipp Tomsich --- doc/README.fdt-control | 16 doc/device-tree-bindings/config.txt | 22 ++ 2 files changed, 22 insertions(+), 16 deletions(-) create mode 100644 doc/device-tree-bindings/config.txt diff --git a/doc/README.fdt-control b/doc/README.fdt-control index 2913fcb..c965629 100644 --- a/doc/README.fdt-control +++ b/doc/README.fdt-control @@ -168,22 +168,6 @@ After board configuration is done, fdt supported u-boot can be build in two ways $ make DEVICE_TREE= -Configuration Options -- - -A number of run-time configuration options are provided in the /config node -of the control device tree. You can access these using fdtdec_get_config_int(), -fdtdec_get_config_bool() and fdtdec_get_config_string(). - -Available options are: - -silent-console - If present and non-zero, the console is silenced by default on boot. - -no-keyboard - Tells U-Boot not to expect an attached keyboard with a VGA console - - Limitations --- diff --git a/doc/device-tree-bindings/config.txt b/doc/device-tree-bindings/config.txt new file mode 100644 index 000..5640bae --- /dev/null +++ b/doc/device-tree-bindings/config.txt @@ -0,0 +1,22 @@ +The /config node (Configuration Options) + + +A number of run-time configuration options are provided in the /config node +of the control device tree. You can access these using fdtdec_get_config_int(), +fdtdec_get_config_bool() and fdtdec_get_config_string(). + +Available options are: + +silent-console + If present and non-zero, the console is silenced by default on boot. + +no-keyboard + Tells U-Boot not to expect an attached keyboard with a VGA console + +u-boot,efi-partition-entries-offset + If present, this provides an offset (in bytes, from the start of a + device) that should be skipped over before the partition entries. + This is used by the EFI/GPT partition implementation when a device + is formatted. + + This setting will override any values configured via Kconfig. -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] dtoc: make ScanTree recurse into subnodes
Previously, dtoc could only process the top-level nodes which led to
device nodes in hierarchical trees to be ignored. E.g. the mmc0 node
in the following example would be ignored, as only the soc node was
processed:
/ {
soc {
mmc0 {
/* ... */
};
};
};
This introduces a recursive helper method ScanNode, which is used by
ScanTree to recursively parse the entire tree hierarchy.
Signed-off-by: Philipp Tomsich
---
tools/dtoc/dtoc.py | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/tools/dtoc/dtoc.py b/tools/dtoc/dtoc.py
index 6df7b0d..fe8b0c2 100755
--- a/tools/dtoc/dtoc.py
+++ b/tools/dtoc/dtoc.py
@@ -170,6 +170,21 @@ class DtbPlatdata:
"""
self.fdt = fdt_select.FdtScan(self._dtb_fname)
+def ScanNode(self, root):
+for node in root.subnodes:
+if 'compatible' in node.props:
+status = node.props.get('status')
+if (not options.include_disabled and not status or
+status.value != 'disabled'):
+self._valid_nodes.append(node)
+phandle_prop = node.props.get('phandle')
+if phandle_prop:
+phandle = phandle_prop.GetPhandle()
+self._phandle_node[phandle] = node
+
+# recurse to handle any subnodes
+self.ScanNode(node);
+
def ScanTree(self):
"""Scan the device tree for useful information
@@ -178,8 +193,10 @@ class DtbPlatdata:
_valid_nodes: A list of nodes we wish to consider include in the
platform data
"""
-node_list = []
self._phandle_node = {}
+self._valid_nodes = []
+return self.ScanNode(self.fdt.GetRoot());
+
for node in self.fdt.GetRoot().subnodes:
if 'compatible' in node.props:
status = node.props.get('status')
--
1.9.1
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[U-Boot] [PATCH v3] armv8: spl: Call spl_relocate_stack_gd for ARMv8
As part of the startup process for boards using the SPL, we need to call spl_relocate_stack_gd. This is needed to set up malloc with its DRAM buffer. Signed-off-by: Philipp Tomsich Reviewed-by: Andre Przywara Reviewed-by: Simon Glass --- arch/arm/lib/crt0_64.S | 13 +++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index 19c6a98..a7cead5 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -109,8 +109,17 @@ relocation_return: */ bl c_runtime_cpu_setup /* still call old routine */ #endif /* !CONFIG_SPL_BUILD */ - -/* TODO: For SPL, call spl_relocate_stack_gd() to alloc stack relocation */ +#if defined(CONFIG_SPL_BUILD) + bl spl_relocate_stack_gd /* may return NULL */ + /* Perform 'sp = (x0 != NULL) ? x0 : sp' while working +* around the constraint that conditional moves can not +* have 'sp' as an operand +*/ + mov x1, sp + cmp x0, #0 + cselx0, x0, x1, ne + mov sp, x0 +#endif /* * Clear BSS section -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v1 0/2] disk: efi: allow gap before partition entries
On Tue, Feb 21, 2017 at 07:21:42PM +0100, Dr. Philipp Tomsich wrote: > > > On 21 Feb 2017, at 18:45, Maxime Ripard > > wrote: > > > > However, I'm a bit skeptical on the /config node. First, this node > > doesn't exist at all, and needs to be documented and acked by the DT > > maintainers. And why would one need to change that per device? > > What’s the consensus on this: remove the /config-node dependency > (or split off into a separate patch), make the CONFIG-option a first > class citizen and add to Kconfig… and reroll as v2? If Simon is happy with /config parameter, so am I, but yeah, moving it to Kconfig is needed. Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] spi: cadence_qspi_apb: Add trigger-base DT bindings from Linux
Marek Vasut wrote:
> On 02/21/2017 05:50 PM, Rush, Jason A. wrote:
>> The socfpga arch uses a different value for the indaddrtrig reg than
>> the ahbbase address. Adopting the Linux DT bindings separates the
>> ahbbase and trigger-base addresses, allowing the trigger-base to be+
>> set correctly on the socfpga arch.
>>
>> Tested on Terasic SoCkit dev board (Altera Cyclone V)
>>
>> Signed-off-by: Jason A. Rush
>> ---
>> arch/arm/dts/socfpga.dtsi | 1 +
>> drivers/spi/cadence_qspi.c | 2 ++
>> drivers/spi/cadence_qspi.h | 1 +
>> drivers/spi/cadence_qspi_apb.c | 4 ++--
>> 4 files changed, 6 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
>> index 8588221e57..2aff0c2419 100644
>> --- a/arch/arm/dts/socfpga.dtsi
>> +++ b/arch/arm/dts/socfpga.dtsi
>> @@ -644,6 +644,7 @@
>> clocks = <&qspi_clk>;
>> ext-decoder = <0>; /* external decoder */
>> num-cs = <4>;
>> +trigger-base = <0x>;
>
> Can you separate the DT patch from the driver patch ? Also, can you check the
> other users of the CQSPI driver to see if they define the
> trigger base ?
>
Yes, I will separate into two patches.
I default the trigger_base to the same value as the ahbbase if the trigger-base
was not defined in the DT. That way, the driver code works as before for
architectures that expect the trigger_base to equal the value of the ahbbase.
(e.g. TI K2G SoC). I updated only the Altera SoC dtsi file since that
architecture
needs a different value for the trigger_base.
Should I change this behavior to default the value to 0x0, and patch the 3
dts/dtsi
files that use the cadence driver to explicitly include the trigger-base?
>
>> fifo-depth = <128>;
>> sram-size = <128>;
>> bus-num = <2>;
>> diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
>> index 9a6e41f330..a18b331f6c 100644
>> --- a/drivers/spi/cadence_qspi.c
>> +++ b/drivers/spi/cadence_qspi.c
>> @@ -296,6 +296,8 @@ static int cadence_spi_ofdata_to_platdata(struct
>> udevice *bus)
>>
>> plat->regbase = (void *)data[0];
>> plat->ahbbase = (void *)data[2];
>> +plat->trigger_base = (void *)fdtdec_get_int(blob, node, "trigger-base",
>> +(int)plat->ahbbase);
>
> Probably get u32 , but what about 64-bit systems ? Don't we have some
> fdtdec_get.*addr ?
You're right, this should be a u32. I don't think I should have made
trigger_base
a void* in the first place, but instead it should be a u32. Looking at the
Linux
kernel, which I just realized they call it trigger_address not trigger_base, it
is just
a 32-bit value that is written into a 32-bit wide register, not an iomem memory
mapped pointer.
What if I change it to a u32 and rename it to trigger_address (which I should
have done the first time)? That would align us correctly with the Linux kernel.
>
>> plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128);
>>
>> /* All other paramters are embedded in the child node */ diff --git
>> a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index
>> d1927a4003..394820f308 100644
>> --- a/drivers/spi/cadence_qspi.h
>> +++ b/drivers/spi/cadence_qspi.h
>> @@ -18,6 +18,7 @@ struct cadence_spi_platdata {
>> unsigned intmax_hz;
>> void*regbase;
>> void*ahbbase;
>
> Can you remove the AHB base ? I think it's no longer used.
ahbbase is still used in cadence_qspi_apb.c, it's the register that the QSPI
data
is read from, so it's still needed.
> Also, I think this should be void __iomem * here , also for regbase .
>
This is probably true, regbase and ahbbase should both be __iomem *, but
that feels like a different clean-up patch. If you'd like me to, I could update
both of these as part of this patch though.
>
>> +void*trigger_base;
>>
>> u32 page_size;
>> u32 block_size;
>> diff --git a/drivers/spi/cadence_qspi_apb.c
>> b/drivers/spi/cadence_qspi_apb.c index e02f2217f4..0e66d5fd82 100644
>> --- a/drivers/spi/cadence_qspi_apb.c
>> +++ b/drivers/spi/cadence_qspi_apb.c
>> @@ -560,7 +560,7 @@ int cadence_qspi_apb_indirect_read_setup(struct
>> cadence_spi_platdata *plat,
>> addr_bytes = cmdlen - 1;
>>
>> /* Setup the indirect trigger address */
>> -writel((u32)plat->ahbbase,
>> +writel((u32)plat->trigger_base,
>> plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
>>
>> /* Configure the opcode */
>> @@ -710,7 +710,7 @@ int cadence_qspi_apb_indirect_write_setup(struct
>> cadence_spi_platdata *plat,
>> return -EINVAL;
>> }
>> /* Setup the indirect trigger address */
>> -writel((u32)plat->ahbbase,
>> +writel((u32)plat->trigger_base,
>> plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
>>
>> /* Configu
Re: [U-Boot] [PATCH v1] sunxi: improve throughput in the sunxi_mmc driver
> On 22 Feb 2017, at 18:22, Maxime Ripard > wrote: > > On Tue, Feb 21, 2017 at 07:34:40PM +0100, Dr. Philipp Tomsich wrote: >> >>> On 21 Feb 2017, at 19:11, Dr. Philipp Tomsich >>> wrote: >>> >>> We’ve never seen performance problems on Linux and benchmarked at >>> up to ~50MByte/s on the A31-uQ7. >> >> I dug into our disti training slides from early 2015—looks like the >> throughput >> number (sustained) for the eMMC was 12MB/s on write and 40MB/s on read >> when using our standard part (at that time), which was a SDIN7DP2-4G. > > I was getting around 60MB/s on an A64 with an HS200 eMMC, which is > quite good but left me the feeling that it could be better. But it was > just a feeling :) What does your eMMC datasheet list as expected throughput at HS200? We haven’t even bothered benchmarking the eMMC on our boards lately, as it’s “fast enough” for all practical purposes. Regards, Philipp. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v1 1/2] sun8i: define CONFIG_PHY_GIGE for EMAC
> On 22 Feb 2017, at 18:18, Maxime Ripard > wrote: > > On Tue, Feb 21, 2017 at 09:37:14PM +0100, Dr. Philipp Tomsich wrote: >> On 21 Feb 2017, at 20:55, Maxime Ripard >> wrote: >>> >>> On Fri, Feb 17, 2017 at 06:47:54PM +0100, Philipp Tomsich wrote: +#ifdef CONFIG_SUN8I_EMAC +#define CONFIG_PHY_GIGE /* GMAC can use gigabit PHY */ +#endif >>> >>> It would make more sense to move that option to Kconfig, and selecting >>> it from SUN8I_EMAC. >> >> CONFIG_PHY_GIGE is not a Kconfig option yet and only enabled via >> board-specific config files. > > Which is exactly what I was suggesting to do, sorry if it wasn't clear > :) > > We're still in the phase of getting options moved to kconfig, so this > seems like the perfect occasion to do so. Looks like this will be one of the many v2 patches for today. All I have to do now is to get my patch-format right ;-) Cheers, Philipp. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v1] sunxi: improve throughput in the sunxi_mmc driver
On Tue, Feb 21, 2017 at 07:34:40PM +0100, Dr. Philipp Tomsich wrote: > > > On 21 Feb 2017, at 19:11, Dr. Philipp Tomsich > > wrote: > > > > We’ve never seen performance problems on Linux and benchmarked at > > up to ~50MByte/s on the A31-uQ7. > > I dug into our disti training slides from early 2015—looks like the throughput > number (sustained) for the eMMC was 12MB/s on write and 40MB/s on read > when using our standard part (at that time), which was a SDIN7DP2-4G. I was getting around 60MB/s on an A64 with an HS200 eMMC, which is quite good but left me the feeling that it could be better. But it was just a feeling :) Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v1 1/2] sun8i: define CONFIG_PHY_GIGE for EMAC
On Tue, Feb 21, 2017 at 09:37:14PM +0100, Dr. Philipp Tomsich wrote: > On 21 Feb 2017, at 20:55, Maxime Ripard > wrote: > > > > On Fri, Feb 17, 2017 at 06:47:54PM +0100, Philipp Tomsich wrote: > >> +#ifdef CONFIG_SUN8I_EMAC > >> +#define CONFIG_PHY_GIGE /* GMAC can use gigabit PHY > >> */ > >> +#endif > > > > It would make more sense to move that option to Kconfig, and selecting > > it from SUN8I_EMAC. > > CONFIG_PHY_GIGE is not a Kconfig option yet and only enabled via > board-specific config files. Which is exactly what I was suggesting to do, sorry if it wasn't clear :) We're still in the phase of getting options moved to kconfig, so this seems like the perfect occasion to do so. Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Makefile: print warning if CONFIG_SYS_EXTRA_OPTIONS is used
On Wed, Feb 22, 2017 at 11:53:05AM +0900, Masahiro Yamada wrote: > 2017-02-22 8:16 GMT+09:00 Maxime Ripard : > > On Sat, Feb 18, 2017 at 03:24:53PM +0900, Masahiro Yamada wrote: > >> The prompt of this option is marked "DEPRECATED" in capital letters, > >> and its help clearly says: > >> This option was prepared for the smooth migration from the old > >> configuration to Kconfig. Since this option will be removed sometime, > >> new boards should not use this option. > >> > >> However, we have had almost no progress on this. In fact, this > >> option is often abused for fresh porting, and more and more new > >> defconfigs with it are coming in (for example, SUNXI boards). > > > > That's not entirely true. We've added more defconfig, but with the > > same set of options we've always had, and are shared by everyone > > (CONS_INDEX, RGMII). > > > > So this patch, in effect, gives the signal that it's better to have a > > proliferation of board-specific headers in include/configs, over using > > SYS_EXTRA until most of the generic functions are merged? > > No. > > I am saying to add > CONFIG_CONS_INDEX=2 > CONFIG_RGMII=y > > instead of > > CONFIG_SYS_EXTRA_OPTIONS=CONS_INDEX=2,RGMII" > > > Why proliferation of board-specific headers? The issue here is that we have a handful of options that need converting still, and are not "easy". For CONS_INDEX we need to find the right generic location for this to be and migrate, and remove the few instances of board-centric versions of the question. I agree with the sentiment of the original patch but I want to see how many of the current options can be knocked out easily. WRT sunxi, I posted moving two of them, and RGMII will happen as part of the general move of all of the network drivers over. SATAPWR and MACPWR will take a little more thinking on, to figure out. Do these values exist within the normal device tree in some way already for example? Thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] arm64: booti: allow to place kernel image anywhere in physical memory
On Wed, Feb 22, 2017 at 11:34:26AM +0900, Masahiro Yamada wrote:
> At first, the ARM64 Linux booting requirement recommended that the
> kernel image be placed text_offset bytes from 2MB aligned base near
> the start of usable system RAM because memory below that base address
> was unusable at that time.
>
> This requirement was relaxed by Linux commit a7f8de168ace ("arm64:
> allow kernel Image to be loaded anywhere in physical memory").
> Since then, the bit 3 of the flags field indicates the tolerance
> of the kernel physical placement. If this bit is set, the 2MB
> aligned base may be anywhere in physical memory. For details, see
> Documentation/arm64/booting.txt of Linux.
>
> The booti command should be also relaxed to not expect the kernel
> image at the start of the system RAM. Even when booting older
> kernel versions, it still makes sense to have some space below the
> kernel. For example, some firmware may sit at the start of the
> system RAM.
>
> After all, the most flexible way for booting the kernel is to respect
> the original images->ep instead of gd->bd->bi_dram[0].start. If
> image->ep (which is the address given to the booti command) already
> meets the address requirement, just use it. If not, relocate the
> kernel to the next 2MB aligned address.
>
> Signed-off-by: Masahiro Yamada
> ---
>
> cmd/booti.c | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/cmd/booti.c b/cmd/booti.c
> index f65f0e7..9408c34 100644
> --- a/cmd/booti.c
> +++ b/cmd/booti.c
> @@ -11,6 +11,8 @@
> #include
> #include
> #include
> +#include
> +#include
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -54,7 +56,9 @@ static int booti_setup(bootm_headers_t *images)
>* If we are not at the correct run-time location, set the new
>* correct location and then move the image there.
>*/
> - dst = gd->bd->bi_dram[0].start + le64_to_cpu(ih->text_offset);
> + dst = images->ep - ih->text_offset;
> + dst = ALIGN(dst, SZ_2M);
> + dst += ih->text_offset;
I think the code will be slightly more complex here but I would rather
see us check for the presence of the flag which allows for us to
relocate things rather than assume that we can always use the address
provided, or round it up. The 'contract' wwith the kernel previously
said it must be from start of memory and I'd rather not change that.
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Re: [U-Boot] [PATCH] board: ns2: Add support for Broadcom Northstar 2
On Fri, Feb 17, 2017 at 04:17:10PM -0500, Jon Mason wrote:
> Add support for the Broadcom Northstar2 SoC and SVK (bcm958712k). The
> BCM5871X is a series of quad-core 64-bit 2GHz ARMv8 Cortex-A57
> processors targeting a broad range of networking applications.
>
> Signed-off-by: Jon Mason
> ---
> arch/arm/Kconfig | 9 ++
> board/broadcom/bcm958712k/MAINTAINERS | 6
> board/broadcom/bcmns2/Kconfig | 15 +
> board/broadcom/bcmns2/Makefile| 7 +
> board/broadcom/bcmns2/northstar2.c| 57
> +++
> configs/bcm958712k_defconfig | 9 ++
> include/configs/bcm_northstar2.h | 55 +
> 7 files changed, 158 insertions(+)
> create mode 100644 board/broadcom/bcm958712k/MAINTAINERS
> create mode 100644 board/broadcom/bcmns2/Kconfig
> create mode 100644 board/broadcom/bcmns2/Makefile
> create mode 100644 board/broadcom/bcmns2/northstar2.c
> create mode 100644 configs/bcm958712k_defconfig
> create mode 100644 include/configs/bcm_northstar2.h
I assume you have some follow up patches to add some code under
arch/arm/mach- ? Or is there just a whole bunch of stuff that's
done in ATF or similar instead? Also:
> +int dram_init(void)
> +{
> + gd->ram_size = PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE;
> + return 0;
> +}
You should be using get_ram_size() here.
[snip]
> +CONFIG_BOOTDELAY=30
Having 30 seconds here is huge. I know in your talk you were mentioning
how to interrupt boot but I'd really rather not see this exceed 10 and 5
is usually sufficient.
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Re: [U-Boot] [PATCH] spi: cadence_qspi_apb: Add trigger-base DT bindings from Linux
On 02/21/2017 05:50 PM, Rush, Jason A. wrote:
> The socfpga arch uses a different value for the indaddrtrig reg than
> the ahbbase address. Adopting the Linux DT bindings separates the
> ahbbase and trigger-base addresses, allowing the trigger-base to be+
> set correctly on the socfpga arch.
>
> Tested on Terasic SoCkit dev board (Altera Cyclone V)
>
> Signed-off-by: Jason A. Rush
> ---
> arch/arm/dts/socfpga.dtsi | 1 +
> drivers/spi/cadence_qspi.c | 2 ++
> drivers/spi/cadence_qspi.h | 1 +
> drivers/spi/cadence_qspi_apb.c | 4 ++--
> 4 files changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
> index 8588221e57..2aff0c2419 100644
> --- a/arch/arm/dts/socfpga.dtsi
> +++ b/arch/arm/dts/socfpga.dtsi
> @@ -644,6 +644,7 @@
> clocks = <&qspi_clk>;
> ext-decoder = <0>; /* external decoder */
> num-cs = <4>;
> + trigger-base = <0x>;
Can you separate the DT patch from the driver patch ? Also, can you
check the other users of the CQSPI driver to see if they define the
trigger base ?
> fifo-depth = <128>;
> sram-size = <128>;
> bus-num = <2>;
> diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
> index 9a6e41f330..a18b331f6c 100644
> --- a/drivers/spi/cadence_qspi.c
> +++ b/drivers/spi/cadence_qspi.c
> @@ -296,6 +296,8 @@ static int cadence_spi_ofdata_to_platdata(struct udevice
> *bus)
>
> plat->regbase = (void *)data[0];
> plat->ahbbase = (void *)data[2];
> + plat->trigger_base = (void *)fdtdec_get_int(blob, node, "trigger-base",
> + (int)plat->ahbbase);
Probably get u32 , but what about 64-bit systems ? Don't we have some
fdtdec_get.*addr ?
> plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128);
>
> /* All other paramters are embedded in the child node */
> diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
> index d1927a4003..394820f308 100644
> --- a/drivers/spi/cadence_qspi.h
> +++ b/drivers/spi/cadence_qspi.h
> @@ -18,6 +18,7 @@ struct cadence_spi_platdata {
> unsigned intmax_hz;
> void*regbase;
> void*ahbbase;
Can you remove the AHB base ? I think it's no longer used.
Also, I think this should be void __iomem * here , also for
regbase .
> + void*trigger_base;
>
> u32 page_size;
> u32 block_size;
> diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
> index e02f2217f4..0e66d5fd82 100644
> --- a/drivers/spi/cadence_qspi_apb.c
> +++ b/drivers/spi/cadence_qspi_apb.c
> @@ -560,7 +560,7 @@ int cadence_qspi_apb_indirect_read_setup(struct
> cadence_spi_platdata *plat,
> addr_bytes = cmdlen - 1;
>
> /* Setup the indirect trigger address */
> - writel((u32)plat->ahbbase,
> + writel((u32)plat->trigger_base,
> plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
>
> /* Configure the opcode */
> @@ -710,7 +710,7 @@ int cadence_qspi_apb_indirect_write_setup(struct
> cadence_spi_platdata *plat,
> return -EINVAL;
> }
> /* Setup the indirect trigger address */
> - writel((u32)plat->ahbbase,
> + writel((u32)plat->trigger_base,
> plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
>
> /* Configure the opcode */
>
--
Best regards,
Marek Vasut
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[U-Boot] [PATCH V3 02/19] imx: mx7ulp: add registers header file
Add imx-regs.h for i.MX7ULP registers addresses definitions and some registers structures. Signed-off-by: Peng Fan Signed-off-by: Ye Li Reviewed-by : Stefano Babic --- V3: Move definitions in other patches into this one Add reviewed by tag. V2: None arch/arm/include/asm/arch-mx7ulp/imx-regs.h | 1120 +++ 1 file changed, 1120 insertions(+) create mode 100644 arch/arm/include/asm/arch-mx7ulp/imx-regs.h diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h new file mode 100644 index 000..dd9db73 --- /dev/null +++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h @@ -0,0 +1,1120 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MX7ULP_REGS_H_ +#define _MX7ULP_REGS_H_ + +#include + +#define CAAM_SEC_SRAM_BASE (0x2600) +#define CAAM_SEC_SRAM_SIZE (SZ_32K) +#define CAAM_SEC_SRAM_END (CAAM_SEC_SRAM_BASE + CAAM_SEC_SRAM_SIZE - 1) + +#define OCRAM_0_BASE(0x2F00) +#define OCRAM_0_SIZE(SZ_128K) +#define OCRAM_0_END (OCRAM_0_BASE + OCRAM_0_SIZE - 1) + +#define OCRAM_1_BASE(0x2F02) +#define OCRAM_1_SIZE(SZ_128K) +#define OCRAM_1_END (OCRAM_1_BASE + OCRAM_1_SIZE - 1) + +#define TCML_BASE (0x1FFD) +#define TCMU_BASE (0x2000) + +#define AIPS3_BASE (0x4080UL) +#define AIPS3_SLOT_SIZE(SZ_64K) +#define AIPS2_BASE (0x4000UL) +#define AIPS2_SLOT_SIZE(SZ_64K) +#define AIPS1_BASE (0x4108UL) +#define AIPS1_SLOT_SIZE(SZ_4K) +#define AIPS0_BASE (0x4100UL) +#define AIPS0_SLOT_SIZE(SZ_4K) +#define IOMUXC0_AIPS0_SLOT (61) +#define WDG0_AIPS0_SLOT(37) +#define WDG1_AIPS2_SLOT(61) +#define WDG2_AIPS2_SLOT(67) +#define WDG0_PCC0_SLOT (37) +#define IOMUXC1_AIPS3_SLOT (44) +#define CMC0_AIPS1_SLOT(36) +#define CMC1_AIPS2_SLOT(65) +#define SCG0_AIPS0_SLOT(39) +#define PCC0_AIPS0_SLOT(38) +#define PCC1_AIPS1_SLOT(50) +#define PCC2_AIPS2_SLOT(63) +#define PCC3_AIPS3_SLOT(51) +#define SCG1_AIPS2_SLOT(62) +#define SIM0_AIPS1_SLOT(35) +#define SIM1_AIPS1_SLOT(48) +#define USBOTG0_AIPS2_SLOT (51) +#define USBOTG1_AIPS2_SLOT (52) +#define USBPHY_AIPS2_SLOT (53) +#define USDHC0_AIPS2_SLOT (55) +#define USDHC1_AIPS2_SLOT (56) +#define RGPIO2P0_AIPS0_SLOT(15) +#define RGPIO2P1_AIPS2_SLOT(15) +#define IOMUXC0_AIPS0_SLOT (61) +#define OCOTP_CTRL_AIPS1_SLOT (38) +#define OCOTP_CTRL_PCC1_SLOT (38) +#define SIM1_PCC1_SLOT (48) +#define MMDC0_AIPS3_SLOT (43) +#define IOMUXC_DDR_AIPS3_SLOT (45) + +#define LPI2C0_AIPS0_SLOT (51) +#define LPI2C1_AIPS0_SLOT (52) +#define LPI2C2_AIPS0_SLOT (53) +#define LPI2C3_AIPS0_SLOT (54) +#define LPI2C4_AIPS2_SLOT (43) +#define LPI2C5_AIPS2_SLOT (44) +#define LPI2C6_AIPS3_SLOT (36) +#define LPI2C7_AIPS3_SLOT (37) + +#define LPUART0_PCC0_SLOT (58) +#define LPUART1_PCC0_SLOT (59) +#define LPUART2_PCC1_SLOT (43) +#define LPUART3_PCC1_SLOT (44) +#define LPUART0_AIPS0_SLOT (58) +#define LPUART1_AIPS0_SLOT (59) +#define LPUART2_AIPS1_SLOT (43) +#define LPUART3_AIPS1_SLOT (44) +#define LPUART4_AIPS2_SLOT (45) +#define LPUART5_AIPS2_SLOT (46) +#define LPUART6_AIPS3_SLOT (38) +#define LPUART7_AIPS3_SLOT (39) + +#define CORE_B_ROM_SIZE(SZ_32K + SZ_64K) +#define CORE_B_ROM_BASE(0x) + +#define ROMCP_ARB_BASE_ADDRCORE_B_ROM_BASE +#define ROMCP_ARB_END_ADDR CORE_B_ROM_SIZE +#define IRAM_BASE_ADDR OCRAM_0_BASE +#define IRAM_SIZE (SZ_128K + SZ_128K) + +#define IOMUXC_PCR_MUX_ALT0(0<<8) +#define IOMUXC_PCR_MUX_ALT1(1<<8) +#define IOMUXC_PCR_MUX_ALT2(2<<8) +#define IOMUXC_PCR_MUX_ALT3(3<<8) +#define IOMUXC_PCR_MUX_ALT4(4<<8) +#define IOMUXC_PCR_MUX_ALT5(5<<8) +#define IOMUXC_PCR_MUX_ALT6(6<<8) +#define IOMUXC_PCR_MUX_ALT7(7<<8) +#define IOMUXC_PCR_MUX_ALT8(8<<8) +#define IOMUXC_PCR_MUX_ALT9
[U-Boot] [PATCH 1/3] mx7: Fix speed grade entry
According to the MX7D fuse map the speed grade of the parts, which
return '1' is 500MHz instead of 850MHz, so fix it accordingly.
Signed-off-by: Fabio Estevam
---
arch/arm/cpu/armv7/mx7/soc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c
index dead1d3..b9fb97b 100644
--- a/arch/arm/cpu/armv7/mx7/soc.c
+++ b/arch/arm/cpu/armv7/mx7/soc.c
@@ -103,7 +103,7 @@ struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
*/
#define OCOTP_TESTER3_SPEED_SHIFT 8
#define OCOTP_TESTER3_SPEED_800MHZ 0
-#define OCOTP_TESTER3_SPEED_850MHZ 1
+#define OCOTP_TESTER3_SPEED_500MHZ 1
#define OCOTP_TESTER3_SPEED_1GHZ 2
u32 get_cpu_speed_grade_hz(void)
@@ -121,8 +121,8 @@ u32 get_cpu_speed_grade_hz(void)
switch(val) {
case OCOTP_TESTER3_SPEED_800MHZ:
return 79200;
- case OCOTP_TESTER3_SPEED_850MHZ:
- return 85200;
+ case OCOTP_TESTER3_SPEED_500MHZ:
+ return 5;
case OCOTP_TESTER3_SPEED_1GHZ:
return 99600;
}
--
2.7.4
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[U-Boot] [PATCH V3 03/19] imx: mx7ulp: add iomux driver to support IOMUXC0 and IOMUXC1
Add a new driver under ULP directory to support its IOMUXC
controllers. The ULP has two IOMUXC, the IOMUXC0 is used
for M4 domain, while IOMUXC1 is for A7. We set IOMUXC1 as
the default IOMUX in this driver. Any pins in IOMUXC0 needs
to configure with IOMUX_CONFIG_MPORTS in its mux_mode field.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
Reviewed-by : Stefano Babic
---
V3:
Add review tag
V2:
none
arch/arm/cpu/armv7/mx7ulp/Makefile | 8 +++
arch/arm/cpu/armv7/mx7ulp/iomux.c| 70 +++
arch/arm/include/asm/arch-mx7ulp/iomux.h | 95
3 files changed, 173 insertions(+)
create mode 100644 arch/arm/cpu/armv7/mx7ulp/Makefile
create mode 100644 arch/arm/cpu/armv7/mx7ulp/iomux.c
create mode 100644 arch/arm/include/asm/arch-mx7ulp/iomux.h
diff --git a/arch/arm/cpu/armv7/mx7ulp/Makefile
b/arch/arm/cpu/armv7/mx7ulp/Makefile
new file mode 100644
index 000..be038e7
--- /dev/null
+++ b/arch/arm/cpu/armv7/mx7ulp/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+#
+
+obj-y := iomux.o
diff --git a/arch/arm/cpu/armv7/mx7ulp/iomux.c
b/arch/arm/cpu/armv7/mx7ulp/iomux.c
new file mode 100644
index 000..1eba24e
--- /dev/null
+++ b/arch/arm/cpu/armv7/mx7ulp/iomux.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include
+#include
+#include
+#include
+
+static void *base = (void *)IOMUXC_BASE_ADDR;
+
+/*
+ * iomuxc0 base address. In imx7ulp-pins.h,
+ * the offsets of pins in iomuxc0 are from 0xD000,
+ * so we set the base address to (0x4103D000 - 0xD000 = 0x4103)
+ */
+static void *base_mports = (void *)(AIPS0_BASE + 0x3);
+
+/*
+ * configures a single pad in the iomuxer
+ */
+void mx7ulp_iomux_setup_pad(iomux_cfg_t pad)
+{
+ u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
+ u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
+ u32 sel_input_ofs =
+ (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
+ u32 sel_input =
+ (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
+ u32 pad_ctrl_ofs = mux_ctrl_ofs;
+ u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
+
+ debug("[PAD CFG] = 0x%16llX \r\n\tmux_ctl = 0x%X(0x%X) sel_input =
0x%X(0x%X) pad_ctrl = 0x%X(0x%X)\r\n",
+ pad, mux_ctrl_ofs, mux_mode, sel_input_ofs, sel_input,
+ pad_ctrl_ofs, pad_ctrl);
+
+ if (mux_mode & IOMUX_CONFIG_MPORTS) {
+ mux_mode &= ~IOMUX_CONFIG_MPORTS;
+ base = base_mports;
+ } else {
+ base = (void *)IOMUXC_BASE_ADDR;
+ }
+
+ __raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) &
+IOMUXC_PCR_MUX_ALT_MASK), base + mux_ctrl_ofs);
+
+ if (sel_input_ofs)
+ __raw_writel((sel_input << IOMUXC_PSMI_IMUX_ALT_SHIFT),
+ base + sel_input_ofs);
+
+ if (!(pad_ctrl & NO_PAD_CTRL))
+ __raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) &
+IOMUXC_PCR_MUX_ALT_MASK) |
+(pad_ctrl & (~IOMUXC_PCR_MUX_ALT_MASK)),
+base + pad_ctrl_ofs);
+}
+
+/* configures a list of pads within declared with IOMUX_PADS macro */
+void mx7ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list,
+ unsigned count)
+{
+ iomux_cfg_t const *p = pad_list;
+ int i;
+
+ for (i = 0; i < count; i++) {
+ mx7ulp_iomux_setup_pad(*p);
+ p++;
+ }
+}
diff --git a/arch/arm/include/asm/arch-mx7ulp/iomux.h
b/arch/arm/include/asm/arch-mx7ulp/iomux.h
new file mode 100644
index 000..a2307db
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7ulp/iomux.h
@@ -0,0 +1,95 @@
+/*
+ * Based on Linux i.MX iomux-v3.h file:
+ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
+ *
+ *
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __MACH_IOMUX_H__
+#define __MACH_IOMUX_H__
+
+/*
+ * build IOMUX_PAD structure
+ *
+ * This iomux scheme is based around pads, which are the physical balls
+ * on the processor.
+ *
+ * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
+ * things like driving strength and pullup/pulldown.
+ * - Each pad can have but not necessarily does have an output routing register
+ * (IOMUXC_SW_MUX_CTL_PAD_x).
+ * - Each pad can have but not necessarily does have an input routing register
+ * (IOMUXC_x_SELECT_INPUT)
+ *
+ * The three register sets do not have a fixed offset to each other,
+ * hence we order this table by pad control registers (which all pads
+ * have) and put the optional i/o routing registers into additional
+ * fields.
+ *
+ * The naming convention for the pad mod
[U-Boot] [PATCH 3/3] mx7: Add 1.2GHz speed grade entry
There are recent MX7 parts that have a 1.2GHz speed grade.
Add support for it.
Signed-off-by: Fabio Estevam
---
arch/arm/cpu/armv7/mx7/soc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c
index 8cde77b..8422f24 100644
--- a/arch/arm/cpu/armv7/mx7/soc.c
+++ b/arch/arm/cpu/armv7/mx7/soc.c
@@ -105,6 +105,7 @@ struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
#define OCOTP_TESTER3_SPEED_800MHZ 0
#define OCOTP_TESTER3_SPEED_500MHZ 1
#define OCOTP_TESTER3_SPEED_1GHZ 2
+#define OCOTP_TESTER3_SPEED_1P2GHZ 3
u32 get_cpu_speed_grade_hz(void)
{
@@ -125,6 +126,8 @@ u32 get_cpu_speed_grade_hz(void)
return 5;
case OCOTP_TESTER3_SPEED_1GHZ:
return 10;
+ case OCOTP_TESTER3_SPEED_1P2GHZ:
+ return 12;
}
return 0;
}
--
2.7.4
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[U-Boot] [PATCH 2/3] mx7: Fix the get_cpu_speed_grade_hz() return values
According to the MX7D fuse map the following speed grades are available:
800 MHz
500 MHz
1000 MHz
1200 MHz
So simply return the real frequency that corresponds to the speed grade.
With this change we see on boot:
CPU: Freescale i.MX7D rev1.2 1000 MHz (running at 792 MHz)
Signed-off-by: Fabio Estevam
---
arch/arm/cpu/armv7/mx7/soc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c
index b9fb97b..8cde77b 100644
--- a/arch/arm/cpu/armv7/mx7/soc.c
+++ b/arch/arm/cpu/armv7/mx7/soc.c
@@ -120,11 +120,11 @@ u32 get_cpu_speed_grade_hz(void)
switch(val) {
case OCOTP_TESTER3_SPEED_800MHZ:
- return 79200;
+ return 8;
case OCOTP_TESTER3_SPEED_500MHZ:
return 5;
case OCOTP_TESTER3_SPEED_1GHZ:
- return 99600;
+ return 10;
}
return 0;
}
--
2.7.4
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