Hi Joe,
On 08.08.2017 17:57, Joe Hershberger wrote:
Hi Stefan (and Stefan),
On Tue, Aug 8, 2017 at 7:05 AM, Stefan Roese wrote:
Hi Joe,
On 11.07.2017 10:04, Stefan Roese wrote:
On 21.06.2017 10:31, stef...@malvell.com wrote:
Huh? Sent from a typo email address?
Where is the problem wit
This driver is replaced by the SPI-flash-based AT45xxx DataFlash
driver, which supports the driver model and device tree, the
atmel_dataflash_spi driver will not be used any more.
Signed-off-by: Wenyou Yang
---
drivers/spi/Makefile | 1 -
drivers/spi/atmel_dataflash_spi.c | 184 -
Add driver model support for mxc spi driver.
Most functions are restructured to be reused by DM and non-DM.
Tested on mx6slevk/mx6qsabresd board.
Signed-off-by: Peng Fan
Cc: Jagan Teki
cc: Stefano Babic
---
V2:
return -ENODEV when dev_get_addr not return a valid value.
Pass error value from
On Sel, 2017-08-08 at 11:29 +0200, Marek Vasut wrote:
> On 08/08/2017 11:12 AM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Function for checking FPGA early release setting which is defined
> > by user in FDT chosen section. This function would be used by
> > later drive
Increase env sector size from 64kb to 256kb for qspi boot
Signed-off-by: Santan Kumar
Signed-off-by: Priyanka Jain
---
Changes for v2:
-Change the commit message
include/configs/ls2080a_common.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/ls2080a_common
On Sel, 2017-08-08 at 12:11 +0200, Marek Vasut wrote:
> On 08/08/2017 12:06 PM, Chee, Tien Fong wrote:
> >
> > On Sel, 2017-08-08 at 11:32 +0200, Marek Vasut wrote:
> > >
> > > On 08/08/2017 11:12 AM, tien.fong.c...@intel.com wrote:
> > > >
> > > >
> > > > From: Tien Fong Chee
> > > >
> > > >
> On Aug 8, 2017, at 21:21, Santan Kumar wrote:
>
>
>
>> -Original Message-
>> From: York Sun
>> Sent: Tuesday, August 08, 2017 11:26 PM
>> To: Santan Kumar ; u-boot@lists.denx.de
>> Cc: Priyanka Jain
>> Subject: Re: [PATCH 1/1] armv8: ls2080a: Increase env size for qspi boot
>>
>>>
On Sel, 2017-08-08 at 11:32 +0200, Marek Vasut wrote:
> On 08/08/2017 11:12 AM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Enable cff driver build which is needed as intermediate driver for
> > handling
> > operation of FPGA program between feeding FPGA design from flas
> -Original Message-
> From: York Sun
> Sent: Tuesday, August 08, 2017 11:26 PM
> To: Santan Kumar ; u-boot@lists.denx.de
> Cc: Priyanka Jain
> Subject: Re: [PATCH 1/1] armv8: ls2080a: Increase env size for qspi boot
>
> On 06/23/2017 03:07 AM, Santan Kumar wrote:
> > Increase env size
Hi Simon, Patrice,
Am 06.08.2017 um 07:15 schrieb Simon Glass:
Hi Patrice,
On 25 July 2017 at 10:02, wrote:
From: Patrice Chotard
Add i2c driver which can be used on both STM32F7 and STM32H7.
This I2C block supports the following features:
_ Slave and master modes
_ Multimaster capabil
Hello Marek,
Am 07.08.2017 um 20:45 schrieb Marek Vasut:
Allow sending restart conditions upon direction change as this is
required by some chips.
Signed-off-by: Marek Vasut
Cc: Stefan Roese
Cc: Alexey Brodkin
Cc: Heiko Schocher
---
drivers/i2c/designware_i2c.c | 3 ++-
1 file changed, 2
在 2017-08-09 11:46，Chen-Yu Tsai 写道：
On Tue, Aug 8, 2017 at 2:46 PM, wrote:
在 2017-08-08 12:13，Chen-Yu Tsai 写道：
On Thu, Jul 20, 2017 at 2:00 PM, Icenowy Zheng
wrote:
Some new Allwinner SoCs' PRCM has a secure switch register, which
controls the access to some clock and power registers in
Hello Adam,
Am 07.08.2017 um 20:11 schrieb Adam Ford:
The driver is for all boards 24XX and up, so let's eliminate the
extra option called CONFIG_SYS_I2C_OMAP34XX since the driver checks
for CONFIG_OMAP34XX we don't need CONFIG_SYS_I2C_OMAP34XX.
Signed-off-by: Adam Ford
---
arch/arm/mach-oma
On Thu, Jul 27, 2017 at 3:31 AM, Maxime Ripard
wrote:
> On Wed, Jul 26, 2017 at 07:55:24PM +0800, icen...@aosc.io wrote:
>> 在 2017-07-20 14:00，Icenowy Zheng 写道：
>> > The PRCM of H3/H5 SoCs have a secure/non-secure switch, which controls
>> > the access to some clock/power related registers in PRCM
On Tue, Aug 8, 2017 at 2:46 PM, wrote:
> 在 2017-08-08 12:13，Chen-Yu Tsai 写道：
>>
>> On Thu, Jul 20, 2017 at 2:00 PM, Icenowy Zheng wrote:
>>>
>>> Some new Allwinner SoCs' PRCM has a secure switch register, which
>>> controls the access to some clock and power registers in PRCM block.
>>>
>>> Add
Hi Simon,
On Wed, Jul 5, 2017 at 3:31 AM, Simon Glass wrote:
> At present the driver-private data is obtained in various functions by
> various means. With driver model this is provided automatically. Without
> driver model it comes from a C array declared at the top of the file.
>
> Adjust inter
Hi York,
> -Original Message-
> From: York Sun
> Sent: 2017年8月9日 0:17
> To: Z.q. Hou ; u-boot@lists.denx.de
> Subject: Re: [PATCH] fsl-lsch2: csu: correct the workaround A-010315
>
> On 08/07/2017 11:31 PM, Z.q. Hou wrote:
> > Hi York,
> >
> > Thanks a lot for your comments!
> >
> >>
Hi York,
The default partition is mainly to facilitate the test staff to view the
partition information of the storage medium, And the jira ticket also carry by
the test staff, I am not sure if it need to push the opensource.
Qspi did not do partition processing, because of hardware design reas
On Tue, Aug 8, 2017 at 8:14 PM, Rob Clark wrote:
> On Tue, Aug 8, 2017 at 7:55 PM, Alexander Graf wrote:
>>
>>
>> On 09.08.17 00:39, Rob Clark wrote:
>>>
>>> On Tue, Aug 8, 2017 at 7:08 PM, Heinrich Schuchardt
>>> wrote:
On 08/09/2017 12:44 AM, Rob Clark wrote:
>
> On Tue, Aug
Stefano,
One question below:
On 2017-08-04 16:38, Stefan Agner wrote:
> From: Stefan Agner
>
> Add USB serial download protocol support to SPL. If the SoC started
> in recovery mode the SPL will immediately switch to SDP and wait for
> further downloads/commands from the host side.
>
> Signed-
On Tue, Aug 8, 2017 at 7:55 PM, Alexander Graf wrote:
>
>
> On 09.08.17 00:39, Rob Clark wrote:
>>
>> On Tue, Aug 8, 2017 at 7:08 PM, Heinrich Schuchardt
>> wrote:
>>>
>>> On 08/09/2017 12:44 AM, Rob Clark wrote:
On Tue, Aug 8, 2017 at 6:03 PM, Heinrich Schuchardt
wrote:
>
>>>
Commit 4483b7eb added variable vqmmc_dev but only uses it under
CONFIG_DM_REGULATOR. Add the same macro to variable declaration to
get rid of compiling warning.
Signed-off-by: York Sun
---
drivers/mmc/fsl_esdhc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mmc/fsl_esdhc.c b/dr
On 09.08.17 00:39, Rob Clark wrote:
On Tue, Aug 8, 2017 at 7:08 PM, Heinrich Schuchardt wrote:
On 08/09/2017 12:44 AM, Rob Clark wrote:
On Tue, Aug 8, 2017 at 6:03 PM, Heinrich Schuchardt wrote:
On 08/04/2017 09:31 PM, Rob Clark wrote:
This is convenient for efi_loader which deals a lot w
On Tue, Aug 8, 2017 at 7:08 PM, Heinrich Schuchardt wrote:
> On 08/09/2017 12:44 AM, Rob Clark wrote:
>> On Tue, Aug 8, 2017 at 6:03 PM, Heinrich Schuchardt
>> wrote:
>>> On 08/04/2017 09:31 PM, Rob Clark wrote:
This is convenient for efi_loader which deals a lot with utf16.
Signe
Hi Stefan,
On 08/07/2017 11:06 AM, Stefan Agner wrote:
Hi Eric,
On 2017-08-06 08:19, Eric Nelson wrote:
Hi Stefan,
On 08/04/2017 04:38 PM, Stefan Agner wrote:
From: Stefan Agner
This series adds NXP's Serial Download Protocol (SDP) support via
USB for SPL/U-Boot. It allows to download U-Bo
On Tue, Aug 8, 2017 at 6:50 PM, Heinrich Schuchardt wrote:
> On 08/04/2017 09:31 PM, Rob Clark wrote:
>> We'll eventually want these in a few places in efi_loader, and also
>> vsprintf.
>>
>> Signed-off-by: Rob Clark
>> ---
>> common/Makefile | 1 +
>> common/charset.c
> Am 09.08.2017 um 00:08 schrieb Heinrich Schuchardt :
>
>> On 08/09/2017 12:44 AM, Rob Clark wrote:
>>> On Tue, Aug 8, 2017 at 6:03 PM, Heinrich Schuchardt
>>> wrote:
On 08/04/2017 09:31 PM, Rob Clark wrote:
This is convenient for efi_loader which deals a lot with utf16.
Hi Patrice,
> -Original Message-
> From: Patrice CHOTARD
> Sent: Friday, August 04, 2017 6:19 AM
> To: u-boot@lists.denx.de; albert.u.b...@aribaud.net; s...@chromium.org; Vikas
> MANOCHA
> Cc: Patrice CHOTARD ; Patrick DELAUNAY
> ; Christophe KERELLO
>
> Subject: [PATCH 09/15] ARM: DTS
Hi Patrice,
> -Original Message-
> From: Patrice CHOTARD
> Sent: Friday, August 04, 2017 6:19 AM
> To: u-boot@lists.denx.de; albert.u.b...@aribaud.net; s...@chromium.org; Vikas
> MANOCHA
> Cc: Patrice CHOTARD ; Patrick DELAUNAY
> ; Christophe KERELLO
>
> Subject: [PATCH 08/15] ARM: DTS
On 08/09/2017 12:44 AM, Rob Clark wrote:
> On Tue, Aug 8, 2017 at 6:03 PM, Heinrich Schuchardt
> wrote:
>> On 08/04/2017 09:31 PM, Rob Clark wrote:
>>> This is convenient for efi_loader which deals a lot with utf16.
>>>
>>> Signed-off-by: Rob Clark
>>
>> Please, put this patch together with
>> [
On Tue, Aug 8, 2017 at 6:03 PM, Heinrich Schuchardt wrote:
> On 08/04/2017 09:31 PM, Rob Clark wrote:
>> This is convenient for efi_loader which deals a lot with utf16.
>>
>> Signed-off-by: Rob Clark
>
> Please, put this patch together with
> [PATCH] vsprintf.c: add GUID printing
> https://patchw
On 08/04/2017 09:31 PM, Rob Clark wrote:
> We'll eventually want these in a few places in efi_loader, and also
> vsprintf.
>
> Signed-off-by: Rob Clark
> ---
> common/Makefile | 1 +
> common/charset.c | 81
>
> include/char
On Tue, Aug 8, 2017 at 6:03 PM, Heinrich Schuchardt wrote:
> On 08/04/2017 09:31 PM, Rob Clark wrote:
>> This is convenient for efi_loader which deals a lot with utf16.
>>
>> Signed-off-by: Rob Clark
>
> Please, put this patch together with
> [PATCH] vsprintf.c: add GUID printing
> https://patchw
On 08/05/2017 01:38 AM, Stefan Agner wrote:
From: Stefan Agner
Add a new command to start USB Serial Download Protocol (SDP)
state machine.
Signed-off-by: Stefan Agner
---
cmd/Kconfig | 7 +++
cmd/Makefile | 1 +
cmd/usb_gadget_sdp.c | 53 +
Hi Stefan,
From: Stefan Agner
Support U-Boot images in SPL so that u-boot.img files can be
directly downloaded and executed. Furthermore support U-Boot
scripts download and execution in full U-Boot so that custom
recovery actions can be downloaded from the host in a third
step.
Signed-off-by:
Hi Stefan,
From: Stefan Agner
Add SDP (Serial Downloader Protocol) implementation for U-Boot. The
protocol is used in NXP SoC's boot ROM and allows to download program
images. Beside that, it can also be used to read/write registers and
download complete Device Configuration Data (DCD) sets. T
On 08/05/2017 01:38 AM, Stefan Agner wrote:
From: Stefan Agner
Move the imximage.h header file to a common location so we can make
use of it from U-Boot too.
Signed-off-by: Stefan Agner
---
{tools => include}/imximage.h | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename {tools =>
Hi Stefan,
From: Stefan Agner
This series adds NXP's Serial Download Protocol (SDP) support via
USB for SPL/U-Boot. It allows to download U-Boot via USB from a
(recovered) SPL using the same tools used to download SPL itself
(specifically imx_usb, but also sb_loader seems to work).
If I migh
On 08/04/2017 09:31 PM, Rob Clark wrote:
> This is convenient for efi_loader which deals a lot with utf16.
>
> Signed-off-by: Rob Clark
Please, put this patch together with
[PATCH] vsprintf.c: add GUID printing
https://patchwork.ozlabs.org/patch/798362/
and
[PATCH v0 06/20] common: add some utf1
On 2017-08-08 03:43, Lothar Waßmann wrote:
> Hi,
>
> On Fri, 4 Aug 2017 16:38:11 -0700 Stefan Agner wrote:
>> From: Stefan Agner
>>
>> Add USB serial download protocol support to SPL. If the SoC started
>> in recovery mode the SPL will immediately switch to SDP and wait for
>> further downloads/
On Tue, Aug 08, 2017 at 12:07:46PM -0400, Tom Rini wrote:
> Reviewed-by: Joe Hershberger
> Signed-off-by: Tom Rini
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: Digital signature
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h
On Mon, Aug 07, 2017 at 09:53:41PM +0200, Anatolij Gustschin wrote:
> Hi Tom,
>
> The following changes since commit eaa90e5df2a4a1cb12fb73571978a9379242d0b5:
>
> common/env_embedded.c: rename PPCENV/PPCTEXT macros (2017-08-04 20:38:39
> -0400)
>
> are available in the git repository at:
>
On Mon, Aug 07, 2017 at 03:30:32PM -0500, Joe Hershberger wrote:
> Hi Tom,
>
> The following changes since commit eaa90e5df2a4a1cb12fb73571978a9379242d0b5:
>
> common/env_embedded.c: rename PPCENV/PPCTEXT macros (2017-08-04 20:38:39
> -0400)
>
> are available in the git repository at:
>
>
On 07/24/2017 11:34 PM, Ashish Kumar wrote:
> CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
> provides full cache coherency between two clusters of multi-core
> CPUs and I/O coherency for devices and I/O masters.
>
> This patch add new CONFIG defination "SYS_FSL_HAS_CCI400" and
> mov
On Tue, Aug 8, 2017 at 11:07 AM, Tom Rini wrote:
>
> Signed-off-by: Tom Rini
> ---
> This does not attempt to imply anything. This level of detail is something
> that I feel must be done at the custodian level.
Reviewed-by: Joe Hershberger
___
U-Boo
On Tue, Aug 8, 2017 at 10:03 AM, Rob Clark wrote:
> On Tue, Aug 8, 2017 at 9:33 AM, Mark Kettenis wrote:
>>> From: Rob Clark
>>> Date: Tue, 8 Aug 2017 08:54:26 -0400
>>>
>>> On Tue, Aug 8, 2017 at 8:26 AM, Mark Kettenis
>>> wrote:
>>> >> From: Rob Clark
>>> >> Date: Mon, 7 Aug 2017 18:18:50 -
On 06/23/2017 03:07 AM, Santan Kumar wrote:
> Increase env size from 64kb to 256kb for qspi boot
>
> Signed-off-by: Santan Kumar
> Signed-off-by: Priyanka Jain
> ---
> This patch is split version of another patch
>
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork
On 2017-08-08 02:15, Stefano Babic wrote:
> Hi Stefan,
>
> On 07/08/2017 20:06, Stefan Agner wrote:
>> Hi Eric,
>>
>> On 2017-08-06 08:19, Eric Nelson wrote:
>>> Hi Stefan,
>>>
>>> On 08/04/2017 04:38 PM, Stefan Agner wrote:
From: Stefan Agner
This series adds NXP's Serial Download
On Tue, Aug 8, 2017 at 12:56 PM, Heinrich Schuchardt wrote:
> On 08/06/2017 01:39 PM, Rob Clark wrote:
>> This works (roughly) the same way as linux's, but we currently always
>> print lower-case (ie. we just keep %pUB and %pUL for compat with linux),
>> mostly just because that is what uuid_bin_t
Am 08.08.2017 um 18:22 schrieb Marek Vasut:
> On 08/08/2017 06:18 PM, Frank Kunz wrote:
>> For EFI boot GPT partition table support is needed as well
>> as the part command and also the SPL needs to fallback to
>> other boot methods after parse the SPL header.
>>
>> Signed-off-by: Frank Kunz
>
>
On 08/06/2017 01:39 PM, Rob Clark wrote:
> This works (roughly) the same way as linux's, but we currently always
> print lower-case (ie. we just keep %pUB and %pUL for compat with linux),
> mostly just because that is what uuid_bin_to_str() supports.
>
> %pUb: 01020304-0506-0708-090a-0b0c0d0e0
On 08/07/2017 07:48 PM, Xiaowei Bao wrote:
> Hi York,
>
> This patch is for the ls1046aqds platform, In order to facilitate the test
> staff and customers to view the detailed partition information, so didn't
> define a larger partition to include all images, and the partition rule is
> discus
On 08/08/2017 06:18 PM, Frank Kunz wrote:
> For EFI boot GPT partition table support is needed as well
> as the part command and also the SPL needs to fallback to
> other boot methods after parse the SPL header.
>
> Signed-off-by: Frank Kunz
Reviewed-by: Marek Vasut
I'd like to get a RB from D
On 08/07/2017 09:48 PM, Priyanka Jain wrote:
>
>
>> -Original Message-
>> From: York Sun
>> Sent: Tuesday, August 08, 2017 3:31 AM
>> To: Santan Kumar ; u-boot@lists.denx.de
>> Cc: Priyanka Jain
>> Subject: Re: [PATCH 1/1] board: ls2080ardb: Add fsl_fdt_fixup_flash
>>
>> On 07/05/2017 05
On 08/07/2017 09:51 PM, Yogesh Narayan Gaur wrote:
> Ack-ed
>
Thanks. For future use, please use this format
Acked-by: Yogesh Narayan Gaur
This will be captured by patchwork.
York
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On 08/07/2017 09:49 PM, Priyanka Jain wrote:
> Ack-ed
>
Thanks. For future use, please use this format
Acked-by: Priyanka Jain
This will be captured by patchwork so I can type less. :)
York
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On 08/07/2017 10:18 PM, Priyanka Jain wrote:
This change is not backward-compatible, is it?
York
>>> Yes, It is backward compatible. As per updated board designs and the
>> manufactured boards, GPIO programming is required only for LS2081ARDB
>> boards.
>>
>> Priyanka,
>>
>> I
For EFI boot GPT partition table support is needed as well
as the part command and also the SPL needs to fallback to
other boot methods after parse the SPL header.
Signed-off-by: Frank Kunz
---
:100644 100644 f56e45e727... 33674cf1ea... M
configs/socfpga_de0_nano_soc_defconfig
configs/socfpg
On 08/07/2017 11:31 PM, Z.q. Hou wrote:
> Hi York,
>
> Thanks a lot for your comments!
>
>> -Original Message-
>> From: York Sun
>> Sent: 2017年8月8日 5:18
>> To: Z.q. Hou ; u-boot@lists.denx.de
>> Subject: Re: [PATCH] fsl-lsch2: csu: correct the workaround A-010315
>>
>> On 07/03/2017 03:07
This enables EFI support for DE0-nano-SoC distro boot.
Tested on openSUSE openSUSE Tumbleweed ARM JeOS image.
Signed-off-by: Frank Kunz
---
Changes in v3: Adaption to distroboot changes in mainline
Frank Kunz (1):
arm: socfpga: Configuration for EFI boot on DE0-nano-SoC
configs/socfpga_de0_n
On Wed, Jun 21, 2017 at 3:31 AM, wrote:
> From: Stefan Chulski
>
> TX drain in transmit procedure could cause issues due
> to race between drain procedure and transmition of descriptor
> between AGGR TXQ and physical TXQ.
> TXQ be cleared before moving to Linux by stop procedure.
TXQ be cleared
On Wed, Jun 21, 2017 at 3:31 AM, wrote:
> From: Stefan Chulski
>
> Set BM poll size once during priv probe and do not
> overwrite it during port probe procedure. Pool is common for
> all CP ports.
>
> Change-Id: Icf8c2be3f9cc653c132365e918044713accef335
> Signed-off-by: Stefan Chulski
> Reviewe
On 08/08/2017 06:43 AM, Marcel Ziswiler wrote:
From: Marcel Ziswiler
Allow optionally bringing up the Apalis type specific 4 lane PCIe port
as well as the PCIe switch as found on the Apalis Evaluation board. In
order to avoid violating the PCIe reset timing do this by overriding the
tegra_pcie_
On 08/08/2017 06:42 AM, Marcel Ziswiler wrote:
From: Marcel Ziswiler
Introduce a weak tegra_pcie_board_port_reset() function by default
calling the existing tegra_pcie_port_reset() function. Additionally add
a tegra_pcie_port_index_of_port() function to retrieve the specific PCIe
port index if
On 08/07/2017 11:56 PM, Xiaowei Bao wrote:
> Hi York,
>
> I will pay attention to the case of the case in commit message.
>
> This patch is for some special reset times for longer pcie devices, in this
> case, the pcie device may on polling compliance state, the RC considers the
> pcie device i
On Wed, Jun 21, 2017 at 3:31 AM, wrote:
> From: Stefan Chulski
>
> Remove IRQ configuration from u-boot PP driver.
> U-BOOT don't use interupts and coniguration of IRQ in u-boot
interupts -> interrupts
coniguration -> configuration
u-boot -> U-Boot
> caused crushes in Linux interupt shared mod
On Wed, Jun 21, 2017 at 3:31 AM, wrote:
> From: Stefan Chulski
>
> MVPP22 driver support 64 Bit arch and require BM pool
> high address configuration.
>
> Change-Id: I04417b8cc081ea75e43b230d5ba1cc5c0071ce25
> Signed-off-by: Stefan Chulski
> Reviewed-on: http://vgitil04.il.marvell.com:8080/3996
On Wed, Jun 21, 2017 at 3:31 AM, wrote:
> From: Stefan Chulski
>
> MBUS driver were replaced by AXI in PPv22 and relevant
> only for PPv21.
>
> Change-Id: Iafb42f121d0ad2d8bc99a42e7ed671cd7b754b42
> Signed-off-by: Stefan Chulski
> Reviewed-on: http://vgitil04.il.marvell.com:8080/39965
> Tested-
On Wed, Jun 21, 2017 at 3:31 AM, wrote:
> From: Stefan Chulski
>
> U-boot use single physical tx queue with size 16 descriptors.
> So aggregated tx queue size should be equal to physical tx queue
> and cpu descriptor chunk(number of descriptors delivered from
> physical tx queue to aggregated tx
On Wed, Jun 21, 2017 at 3:31 AM, wrote:
> From: Stefan Chulski
>
> Issue:
> BM counters were overran by probe that called per Network interface and
overran -> overrun
> caused release of wrong number of buffers during remove procedure.
>
> Fix:
> Add CP level flags to call init and remove proc
On Wed, Jun 21, 2017 at 3:31 AM, wrote:
> From: Stefan Chulski
>
> This patch enable padding of packets shorter than 64B in TX(set by default).
enable -> enables
> Disabling of padding cause crushes on MACCIATO board.
cause -> causes
crushes -> crashes
> Regarding to GoP instruction padding
Hi Stefan (and Stefan),
On Tue, Aug 8, 2017 at 7:05 AM, Stefan Roese wrote:
> Hi Joe,
>
> On 11.07.2017 10:04, Stefan Roese wrote:
>>
>> On 21.06.2017 10:31, stef...@malvell.com wrote:
Huh? Sent from a typo email address? That's pretty tedious. I
recommend fixing your git config. And if that's f
On Wed, Jun 21, 2017 at 3:31 AM, wrote:
> From: Stefan Chulski
>
> This WA for mdio issue. U-boot 2017 don't have mdio driver
> and on MACHIATOBin board ports from CP1 connected to mdio on
> CP0. WA is to get mdio address from phy handler parent base address.
> WA should be removed after mdio dr
On Wed, Jun 21, 2017 at 3:31 AM, wrote:
> From: Stefan Chulski
>
> This patch add GPIO configuration support in mvpp2x driver.
> Driver will handle 10G SFP gpio reset and SFP TX disable. GPIO pins should
> be set in device tree.
>
> Change-Id: I3165545b276a3590399d1ac66b1e20d4544212c6
> Signed-o
On Tue, Aug 8, 2017 at 10:03 AM, Rob Clark wrote:
> I suppose special case handling in efi_load_image() wouldn't be too
> bad. It won't fix every theoretical problem on armv7 without
> unaligned access disabled.
>
s/disabled/enabled/
BR,
-R
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On Tue, Aug 8, 2017 at 9:33 AM, Mark Kettenis wrote:
>> From: Rob Clark
>> Date: Tue, 8 Aug 2017 08:54:26 -0400
>>
>> On Tue, Aug 8, 2017 at 8:26 AM, Mark Kettenis
>> wrote:
>> >> From: Rob Clark
>> >> Date: Mon, 7 Aug 2017 18:18:50 -0400
>> >>
>> >> On Mon, Aug 7, 2017 at 5:14 PM, Mark Ketten
The 512 MB DDR version of SOM's use CS0 and CS1. CS1 is not correctly
setup in the pin muxing. This causes erratic behavior on suspend/resume
This fix has been tested on both 256 and 512 MB DDR versions.
Signed-off-by: Adam Ford
diff --git a/board/logicpd/omap3som/omap3logic.c
b/board/logicp
Masahiro & Tom,
the proposed fix is at
https://patchwork.ozlabs.org/patch/799172/
Thanks,
Phil.
> On 07 Aug 2017, at 16:05, Tom Rini wrote:
>
> On Mon, Aug 07, 2017 at 10:48:12AM +0200, Dr. Philipp Tomsich wrote:
>> +Tom
>>
>> Ok, so the problem is 'scripts/setlocalversion’, which doe
Moving SPL_LDSCRIPT to Kconfig triggered an unfortunate attempt of
command substitution, as the sourced auto.conf may include $(ARCH)
which tries to execute a command 'ARCH'.
This showed up as a warning similar to the following:
include/config/auto.conf: line 209: ARCH: command not found
This ch
On Tuesday 08 August 2017 10:27 AM, Chris Packham wrote:
> "jedec,spi-nor" is used by Linux for many boards with spi flash. In fact
> according to the binding documentation this must be included for any SPI
> NOR flash that can be identified by the JEDEC READ ID opcode (0x9F).
> Make device trees
> From: Rob Clark
> Date: Tue, 8 Aug 2017 08:54:26 -0400
>
> On Tue, Aug 8, 2017 at 8:26 AM, Mark Kettenis wrote:
> >> From: Rob Clark
> >> Date: Mon, 7 Aug 2017 18:18:50 -0400
> >>
> >> On Mon, Aug 7, 2017 at 5:14 PM, Mark Kettenis
> >> wrote:
> >> >> From: Alexander Graf
> >> >> Date: Mon,
Hi Tom,
The following changes since commit eaa90e5df2a4a1cb12fb73571978a9379242d0b5:
common/env_embedded.c: rename PPCENV/PPCTEXT macros (2017-08-04
20:38:39 -0400)
are available in the git repository at:
git://git.denx.de/u-boot-x86.git
for you to fetch changes up to 6a5691e297fc44a7c963b
On Tue, Aug 8, 2017 at 6:06 PM, Bin Meng wrote:
> On Tue, Aug 8, 2017 at 5:52 PM, Stefan Roese wrote:
>> This defconfig uses the PCIe x4 binary blobs from the congatec BIOS.
>>
>> Signed-off-by: Stefan Roese
>> Cc: Simon Glass
>> Cc: Bin Meng
>> ---
>> v5:
>> - SPI NOR chips removed because of
On Tue, Aug 8, 2017 at 6:06 PM, Bin Meng wrote:
> On Tue, Aug 8, 2017 at 5:52 PM, Stefan Roese wrote:
>> - Disable debug UART
>> - Enable more partition support
>>
>> Signed-off-by: Stefan Roese
>> Cc: Simon Glass
>> Cc: Bin Meng
>> ---
>> v5:
>> - SPI NOR chips removed because of imply in boa
On Tue, Aug 8, 2017 at 6:06 PM, Bin Meng wrote:
> On Tue, Aug 8, 2017 at 5:52 PM, Stefan Roese wrote:
>> This patch adds the common header include file theadorable-x86-common.h
>> for the theadorable-x86 targets to define all common options and the
>> default environment.
>>
>> Signed-off-by: Ste
On Tue, Aug 8, 2017 at 6:06 PM, Bin Meng wrote:
> On Tue, Aug 8, 2017 at 5:52 PM, Stefan Roese wrote:
>> - Enable ACPI resume support
>> - Disable debug UART
>> - Enable Spansion and Winbond SPI flash support
>> - Move VGA BIOS binary address to enable bigger U-Boot images
>>
>> Signed-off-by: St
On Tue, Aug 8, 2017 at 6:06 PM, Bin Meng wrote:
> On Tue, Aug 8, 2017 at 5:52 PM, Stefan Roese wrote:
>> This patch adds the infrastructure to define different config headers
>> with different configurations and default environment for the baseboards
>> that can now be selected via Kconfig. The n
On Tue, Aug 8, 2017 at 7:44 PM, Stefan Roese wrote:
> On 08.08.2017 13:35, Bin Meng wrote:
>>
>> When CONFIG_EFI_PARTITION is not set, the following build error is
>> seen in arch/x86/lib/acpi_s3.c:
>>
>>error: expected declaration specifiers or '...' before '*' token
>>static void asmlink
On Tue, Aug 8, 2017 at 6:06 PM, Bin Meng wrote:
> On Tue, Aug 8, 2017 at 5:52 PM, Stefan Roese wrote:
>> This patch adds the infrastructure to define different config headers
>> with different configurations and default environment for the baseboards
>> that can now be selected via Kconfig. The n
commit f1896c45cb2f: spl: make SPL and normal u-boot stage use independent
SYS_MALLOC_F_LEN
introduced independent SYS_MALLOC_F_LEN for SPL and U-Boot.
Use it on the smartweb board, as above commit broke
the smartweb board.
Signed-off-by: Heiko Schocher
---
configs/smartweb_defconfig | 1 +
i
On Tue, Aug 8, 2017 at 8:26 AM, Mark Kettenis wrote:
>> From: Rob Clark
>> Date: Mon, 7 Aug 2017 18:18:50 -0400
>>
>> On Mon, Aug 7, 2017 at 5:14 PM, Mark Kettenis
>> wrote:
>> >> From: Alexander Graf
>> >> Date: Mon, 7 Aug 2017 21:19:37 +0100
>> >>
>> >> For AArch64 things are different. Ther
On 08/05/2017 11:45 PM, Simon Glass wrote:
Add some documentation for the live device tree support in U-Boot. This
was missing from the initial series.
Signed-off-by: Simon Glass
Suggested-by: Lukasz Majewski
---
doc/driver-model/livetree.txt | 272 ++
From: Marcel Ziswiler
Add some more comments describing the various PCIe ports available.
Signed-off-by: Marcel Ziswiler
---
arch/arm/dts/tegra30-apalis.dts | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/dts/tegra30-apalis.dts b/arch/arm/dts/tegra30-apalis.dts
index 0b84dae..
This series addresses a PCIe reliability issue as observed on Apalis T30
related to a PCIe reset timing violation.
This series depends on Simon's work available at u-boot-dm/master plus
my previous series "move apalis t30/tk1, colibri t20/t30 to livetree"
and "fix apalis-tk1 pcie gigabit ethernet
From: Marcel Ziswiler
Fix optional Apalis type specific 4 lane PCIe port 0 and Apalis PCIe
port 1 pin muxing.
Signed-off-by: Marcel Ziswiler
---
board/toradex/apalis_t30/pinmux-config-apalis_t30.h | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/board/toradex/a
From: Marcel Ziswiler
Allow optionally bringing up the Apalis type specific 4 lane PCIe port
as well as the PCIe switch as found on the Apalis Evaluation board. In
order to avoid violating the PCIe reset timing do this by overriding the
tegra_pcie_board_port_reset() function. Note however that bo
This series addresses a gigabit Ethernet reliability issue as observed
on Apalis TK1 related to a PCIe reset timing violation.
This series depends on Simon's work available at u-boot-dm/master plus
my previous series "move apalis t30/tk1, colibri t20/t30 to livetree".
This series is available at
From: Marcel Ziswiler
Fix ldo_get_enable() and ldo_set_enable() functions for LDOs with an
index > 7. Turns out there are actually two separate AS3722_LDO_CONTROL
registers AS3722_LDO_CONTROL0 and AS3722_LDO_CONTROL1. Actually make use
of both. While at it also actually use the enable parameter o
From: Marcel Ziswiler
As the AS3722 GPIO0 is also a not connected on our Apalis TK1 module
explicitly configure it to high-impedance as well.
Signed-off-by: Marcel Ziswiler
Reviewed-by: Simon Glass
---
Changes in v2:
- Add Simon's reviewed-by.
arch/arm/dts/tegra124-apalis.dts | 6 +++---
1
From: Marcel Ziswiler
It turns out that the current PCIe reset implementation in the PCIe
board init function is not quite working reliably due to PCIe reset
timing violations. Fix this by overriding the
tegra_pcie_board_port_reset() function.
Also allow optionally bringing up the PCIe switch as
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