Re: [U-Boot] [PATCH] ARM: zynq: Add support for SYZYGY Hub board

[Michal Simek]

On 12.9.2017 20:05, Tom McLeod wrote:
> Add the Zynq-based SYZYGY Hub board from Opal Kelly. The board
> contains a Xilinx Zynq xc7z012s SoC, 1GB DDR3 RAM, and supports
> booting from SD.
> 
> Signed-off-by: Tom McLeod 
> ---
>  arch/arm/dts/Makefile  |1 +
>  arch/arm/dts/zynq-syzygy-hub.dts   |   72 ++
>  board/opalkelly/zynq/MAINTAINERS   |6 +
>  board/opalkelly/zynq/Makefile  |9 +
>  board/opalkelly/zynq/board.c   |1 +
>  .../opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c  | 1078 
> 
>  .../opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h  |  103 ++

Can you please look at board/topic/zynq/* and try to minimalize these
ps7_init* files?
At least remove functions related to silicon v1/v2?

+   if (si_ver == PCW_SILICON_VERSION_1) {
+   ps7_mio_init_data = ps7_mio_init_data_1_0;
+   ps7_pll_init_data = ps7_pll_init_data_1_0;
+   ps7_clock_init_data = ps7_clock_init_data_1_0;
+   ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+   ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+   } else if (si_ver == PCW_SILICON_VERSION_2) {
+   ps7_mio_init_data = ps7_mio_init_data_2_0;
+   ps7_pll_init_data = ps7_pll_init_data_2_0;
+   ps7_clock_init_data = ps7_clock_init_data_2_0;
+   ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+   ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+   } else {





>  configs/syzygy_hub_defconfig   |   57 ++
>  include/configs/syzygy_hub.h   |   72 ++
>  9 files changed, 1399 insertions(+)
>  create mode 100644 arch/arm/dts/zynq-syzygy-hub.dts
>  create mode 100644 board/opalkelly/zynq/MAINTAINERS
>  create mode 100644 board/opalkelly/zynq/Makefile
>  create mode 100644 board/opalkelly/zynq/board.c
>  create mode 100644 board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
>  create mode 100644 board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h
>  create mode 100644 configs/syzygy_hub_defconfig
>  create mode 100644 include/configs/syzygy_hub.h
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 1d6cee2..c15d94f 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -126,6 +126,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
>   zynq-zc706.dtb \
>   zynq-zed.dtb \
>   zynq-zybo.dtb \
> + zynq-syzygy-hub.dtb \

as I see we should sort it :-)

>   zynq-microzed.dtb \
>   zynq-picozed.dtb \
>   zynq-topic-miami.dtb \
> diff --git a/arch/arm/dts/zynq-syzygy-hub.dts 
> b/arch/arm/dts/zynq-syzygy-hub.dts
> new file mode 100644
> index 000..c98ef01
> --- /dev/null
> +++ b/arch/arm/dts/zynq-syzygy-hub.dts
> @@ -0,0 +1,72 @@
> +/*
> + * SYZYGY Hub DTS
> + *
> + *  Copyright (C) 2011 - 2015 Xilinx
> + *  Copyright (C) 2017 Opal Kelly Inc.
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +/dts-v1/;
> +/include/ "zynq-7000.dtsi"
> +
> +/ {
> + model = "SYZYGY Hub";
> + compatible = "xlnx,zynq-7000";


compatible string should contain also information about your board.
It means you should record your prefix in Linux kernel first and then
use it here.

compatible = "opalkelly,syzygy-hub-vXX", "opalkelly,syzygy-hub",
"xlnx,zynq-7000";

The rest is good.

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP SoCs




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Re: [U-Boot] [PATCH v2 15/19] arm: socfpga: Add support to memory allocation in SPL

[Chee, Tien Fong]

On Sel, 2017-09-26 at 12:37 +0200, Marek Vasut wrote:
> On 09/26/2017 07:06 AM, Chee, Tien Fong wrote:
> > 
> > On Isn, 2017-09-25 at 11:21 +0200, Marek Vasut wrote:
> > > 
> > > On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> > > > 
> > > > 
> > > > From: Tien Fong Chee 
> > > > 
> > > > Add support to memory allocation in SPL for preparation to
> > > > enable
> > > > FAT
> > > > in SPL. Memory allocation is needed by FAT to work properly.
> > > > 
> > > > Signed-off-by: Tien Fong Chee 
> > > Gen 5 does have malloc support in SPL, so what's the deal here ?
> > > 
> > For FAT to work properly in Arria 10 SPL, SPL malloc need to be
> > enabled,
> It is already enabled on Gen 5
> 
I think i have confused you, this patch is for getting the malloc area
mapping to Arria 10 SRAM memory correctly. I will improve the commit
message.
> > 
> > and the min of SPL malloc size is 0x2000.
> Where did you find about this minimum ? That can be configured ...
> 
I having issue to boot u-boot successful(Hung or reset), after debuging
through debugger, just found that 0x2000 is min required.
> > 
> > FAT needed in Arria
> > 10 SPL, because u-boot.img is stored in FAT partition.
> It can also be stored on ext partition (which is preferred, patent-
> wise)
> 
> > 
> > > 
> > > > 
> > > > 
> > > > ---
> > > >  include/configs/socfpga_common.h | 23 ++-
> > > >  1 file changed, 22 insertions(+), 1 deletion(-)
> > > > 
> > > > diff --git a/include/configs/socfpga_common.h
> > > > b/include/configs/socfpga_common.h
> > > > index 7549ee8..9b6719e 100644
> > > > --- a/include/configs/socfpga_common.h
> > > > +++ b/include/configs/socfpga_common.h
> > > > @@ -280,17 +280,34 @@ unsigned int
> > > > cm_get_qspi_controller_clk_hz(void);
> > > >  /*
> > > >   * SPL
> > > >   *
> > > > - * SRAM Memory layout:
> > > > + * SRAM Memory layout for gen 5:
> > > >   *
> > > >   * 0x_ .. Start of SRAM
> > > >   * 0x_ .. Top of stack (grows down)
> > > >   * 0x_ .. Malloc area
> > > >   * 0x_ .. Global Data
> > > >   * 0x_FF00 .. End of SRAM
> > > > + *
> > > > + * SRAM Memory layout for Arria 10:
> > > > + * 0xFFE0_ .. Start of SRAM (bottom)
> > > > + * 0xFFEx_ .. Top of stack (grows down to bottom)
> > > > + * 0xFFEy_ .. Malloc area (grows up to top)
> > > > + * 0xFFEz_ .. Global Data
> > > > + * 0xFFE3_ .. End of SRAM (top)
> > > >   */
> > > >  #define CONFIG_SPL_FRAMEWORK
> > > >  #define CONFIG_SPL_TEXT_BASE   CONFIG_SYS_INIT_RA
> > > > M_AD
> > > > DR
> > > >  #define CONFIG_SPL_MAX_SIZECONFIG_SYS_INIT_RAM
> > > > _SIZ
> > > > E
> > > > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > > +/* SPL memory allocation configuration, it is required by FAT
> > > > feature */
> > > > +#ifndef CONFIG_SYS_SPL_MALLOC_START
> > > > +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x2000
> > > > +#define CONFIG_SYS_SPL_MALLOC_START(CONFIG_SYS_INIT_RA
> > > > M_SI
> > > > ZE - \
> > > > +    GENERATED_GBL_DATA_SI
> > > > ZE -
> > > > \
> > > > +    CONFIG_SYS_SPL_MALLOC
> > > > _SIZ
> > > > E + \
> > > > +    CONFIG_SYS_INIT_RAM_A
> > > > DDR)
> > > > +#endif
> > > > +#endif
> > > >  
> > > >  /* SPL SDMMC boot support */
> > > >  #ifdef CONFIG_SPL_MMC_SUPPORT
> > > > @@ -320,7 +337,11 @@ unsigned int
> > > > cm_get_qspi_controller_clk_hz(void);
> > > >  /*
> > > >   * Stack setup
> > > >   */
> > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > >  #define CONFIG_SPL_STACK   CONFIG_SYS_INIT_SP_ADD
> > > > R
> > > > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > > +#define CONFIG_SPL_STACK   (CONFIG_SYS_SPL_MALLOC
> > > > _STA
> > > > RT - 1)
> > > > +#endif
> > > >  
> > > >  /* Extra Environment */
> > > >  #ifndef CONFIG_SPL_BUILD
> > > > 
> 
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Re: [U-Boot] [PATCH] mmc: uniphier-sd: Update the file to match V3 patchset

[Jaehoon Chung]

On 09/27/2017 03:05 AM, Marek Vasut wrote:
> Old version of the uniphier-sd 64bit IO support patchset V1 was
> applied by the maintainer, update the uniphier-sd.c with the
> changes from the V3 of the patchset.
> 
> Signed-off-by: Marek Vasut 
> Cc: Masahiro Yamada 
> Cc: Jaehoon Chung 

Sorry for it, I just picked from patchwork in my box.
Thanks for sending this patch. Next time, i will do more carefully.

Best Regards,
Jaehoon Chung

> ---
>  drivers/mmc/uniphier-sd.c | 83 
> ---
>  1 file changed, 42 insertions(+), 41 deletions(-)
> 
> diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c
> index 0786ad0d5f..3c52161067 100644
> --- a/drivers/mmc/uniphier-sd.c
> +++ b/drivers/mmc/uniphier-sd.c
> @@ -135,7 +135,7 @@ struct uniphier_sd_priv {
>  #define UNIPHIER_SD_CAP_64BITBIT(3)  /* Controller is 64bit 
> */
>  };
>  
> -static u64 uniphier_sd_readq(struct uniphier_sd_priv *priv, const u32 reg)
> +static u64 uniphier_sd_readq(struct uniphier_sd_priv *priv, unsigned int reg)
>  {
>   if (priv->caps & UNIPHIER_SD_CAP_64BIT)
>   return readq(priv->regbase + (reg << 1));
> @@ -144,7 +144,7 @@ static u64 uniphier_sd_readq(struct uniphier_sd_priv 
> *priv, const u32 reg)
>  }
>  
>  static void uniphier_sd_writeq(struct uniphier_sd_priv *priv,
> -const u64 val, const u32 reg)
> +u64 val, unsigned int reg)
>  {
>   if (priv->caps & UNIPHIER_SD_CAP_64BIT)
>   writeq(val, priv->regbase + (reg << 1));
> @@ -152,7 +152,7 @@ static void uniphier_sd_writeq(struct uniphier_sd_priv 
> *priv,
>   writeq(val, priv->regbase + reg);
>  }
>  
> -static u32 uniphier_sd_readl(struct uniphier_sd_priv *priv, const u32 reg)
> +static u32 uniphier_sd_readl(struct uniphier_sd_priv *priv, unsigned int reg)
>  {
>   if (priv->caps & UNIPHIER_SD_CAP_64BIT)
>   return readl(priv->regbase + (reg << 1));
> @@ -161,7 +161,7 @@ static u32 uniphier_sd_readl(struct uniphier_sd_priv 
> *priv, const u32 reg)
>  }
>  
>  static void uniphier_sd_writel(struct uniphier_sd_priv *priv,
> -const u32 val, const u32 reg)
> +u32 val, unsigned int reg)
>  {
>   if (priv->caps & UNIPHIER_SD_CAP_64BIT)
>   writel(val, priv->regbase + (reg << 1));
> @@ -246,7 +246,7 @@ static int uniphier_sd_wait_for_irq(struct udevice *dev, 
> unsigned int reg,
>   return 0;
>  }
>  
> -static int uniphier_sd_pio_read_one_block(struct udevice *dev, u32 **pbuf,
> +static int uniphier_sd_pio_read_one_block(struct udevice *dev, char *pbuf,
> uint blocksize)
>  {
>   struct uniphier_sd_priv *priv = dev_get_priv(dev);
> @@ -264,36 +264,33 @@ static int uniphier_sd_pio_read_one_block(struct 
> udevice *dev, u32 **pbuf,
>*/
>   uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2);
>  
> - if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) {
> - if (priv->caps & UNIPHIER_SD_CAP_64BIT) {
> + if (priv->caps & UNIPHIER_SD_CAP_64BIT) {
> + u64 *buf = (u64 *)pbuf;
> + if (likely(IS_ALIGNED((uintptr_t)buf, 8))) {
>   for (i = 0; i < blocksize / 8; i++) {
> - u64 data;
> - data = uniphier_sd_readq(priv,
> -  UNIPHIER_SD_BUF);
> - *(*pbuf)++ = data;
> - *(*pbuf)++ = data >> 32;
> + *buf++ = uniphier_sd_readq(priv,
> +UNIPHIER_SD_BUF);
>   }
>   } else {
> - for (i = 0; i < blocksize / 4; i++) {
> - u32 data;
> - data = uniphier_sd_readl(priv, UNIPHIER_SD_BUF);
> - *(*pbuf)++ = data;
> - }
> - }
> - } else {
> - if (priv->caps & UNIPHIER_SD_CAP_64BIT) {
>   for (i = 0; i < blocksize / 8; i++) {
>   u64 data;
>   data = uniphier_sd_readq(priv,
>UNIPHIER_SD_BUF);
> - put_unaligned(data, (*pbuf)++);
> - put_unaligned(data >> 32, (*pbuf)++);
> + put_unaligned(data, buf++);
> + }
> + }
> + } else {
> + u32 *buf = (u32 *)pbuf;
> + if (likely(IS_ALIGNED((uintptr_t)buf, 4))) {
> + for (i = 0; i < blocksize / 4; i++) {
> + *buf++ = uniphier_sd_readl(priv,
> +  

Re: [U-Boot] [PATCH v2 10/19] arm: socfpga: Rename the gen5 sdram driver to more specific name

[Chee, Tien Fong]

On Sel, 2017-09-26 at 12:33 +0200, Marek Vasut wrote:
> On 09/26/2017 10:23 AM, Chee, Tien Fong wrote:
> > 
> > On Isn, 2017-09-25 at 11:15 +0200, Marek Vasut wrote:
> > > 
> > > On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> > > > 
> > > > 
> > > > From: Tien Fong Chee 
> > > > 
> > > > Current sdram driver is only applied to gen5 device, hence it
> > > > is
> > > > better
> > > > to rename sdram driver to more specific name which is related
> > > > to
> > > > gen5
> > > > device.
> > > > 
> > > > Signed-off-by: Tien Fong Chee 
> > > > ---
> > > >  arch/arm/mach-socfpga/include/mach/sdram.h | 434 +--
> > > > 
> > > > --
> > > >  .../include/mach/{sdram.h => sdram_gen5.h} |   6 +-
> > > >  drivers/ddr/altera/Makefile|   2 +-
> > > >  drivers/ddr/altera/{sdram.c => sdram_gen5.c}   |   0
> > > >  4 files changed, 8 insertions(+), 434 deletions(-)
> > > >  copy arch/arm/mach-socfpga/include/mach/{sdram.h =>
> > > > sdram_gen5.h}
> > > > (99%)
> > > >  rename drivers/ddr/altera/{sdram.c => sdram_gen5.c} (100%)
> > > > 
> > > > diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > b/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > index b11228f..4a9754e 100644
> > > > --- a/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > +++ b/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > @@ -1,5 +1,5 @@
> > > >  /*
> > > > - * Copyright Altera Corporation (C) 2014-2015
> > > > + * Copyright (C) 2017 Intel Corporation 
> > > Retain the old copyright ?
> > > 
> > Okay.
> > > 
> > > > 
> > > > 
> > > >   *
> > > >   * SPDX-License-Identifier:GPL-2.0+
> > > >   */
> > > > @@ -8,435 +8,9 @@
> > > >  
> > > >  #ifndef __ASSEMBLY__
> > > What's with this massive deletion here ?
> > > 
> > Move to sdram_gen5.h . This header should contain common stuff.
> Then where did the + part go ?
> 
I'm not sure why the patch didn't showing "+" portion, i suspect the
patch use below instead of "+".
 copy arch/arm/mach-socfpga/include/mach/{sdram.h =>
> > > > sdram_gen5.h}> > > > (99%)> > > >  rename
drivers/ddr/altera/{sdram.c => sdram_gen5.c} (100%)
> > 
> > > 
> > > > 
> > > > 
> > > > -unsigned long sdram_calculate_size(void);
> > > > -int sdram_mmr_init_full(unsigned int sdr_phy_reg);
> > > > -int sdram_calibration_full(void);
> > > > -
> > > > -const struct socfpga_sdram_config
> > > > *socfpga_get_sdram_config(void);
> > > > -
> > > > -void socfpga_get_seq_ac_init(const u32 **init, unsigned int
> > > > *nelem);
> > > > -void socfpga_get_seq_inst_init(const u32 **init, unsigned int
> > > > *nelem);
> > > > -const struct socfpga_sdram_rw_mgr_config
> > > > *socfpga_get_sdram_rwmgr_config(void);
> > > [...]
> 
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Re: [U-Boot] [PATCH v2 12/19] arm: socfpga: Add DDR driver for Arria 10

[Chee, Tien Fong]

On Sel, 2017-09-26 at 12:35 +0200, Marek Vasut wrote:
> On 09/26/2017 10:20 AM, Chee, Tien Fong wrote:
> > 
> > On Isn, 2017-09-25 at 11:19 +0200, Marek Vasut wrote:
> > > 
> > > On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> > > > 
> > > > 
> > > > From: Tien Fong Chee 
> > > > 
> > > > Add DDR driver suppport for Arria 10.
> > > > 
> > > > Signed-off-by: Tien Fong Chee 
> > > > ---
> > > >  arch/arm/mach-socfpga/include/mach/sdram.h |   2 +
> > > >  arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 103 ++-
> > > >  drivers/ddr/altera/sdram_arria10.c | 735
> > > > +
> > > >  3 files changed, 839 insertions(+), 1 deletion(-)
> > > >  create mode 100644 drivers/ddr/altera/sdram_arria10.c
> > > > 
> > > > diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > b/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > index 4a9754e..b833fc2 100644
> > > > --- a/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > +++ b/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > @@ -10,6 +10,8 @@
> > > >  
> > > >  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > >  #include 
> > > > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > > +#include 
> > > >  #endif
> > > >  
> > > >  #endif
> > > > diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> > > > b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> > > > index 1d7b7c1..7af9431 100644
> > > > --- a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> > > > +++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> > > > @@ -1,5 +1,5 @@
> > > >  /*
> > > > - * Copyright (C) 2015-2017 Intel Corporation 
> > > > + * Copyright (C) 2017 Intel Corporation 
> > > >   *
> > > >   * SPDX-License-Identifier:GPL-2.0
> > > >   */
> > > > @@ -8,6 +8,7 @@
> > > >  #define _SOCFPGA_SDRAM_ARRIA10_H_
> > > >  
> > > >  #ifndef __ASSEMBLY__
> > > > +int ddr_calibration_sequence(void);
> > > >  
> > > >  struct socfpga_ecc_hmc {
> > > >     u32 ip_rev_id;
> > > > @@ -204,6 +205,106 @@ struct socfpga_io48_mmr {
> > > >     u32 niosreserve1;
> > > >     u32 niosreserve2;
> > > >  };
> > > > +
> > > > +union dramaddrw_reg {
> > > > +   struct {
> > > > +   u32 cfg_col_addr_width:5;
> > > > +   u32 cfg_row_addr_width:5;
> > > > +   u32 cfg_bank_addr_width:4;
> > > > +   u32 cfg_bank_group_addr_width:2;
> > > > +   u32 cfg_cs_addr_width:3;
> > > > +   u32 reserved:13;
> > > > +   };
> > > Use regular macros for bitfields, not this crap.
> > > 
> > Why regular macros is prefered? Above implementation improve
> > readability, simplify the implementation and saving memory.
> Because that's how U-Boot does it (and the above afair breaks on
> different endianness).
> 
Okay.
> > 
> > > 
> > > > 
> > > > 
> > > > +   u32 word;
> > > > +};
> > > > +
> > > > +union ctrlcfg0_reg {
> > > > +   struct {
> > > > +   u32 cfg_mem_type:4;
> > > > +   u32 cfg_dimm_type:3;
> > > > +   u32 cfg_ac_pos:2;
> > > > +   u32 cfg_ctrl_burst_len:5;
> > > > +   u32 reserved:18;  /* Other fields unused */
> > > > +   };
> > > > +   u32 word;
> > > > +};
> > > [...]
> [...]
> 
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Re: [U-Boot] Antwort: Re: QSPI "sf probe ...", "sf read ..." on Altera SoC FPGA

[Hannes Schmelzer]

On 09/22/2017 02:20 PM, Clément Péron wrote:

Sorry these are my local commits you can find them here :

https://patchwork.ozlabs.org/patch/765992/
https://patchwork.ozlabs.org/patch/765996/
https://patchwork.ozlabs.org/patch/765997/
https://patchwork.ozlabs.org/patch/765998/

Hi,
just tested this on my cyclone5 board, but unfortunately without success.

---
U-Boot SPL 2017.09-00354-g824def8 (Sep 27 2017 - 06:47:19)
()
Hit any key to stop autoboot:  0
=> sf probe
SF: Detected n25q512 with page size 256 Bytes, erase size 64 KiB, total 
64 MiB

### ERROR ### Please RESET the board ###


same behavior as before.

But the good news are, that a colleague of mine successfully brought up 
a custom board with this patch.

Prior he had trouble in SPL accessing the flash.

I will poke him to give some "tested-by" credits on this.

cheers,
Hannes



2017-09-22 14:12 GMT+02:00 Clément Péron :

Hi,

I got also somme issue with my QSPI on CycmoneV and u-boot 2017.07
I cherry-picked commits from  Jason Rush :
b90ce1c29023abe730d2b4174294bdc09acef3e0
836a0278476be94c95ff084f81c2302fc5c0265c
b0eac7e0d1e4817388543b58d30b322d0bac49a8

Also i forgot to put the
"u-boot,dm-pre-reloc;" in my device tree in the qspi node.

Now my QSPI is working fine except the sf unlock / lock
I have remove the "clear BP# bits" in the mtd/spi/spi_flash.c

Hope this can help you

Regards,
Clement

2017-09-06 8:10 GMT+02:00 Hannes Schmelzer :

Hi Jagan,


On 09/04/2017 08:22 AM, Hannes Schmelzer wrote:

"U-Boot"  schrieb am 01.09.2017 16:39:03:
 wrote:

Hi Eldor,

just found your post in the mailinglist.

https://lists.denx.de/pipermail/u-boot/2016-December/276491.html

Reason why i'm searched there is, that i've now excactly same problem

as

you.

Can you give some details, issue came-up while 'sf probe' or 'sf read' ?

Hi Jagan,
please have a look into the weblink to the denx mailing list server.
I have basically same trouble as eldor reported the days ago.

A simple 'sf probe' ends up in a
### ERROR ### Please RESET the board ###
Interesting detail is, that the information about the flash (type, size,
...) is printed out quite before the "hang".

On wednesday i have the next time-slot to access the socfpga devkit board.
So i could bring in more details if necessary.

as told few days ago, i've now again access to my socfpga devkit board.
Here comes the console output:

---
U-Boot SPL 2017.09-rc4-00023-g84a4206 (Sep 06 2017 - 08:02:35)
/home/schmelzerh/work/u-boot/drivers/ddr/altera/sequencer.c: Preparing to
start memory calibration
/home/schmelzerh/work/u-boot/drivers/ddr/altera/sequencer.c: CALIBRATION
PASSED
/home/schmelzerh/work/u-boot/drivers/ddr/altera/sequencer.c: Calibration
complete
Trying to boot from MMC1
spl: partition error


U-Boot 2017.09-rc4-00023-g84a4206 (Sep 06 2017 - 08:02:35 +0200)

CPU:   Altera SoCFPGA Platform
FPGA:  Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
BOOT:  SD/MMC Internal Transceiver (3.0V)
Watchdog enabled
I2C:   ready
DRAM:  1 GiB
MMC:   dwmmc0@ff704000: 0
*** Warning - bad CRC, using default environment

In:serial
Out:   serial
Err:   serial
Model: Altera SOCFPGA Cyclone V SoC Development Kit
Net:
Error: ethernet@ff702000 address not set.
No ethernet found.
Hit any key to stop autoboot:  0
=> sf probe
SF: Detected n25q512 with page size 256 Bytes, erase size 64 KiB, total 64
MiB
### ERROR ### Please RESET the board ###


Afterwards the board does some reset (about 20sec. later).


cheers,
Hannes
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Re: [U-Boot] [PATCH v2 16/19] arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10

[Chee, Tien Fong]

On Sel, 2017-09-26 at 12:37 +0200, Marek Vasut wrote:
> On 09/26/2017 06:42 AM, Chee, Tien Fong wrote:
> > 
> > On Isn, 2017-09-25 at 11:23 +0200, Marek Vasut wrote:
> > > 
> > > On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> > > > 
> > > > 
> > > > From: Tien Fong Chee 
> > > > 
> > > > Enhance preloader header with both additional program length
> > > > and
> > > > program
> > > > entry offset attributes, which offset is relative to the start
> > > > of
> > > > program
> > > > header.
> > > > 
> > > > Signed-off-by: Tien Fong Chee 
> > > > ---
> > > >  arch/arm/mach-socfpga/include/mach/boot0.h | 11 +--
> > > >  1 file changed, 9 insertions(+), 2 deletions(-)
> > > > 
> > > > diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h
> > > > b/arch/arm/mach-socfpga/include/mach/boot0.h
> > > > index 22d9e7f..33c9368 100644
> > > > --- a/arch/arm/mach-socfpga/include/mach/boot0.h
> > > > +++ b/arch/arm/mach-socfpga/include/mach/boot0.h
> > > > @@ -11,8 +11,15 @@
> > > >     .balignl 64,0xf33db33f;
> > > >  
> > > >     .word   0x1337c0d3; /* SoCFPGA preloader
> > > > validation word */
> > > > -   .word   0xc01df00d; /* Version, flags,
> > > > length
> > > > */
> > > > -   .word   0xcafec0d3; /* Checksum, zero-pad
> > > > */
> > > > +   .word   0xc01df00d; /* Header
> > > > length(2B),flags(1B),version(1B) */
> > > > +#ifndef CONFIG_TARGET_SOCFPGA_GEN5
> > > > +   .word   0xfeedface; /* Program length(4B) */
> > > Keep this indent intact, then it won't generate these crappy -
> > > entries.
> > > 
> > Are you saying to keep the comment indent intact, and allign with
> > 1st
> > comment  /* SoCFPGA preloader validation word */ ?
> Just look at the diff and make sure that it only changes the relevant
> parts, not extras due to indent changes.
> 
Not get you, which particular change is due to indent changes only?
Some changes are for re-writing more descriptive comment. And some new
adding header attributes to support Arria 10.
> > 
> > > 
> > > > 
> > > > 
> > > > +   .word   0xf00dcafe; /*
> > > > +    * Program entry
> > > > offset(4B),relative
> > > > to
> > > > +    * the start of program header
> > > > +    */
> > > > +#endif
> > > > +   .word   0xcafec0d3; /* Simple
> > > > checksum(2B),spare offset(2B) */
> > > >     nop;
> > > >  
> > > >     b reset;/* SoCFPGA jumps here */
> > > > 
> 
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Re: [U-Boot] [PATCH v2 17/19] arm: socfpga: Adding clock frequency info for U-boot

[Chee, Tien Fong]

On Isn, 2017-09-25 at 11:23 +0200, Marek Vasut wrote:
> On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> > 
> > From: Tien Fong Chee 
> > 
> > Clock frequency info is required in U-boot.
> > 
> > Signed-off-by: Tien Fong Chee 
> I want a TB on Gen 5
> 
Okay.
> > 
> > ---
> >  arch/arm/mach-socfpga/board.c | 6 ++
> >  1 file changed, 6 insertions(+)
> > 
> > diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-
> > socfpga/board.c
> > index 965f9dc..a00f63b 100644
> > --- a/arch/arm/mach-socfpga/board.c
> > +++ b/arch/arm/mach-socfpga/board.c
> > @@ -8,7 +8,10 @@
> >  
> >  #include 
> >  #include 
> > +#include 
> >  #include 
> > +#include 
> > +#include 
> >  #include 
> >  
> >  #include 
> > @@ -26,6 +29,9 @@ int board_init(void)
> >     /* Address of boot parameters for ATAG (if ATAG is used)
> > */
> >     gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
> >  
> > +   /* configuring the clock based on handoff */
> > +   cm_basic_init(gd->fdt_blob);
> > +
> >     return 0;
> >  }
> >  
> > 
> 
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Re: [U-Boot] [PATCH v2 19/19] arm: socfpga: Enable SPL loading U-boot to DDR and booting U-boot

[Chee, Tien Fong]

On Sel, 2017-09-26 at 12:38 +0200, Marek Vasut wrote:
> On 09/26/2017 06:31 AM, Chee, Tien Fong wrote:
> > 
> > On Isn, 2017-09-25 at 11:24 +0200, Marek Vasut wrote:
> > > 
> > > On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> > > > 
> > > > 
> > > > From: Tien Fong Chee 
> > > > 
> > > > Enable SPL loading U-boot from SDMMC to DDR and booting U-boot.
> > > This patch seems to be doing more than just one thing ...
> > > 
> > I can split into two patches:
> > 1) Enable DDR up by configuring FPGA so SPL able loading U-boot to
> > DDR
> > 2) Setting up configs so SPL can boot U-boot from FAT.
> Split it so that one patch does one thing.
> 
Okay.
> > 
> > > 
> > > > 
> > > > 
> > > > Signed-off-by: Tien Fong Chee 
> > > > ---
> > > >  arch/arm/mach-socfpga/spl.c   | 55
> > > > +
> > > >  common/spl/spl_mmc.c  |  2 +-
> > > >  configs/socfpga_arria10_defconfig | 57
> > > > ++-
> > > >  include/spl.h |  2 ++
> > > >  4 files changed, 108 insertions(+), 8 deletions(-)
> > > > 
> > > > diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-
> > > > socfpga/spl.c
> > > > index aba116d..9b381bb 100644
> > > > --- a/arch/arm/mach-socfpga/spl.c
> > > > +++ b/arch/arm/mach-socfpga/spl.c
> > > > @@ -15,6 +15,7 @@
> > > >  #include 
> > > >  #include 
> > > >  #include 
> > > > +#include 
> > > >  #include 
> > > >  #include 
> > > >  #include 
> > > > @@ -22,6 +23,10 @@
> > > >  #include 
> > > >  #include 
> > > >  #include 
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > > >  #include 
> > > >  #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > >  #include 
> > > > @@ -29,6 +34,9 @@
> > > >  
> > > >  DECLARE_GLOBAL_DATA_PTR;
> > > >  
> > > > +#define BSIZE  4096
> > > > +#define PERIPH_RBF 0
> > > > +
> > > >  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > >  static struct pl310_regs *const pl310 =
> > > >     (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
> > > > @@ -197,6 +205,12 @@ void board_init_f(ulong dummy)
> > > >  #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > >  void spl_board_init(void)
> > > >  {
> > > > +   int rval = 0;
> > > > +   int len = 0;
> > > > +   u32 buffer[BSIZE] __aligned(ARCH_DMA_MINALIGN);
> > > > +   struct spl_boot_device bootdev;
> > > > +   fpga_fs_info fpga_fsinfo;
> > > > +
> > > >     /* configuring the clock based on handoff */
> > > >     cm_basic_init(gd->fdt_blob);
> > > >     WATCHDOG_RESET();
> > > > @@ -214,6 +228,47 @@ void spl_board_init(void)
> > > >  
> > > >     /* Add device descriptor to FPGA device table */
> > > >     socfpga_fpga_add();
> > > > +
> > > > +   bootdev.boot_device = spl_boot_device();
> > > > +
> > > > +   if (BOOT_DEVICE_MMC1 == bootdev.boot_device) {
> > > > +   struct mmc *mmc = NULL;
> > > > +   int err = 0;
> > > > +
> > > > +   spl_mmc_find_device(,
> > > > bootdev.boot_device);
> > > > +
> > > > +   err = mmc_init(mmc);
> > > > +
> > > > +   if (err) {
> > > > +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
> > > > +   printf("spl: mmc init failed with
> > > > error:
> > > > %d\n", err);
> > > > +#endif
> > > > +   }
> > > > +
> > > > +   fpga_fsinfo.dev_part = (char
> > > > *)get_cff_devpart(gd-
> > > > > 
> > > > > fdt_blob,
> > > > +   
> > > >  &
> > > > len);
> > > > +
> > > > +   fpga_fsinfo.filename = (char
> > > > *)get_cff_filename(gd->fdt_blob,
> > > > +   
> > > >  &
> > > > len,
> > > > +   
> > > > PE
> > > > RIPH_RBF);
> > > > +
> > > > +   fpga_fsinfo.interface = "mmc";
> > > > +
> > > > +   fpga_fsinfo.fstype = FS_TYPE_FAT;
> > > > +   } else {
> > > > +   printf("Invalid boot device!\n");
> > > > +   return;
> > > > +   }
> > > > +
> > > > +   /* Program peripheral RBF */
> > > > +   if (fpga_fsinfo.filename && fpga_fsinfo.dev_part &&
> > > > (len >
> > > > 0))
> > > > +   rval = fpga_fsload(0, buffer, BSIZE,
> > > > _fsinfo);
> > > > +
> > > > +   if (rval > 0) {
> > > > +   config_pins(gd->fdt_blob, "shared");
> > > > +
> > > > +   ddr_calibration_sequence();
> > > > +   }
> > > >  }
> > > >  
> > > >  void board_init_f(ulong dummy)
> > > > diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
> > > > index b26..159443f 100644
> > > > --- a/common/spl/spl_mmc.c
> > > > +++ b/common/spl/spl_mmc.c
> > > > @@ -113,7 +113,7 @@ static int spl_mmc_get_device_index(u32
> > > > boot_device)
> > > >     return -ENODEV;
> > > >  }
> > > >  
> > > > -static int 

Re: [U-Boot] [PATCH v2 02/19] doc: dtbinding: Description on FPGA RBF properties at Arria 10 FPGA manager

[Chee, Tien Fong]

On Sel, 2017-09-26 at 12:30 +0200, Marek Vasut wrote:
> On 09/26/2017 10:54 AM, Chee, Tien Fong wrote:
> > 
> > On Isn, 2017-09-25 at 11:00 +0200, Marek Vasut wrote:
> > > 
> > > On 09/25/2017 10:39 AM, tien.fong.c...@intel.com wrote:
> > > > 
> > > > 
> > > > From: Tien Fong Chee 
> > > > 
> > > > This patch adds description on properties about location of
> > > > FPGA
> > > > RBFs are
> > > > stored, type and functionality of RBF used to configure FPGA.
> > > > 
> > > > Signed-off-by: Tien Fong Chee 
> > > Why does this patch have different tags than 1/19 ? Please keep
> > > things
> > > consistent ...
> > > 
> > Not get you. What's you means for tags?
> ARM: socfpga: , not the random doc: dtbinding: .
> Heck, the first and second patch change the same file, yet have
> different tags, why ?
> 
I ported patch 01 from Linux, so i keep everything intact. For patch
02, i put doc:dtbinding because i think that is more descriptive to the
file i changed.
I can change to ARM:socfpga .
> > 
> > > 
> > > > 
> > > > ---
> > > >  doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
> > > > | 11
> > > > +++
> > > >  1 file changed, 11 insertions(+)
> > > > 
> > > > diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-
> > > > fpga-
> > > > mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-
> > > > fpga-
> > > > mgr.txt
> > > > index 2fd8e7a..7abb746 100644
> > > > --- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-
> > > > mgr.txt
> > > > +++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-
> > > > mgr.txt
> > > > @@ -7,6 +7,14 @@ Required properties:
> > > > - The second index is for writing FPGA
> > > > configuration data.
> > > >  - resets : Phandle and reset specifier for the device's
> > > > reset.
> > > >  - clocks : Clocks used by the device.
> > > > +- bitstream_periph : FPGA peripheral raw binary file which is
> > > > used
> > > > to
> > > > + initialize FPGA IOs, PLL, IO48 and DDR.
> > > > +- bitstream_core : FPGA core raw binary file contains FPGA
> > > > design
> > > > which is used
> > > > +   to program FPGA CRAM and ERAM.
> > > > +- bitstream_devpart : Partition of flash device where
> > > > bitstream
> > > > files are
> > > > +      stored.
> > > > +   - dev is flash device
> > > > number,
> > > > part is flash
> > > > + device partition.
> > > >  
> > > >  Example:
> > > >  
> > > > @@ -16,4 +24,7 @@ Example:
> > > >        0xffcfe400 0x20>;
> > > >     clocks = <_mp_clk>;
> > > >     resets = < FPGAMGR_RESET>;
> > > > +   bitstream_periph =
> > > > "ghrd_10as066n2.periph.rbf.mkimage";
> > > > +   bitstream_core =
> > > > "ghrd_10as066n2.core.rbf.mkimage";
> > > > +   bitstream_devpart = "0:1";
> > > >     };
> > > > 
> 
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[U-Boot] [PATCH] fs/ext4/ext4fs.c: Free dirnode in error path of ext4fs_ls

[Tom Rini]

As reported by Coverity, we did not free dirnode in the case of failure.
Do so now.

Reported-by: Coverity (CID: 131221)
Cc: Stefan Brüns 
Signed-off-by: Tom Rini 
---
 fs/ext4/ext4fs.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c
index 081509dbb4db..b0c7303aa410 100644
--- a/fs/ext4/ext4fs.c
+++ b/fs/ext4/ext4fs.c
@@ -167,6 +167,7 @@ int ext4fs_ls(const char *dirname)
  FILETYPE_DIRECTORY);
if (status != 1) {
printf("** Can not find directory. **\n");
+   ext4fs_free_node(dirnode, _root->diropen);
return 1;
}
 
-- 
1.9.1

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[U-Boot] [PATCH] tools/fit_image.c: Update some return code paths

[Tom Rini]

Coverity has found some problems with the return paths in parts of this
code.  We have a case where we were going to the wrong part of the
unwind (open() failed so we cannot close the fd), a case where we were
only free()ing our buf on the error path and finally a case where we did
not munmap in the failure path.

Reported-by: Coverity (CID: 138492, 138495, 143064)
Signed-off-by: Tom Rini 
---
 tools/fit_image.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/tools/fit_image.c b/tools/fit_image.c
index 4dc8bd886245..c6026567f3a6 100644
--- a/tools/fit_image.c
+++ b/tools/fit_image.c
@@ -372,7 +372,7 @@ static int fit_build(struct image_tool_params *params, 
const char *fname)
if (fd < 0) {
fprintf(stderr, "%s: Can't open %s: %s\n",
params->cmdname, fname, strerror(errno));
-   goto err;
+   goto err_buf;
}
ret = write(fd, buf, size);
if (ret != size) {
@@ -501,6 +501,7 @@ static int fit_extract_data(struct image_tool_params 
*params, const char *fname)
ret = -EIO;
goto err;
}
+   free(buf);
close(fd);
return 0;
 
@@ -601,6 +602,7 @@ static int fit_import_data(struct image_tool_params 
*params, const char *fname)
ret = 0;
 
 err:
+   munmap(old_fdt, sbuf.st_size);
free(fdt);
close(fd);
return ret;
-- 
1.9.1

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Re: [U-Boot] u-boot Boot issue about rk3188

[Andy Yan]

Hi Pawel:


On 2017年09月26日 19:34, Paweł Jarosz wrote:

Hi,


W dniu 25.09.2017 o 12:29, Heiko Stübner pisze:

Hi Andy,

Am Montag, 25. September 2017, 17:45:03 CEST schrieb Andy Yan:

On 2017年09月22日 13:56, Heiko Stuebner wrote:

Am Freitag, 22. September 2017, 08:50:49 CEST schrieb Andy Yan:

Hi Heiko:

On 2017年09月22日 08:24, Andy Yan wrote:

Hi Heiko:

On 2017年09月21日 22:55, Heiko Stübner wrote:

Hi Andy,

Am Donnerstag, 21. September 2017, 22:03:32 CEST schrieb Andy Yan:

Hi Heiko:
I try to boot the upstream u-boot-rockchip branch on my rk3188 
board

with(rock_defconfig)

But I got this error:
early_init()
nit_and_scan() returned error -22
early_init() failed: -22
ERROR ### Please RESET the board ###

the current commit head is: 782088d("rockchip: imply ADC and
SARADC_ROCKCHIP
on supported SoCs") Do you ever meet something like this?

that is very strange. When testing Philipp's branch, I was also
testing the
commit you mention to see if anything broke since I last changed 
u-boot
on my radxa rock. And the above commit started just fine, when 
starting

from an sd-card.

Not sure from which medium you're starting though. But from what I
remember Pawel got nand working in his rk3066 series, but that 
is not

yet merged.


  I boot from emmc, I will go on hack on it.

   I finally can boot it with the rock_defconfig. But the way to

package the tpl spl u-boot a little different.

   cat ${DIR}/out/tpl/u-boot-tpl.bin > tplspl.bin
   truncate -s 1020 tplspl.bin
    sed -i "/^/{1s/^/RK31/}" tplspl.bin
  cat ${DIR}/out/spl/u-boot-spl.bin > spl.bin
  truncate -s %2048 spl.bin
  cat spl.bin >> tplspl.bin
    Then the tplspl.bin + u-boot.bin should package by

boot_merger(tplsplb.in for FLashData, u-boot.bin for FlashBoot) from

rockchip downstream u-boot repo:
  ./tools/boot_merger ./tools/rk_tools/RKBOOT/RK310BMINIALL.ini
    download to emmc by "upgrade_tool ul" command. 
According to our


bootrom code author, the rk31(maybe include rk30) bootrom has a
limitation that the idbblock
couldn't accessed by upgrade_tool wl command.

I do have a script handling that [0]. At least for the sd-card variant
a simple "openssl rc4" works just as well as the legacy boot_merger 
:-)


Heiko

[0]
https://github.com/mmind/u-boot-rockchip/commit/81458bde873d6cf588e082ccf 


556e818f46ad9df

 Is there a way to download the out that generated by[0] to
emmc/flash? It seems that the upgrate_tool can't access 0x40 of the
emmc/nand on rk3188.

you have the @rock-chips.com address, so I'd guess you might even have
the better resources to find out ;-)  .

In any case, as I said I haven't looked at all at the internal 
storage on

my radxarock so far.

But as the rk3066 and rk3188 are so similar I've added Paweł.

@Paweł: you had uboot starting from nand on your rk3066 board, maybe 
you

could describe how you wrote it to the board so maybe Andy can check if
he needs to adapt anything?
Almost all knowledge i had about rk3066 boot process was from Heiko 
and bootrom disassembly.


Andy, do you have any output on serial console ? (TPL, Uboot-spl or 
anything else)
Can you compile u-boot with #define DEBUG in rk3188_common and send 
the output?


    Here is my console output [1] that boot from a nand on rk3188 board.
But I found that the board will reset again and again in spl stage if I 
defined DEBUG in rk3188_common [2]



Also you can check size of u-boot tpl (less than 1kb), u-boot spl + 
tpl (less than sram size on rk3188, i think it's 32KB)? This is 
important as you wont get any output on serial console if you don't 
meet this conditions.
Also on rk3066 bootmerger FlashBoot size + FlashData size should be 
less than 256KB (32KB for FlashData, and the rest for FlashBoot, if 
it's more than 256KB, you get few lines of errors when flashing with 
upgrade_tool and might have no output on serial console)


Bellow is my binary blob size. And I got a knowledge that the safe size 
of  FlashBoot  + FlashData shoud be less than 128kb(some flashed can up 
to 256, but some may not).


-rwxrwxr-x 1 andy andy 788  u-boot-tpl.bin
-rwxrwxr-x 1 andy andy 15956 u-boot-spl.bin
-rw-rw-r-- 1 andy andy 98249 u-boot.bin



One more thing ... to boot from usb with openssl rc4 method on rk3066 
i think only one back to bootrom is needed, two if you are booting 
from nand.



[1]
tpl-1
Returning to boot ROM...
tpl-2
spl
first data training fail!

U-Boot SPL 2017.09-00107-g99c4c38-dirty (Sep 27 2017 - 08:46:48)
Returning to boot ROM...


U-Boot 2017.09-00107-g99c4c38-dirty (Sep 27 2017 - 08:46:48 +0800)

Model: Radxa Rock
DRAM:  2 GiB
MMC:
MMC Device 0 not found
*** Warning - No MMC card found, using default environment

In:    serial@20064000
Out:   serial@20064000
Err:   serial@20064000
Model: Radxa Rock
=>



[2]
tpl-1
Returning to boot ROM...
tpl-2
spl
spl_early_init()
malloc_simple: size=18, ptr=18, limit=2000: 10085ff0
malloc_simple: size=54, ptr=6c, limit=2000: 10086008
malloc_simple: 

[U-Boot] [PATCH] usb: kbd: Don't fail with iomux

[Rob Clark]

stdin might not be set, which would cause iomux_doenv() to fail
therefore causing probe_usb_keyboard() to fail.  Furthermore if we do
have iomux enabled, the sensible thing (in terms of user experience)
would be to simply add ourselves to the list of stdin devices.

This fixes an issue with usbkbd on dragonboard410c with distro-
bootcmd, where stdin is not set (so stdinname is null).

Signed-off-by: Rob Clark 
---
Somehow this patch was dropped on the floor.  I don't remember
which version # this is up to, search the list if you care.  But
this is the latest.  I only noticed it was missing because u-boot
crashes when you boot with usb-keyboard plugged in (at least on
db410c) without it.  So someone please apply this patch before it
gets lost again.

 common/usb_kbd.c  | 46 +++---
 include/console.h |  2 --
 2 files changed, 31 insertions(+), 17 deletions(-)

diff --git a/common/usb_kbd.c b/common/usb_kbd.c
index a323d72a36..4c3ad95fca 100644
--- a/common/usb_kbd.c
+++ b/common/usb_kbd.c
@@ -516,23 +516,39 @@ static int probe_usb_keyboard(struct usb_device *dev)
return error;
 
stdinname = env_get("stdin");
-#if CONFIG_IS_ENABLED(CONSOLE_MUX)
-   error = iomux_doenv(stdin, stdinname);
-   if (error)
-   return error;
-#else
-   /* Check if this is the standard input device. */
-   if (strcmp(stdinname, DEVNAME))
-   return 1;
+   if (CONFIG_IS_ENABLED(CONSOLE_MUX)) {
+   char *devname = DEVNAME;
+   char *newstdin = NULL;
+   /*
+* stdin might not be set yet.. either way, with console-
+* mux the sensible thing to do is add ourselves to the
+* list of stdio devices:
+*/
+   if (stdinname && !strstr(stdinname, DEVNAME)) {
+   newstdin = malloc(strlen(stdinname) +
+   strlen(","DEVNAME) + 1);
+   sprintf(newstdin, "%s,"DEVNAME, stdinname);
+   stdinname = newstdin;
+   } else if (!stdinname) {
+   stdinname = devname;
+   }
+   error = iomux_doenv(stdin, stdinname);
+   free(newstdin);
+   if (error)
+   return error;
+   } else {
+   /* Check if this is the standard input device. */
+   if (strcmp(stdinname, DEVNAME))
+   return 1;
 
-   /* Reassign the console */
-   if (overwrite_console())
-   return 1;
+   /* Reassign the console */
+   if (overwrite_console())
+   return 1;
 
-   error = console_assign(stdin, DEVNAME);
-   if (error)
-   return error;
-#endif
+   error = console_assign(stdin, DEVNAME);
+   if (error)
+   return error;
+   }
 
return 0;
 }
diff --git a/include/console.h b/include/console.h
index cea29ed6dc..7dfd36d7d1 100644
--- a/include/console.h
+++ b/include/console.h
@@ -57,8 +57,6 @@ int console_announce_r(void);
 /*
  * CONSOLE multiplexing.
  */
-#ifdef CONFIG_CONSOLE_MUX
 #include 
-#endif
 
 #endif
-- 
2.13.5

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[U-Boot] [PATCH] cmd/time.c: Initialize 'repeatable' variable

[Tom Rini]

We cannot leave this uninitialized, set it to 0.

Reported-by: Coverity (CID: 144426)
Signed-off-by: Tom Rini 
---
 cmd/time.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/cmd/time.c b/cmd/time.c
index de57e3b9dd5e..2cd8b1a5 100644
--- a/cmd/time.c
+++ b/cmd/time.c
@@ -28,7 +28,7 @@ static int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char 
* const argv[])
 {
ulong cycles = 0;
int retval = 0;
-   int repeatable;
+   int repeatable = 0;
 
if (argc == 1)
return CMD_RET_USAGE;
-- 
1.9.1

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[U-Boot] [PATCH] cmd/pxe.c: Rework initrd and bootargs handling slightly

[Tom Rini]

For the initrd portion of handling our bootm arguments we do not have a
sufficiently long enough buffer for some improbable 64bit cases.  Expand
this buffer to allow for a 64bit address and almost 256MB initrd to be
used.  Make use of strncpy/strncat when constructing the values here
since we know what the worst case valid values are, length wise.

Similarly for bootargs themselves, we need to make use of strlen/sizeof
and strncpy/strncat to ensure that we don't overflow bootargs itself.

Cc: Simon Glass 
Cc: Alexander Graf 
Reported-by: Coverity (CID: 131256)
Signed-off-by: Tom Rini 
---
 cmd/pxe.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/cmd/pxe.c b/cmd/pxe.c
index c5a770a26995..a62cbe192a32 100644
--- a/cmd/pxe.c
+++ b/cmd/pxe.c
@@ -616,7 +616,7 @@ static int label_localboot(struct pxe_label *label)
 static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label *label)
 {
char *bootm_argv[] = { "bootm", NULL, NULL, NULL, NULL };
-   char initrd_str[22];
+   char initrd_str[28];
char mac_str[29] = "";
char ip_str[68] = "";
int bootm_argc = 2;
@@ -648,9 +648,9 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label 
*label)
}
 
bootm_argv[2] = initrd_str;
-   strcpy(bootm_argv[2], env_get("ramdisk_addr_r"));
+   strncpy(bootm_argv[2], env_get("ramdisk_addr_r"), 18);
strcat(bootm_argv[2], ":");
-   strcat(bootm_argv[2], env_get("filesize"));
+   strncat(bootm_argv[2], env_get("filesize"), 9);
}
 
if (get_relfile_envaddr(cmdtp, label->kernel, "kernel_addr_r") < 0) {
@@ -689,9 +689,9 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label 
*label)
}
 
if (label->append)
-   strcpy(bootargs, label->append);
-   strcat(bootargs, ip_str);
-   strcat(bootargs, mac_str);
+   strncpy(bootargs, label->append, sizeof(bootargs));
+   strncat(bootargs, ip_str, sizeof(bootargs) - strlen(bootargs));
+   strncat(bootargs, mac_str, sizeof(bootargs) - strlen(bootargs));
 
cli_simple_process_macros(bootargs, finalbootargs);
env_set("bootargs", finalbootargs);
-- 
1.9.1

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[U-Boot] [PATCH] cmd/nvedit.c: Update input handling to cover overflow cases

[Tom Rini]

When we have multiple messages provided, we need to be sure that we do
not exceed the length of our 'message' buffer.  In the for loop, make
sure that pos is not larger than message.  Only copy in at most however
much of the message buffer remains.  Finally, if we have not reached the
end of the message buffer, put in a space and NULL, and if we have,
ensure the buffer is now NULL termined.

Reported-by: Coverity (CID: 165116)
Signed-off-by: Tom Rini 
---
 cmd/nvedit.c | 11 +++
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/cmd/nvedit.c b/cmd/nvedit.c
index 4033d90c8e2d..055836cc72d1 100644
--- a/cmd/nvedit.c
+++ b/cmd/nvedit.c
@@ -393,15 +393,18 @@ int do_env_ask(cmd_tbl_t *cmdtp, int flag, int argc, char 
* const argv[])
sprintf(message, "Please enter '%s': ", argv[1]);
} else {
/* env_ask envname message1 ... messagen [size] */
-   for (i = 2, pos = 0; i < argc; i++) {
+   for (i = 2, pos = 0; i < argc && pos < sizeof(message); i++) {
if (pos)
message[pos++] = ' ';
 
-   strcpy(message + pos, argv[i]);
+   strncpy(message + pos, argv[i], sizeof(message) - pos);
pos += strlen(argv[i]);
}
-   message[pos++] = ' ';
-   message[pos] = '\0';
+   if (pos < sizeof(message) - 1) {
+   message[pos++] = ' ';
+   message[pos] = '\0';
+   } else
+   message[CONFIG_SYS_CBSIZE - 1] = '\0';
}
 
if (size >= CONFIG_SYS_CBSIZE)
-- 
1.9.1

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Re: [U-Boot] [PATCH 06/14] arm: socfpga: stratix10: Add misc support for Stratix10 SoC

[Dinh Nguyen]

On Tue, Sep 19, 2017 at 4:22 AM,   wrote:
> From: Chin Liang See 
>
> Add misc support for Stratix SoC

Just because the file is call misc.c doesn't mean you can just keep the commit
message that simple. Can you add what functions are you adding?

>
> Signed-off-by: Chin Liang See 
> ---
>  arch/arm/mach-socfpga/Makefile   |   1 +
>  arch/arm/mach-socfpga/misc.c |   4 +
>  arch/arm/mach-socfpga/misc_s10.c | 165 
> +++
>  3 files changed, 170 insertions(+)
>  create mode 100644 arch/arm/mach-socfpga/misc_s10.c
>
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
> index 910eb6f..b253914 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -32,6 +32,7 @@ endif
>
>  ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
>  obj-y  += clock_manager_s10.o
> +obj-y  += misc_s10.o
>  obj-y  += reset_manager_s10.o
>  obj-y  += system_manager_s10.o
>  obj-y  += wrap_pinmux_config_s10.o
> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
> index 00eff90..2ea94bc 100644
> --- a/arch/arm/mach-socfpga/misc.c
> +++ b/arch/arm/mach-socfpga/misc.c
> @@ -23,8 +23,10 @@
>
>  DECLARE_GLOBAL_DATA_PTR;
>
> +#ifdef CONFIG_SYS_L2_PL310
>  static const struct pl310_regs *const pl310 =
> (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
> +#endif
>
>  struct bsel bsel_str[] = {
> { "rsvd", "Reserved", },
> @@ -53,6 +55,7 @@ void enable_caches(void)
>  #endif
>  }
>
> +#ifdef CONFIG_SYS_L2_PL310
>  void v7_outer_cache_enable(void)
>  {
> /* Disable the L2 cache */
> @@ -73,6 +76,7 @@ void v7_outer_cache_disable(void)
> /* Disable the L2 cache */
> clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
>  }
> +#endif
>
>  #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
>  defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
> diff --git a/arch/arm/mach-socfpga/misc_s10.c 
> b/arch/arm/mach-socfpga/misc_s10.c
> new file mode 100644
> index 000..b84f055
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/misc_s10.c

This misc_s10.c look very similar to the Gen5 stuff, can you re-use it?

Dinh
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Re: [U-Boot] [PATCH 04/14] arm: socfpga: stratix10: Add Reset Manager driver for Stratix10 SoC

[Dinh Nguyen]

On Tue, Sep 19, 2017 at 4:22 AM,   wrote:
> From: Chin Liang See 
>
> Add Reset Manager driver support for Stratix SoC
>
> Signed-off-by: Chin Liang See 
> ---
>  arch/arm/mach-socfpga/Makefile |   1 +
>  arch/arm/mach-socfpga/include/mach/reset_manager.h |   2 +
>  .../mach-socfpga/include/mach/reset_manager_s10.h  | 116 +
>  arch/arm/mach-socfpga/reset_manager.c  |   5 +
>  arch/arm/mach-socfpga/reset_manager_s10.c  | 140 
> +

I don't see why you need to add a new file for S10? The functionality between
Gen 5 and Stratix10 is identical for the reset manager.

Dinh
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Re: [U-Boot] [PATCH 03/14] arm: socfpga: stratix10: Add Clock Manager driver for Stratix10 SoC

[Dinh Nguyen]

On Tue, Sep 19, 2017 at 4:22 AM,   wrote:
> From: Chin Liang See 
>
> Add Clock Manager driver support for Stratix SoC
>
> Signed-off-by: Chin Liang See 
> ---
>  arch/arm/mach-socfpga/Makefile |   4 +
>  arch/arm/mach-socfpga/clock_manager.c  |   4 +-
>  arch/arm/mach-socfpga/clock_manager_s10.c  | 359 
> +
>  arch/arm/mach-socfpga/include/mach/clock_manager.h |   2 +
>  .../mach-socfpga/include/mach/clock_manager_s10.h  | 202 
>  arch/arm/mach-socfpga/include/mach/handoff_s10.h   |  29 ++
>  arch/arm/mach-socfpga/wrap_pll_config_s10.c|  46 +++
>  7 files changed, 644 insertions(+), 2 deletions(-)
>  create mode 100644 arch/arm/mach-socfpga/clock_manager_s10.c
>  create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
>  create mode 100644 arch/arm/mach-socfpga/include/mach/handoff_s10.h
>  create mode 100644 arch/arm/mach-socfpga/wrap_pll_config_s10.c
>
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
> index 286bfef..e5f9dd7 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -30,6 +30,10 @@ obj-y+= pinmux_arria10.o
>  obj-y  += reset_manager_arria10.o
>  endif
>
> +ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
> +obj-y  += clock_manager_s10.o
> +obj-y  += wrap_pll_config_s10.o
> +endif
>  ifdef CONFIG_SPL_BUILD
>  obj-y  += spl.o
>  ifdef CONFIG_TARGET_SOCFPGA_GEN5
> diff --git a/arch/arm/mach-socfpga/clock_manager.c 
> b/arch/arm/mach-socfpga/clock_manager.c
> index cb6ae03..f9450a4 100644
> --- a/arch/arm/mach-socfpga/clock_manager.c
> +++ b/arch/arm/mach-socfpga/clock_manager.c
> @@ -21,7 +21,7 @@ void cm_wait_for_lock(u32 mask)
> do {
>  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> inter_val = readl(_manager_base->inter) & mask;
> -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +#else
> inter_val = readl(_manager_base->stat) & mask;
>  #endif
> /* Wait for stable lock */
> @@ -52,7 +52,7 @@ int set_cpu_clk_info(void)
>
>  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 100;
> -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +#else
> gd->bd->bi_ddr_freq = 0;
>  #endif
>
> diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c 
> b/arch/arm/mach-socfpga/clock_manager_s10.c
> new file mode 100644
> index 000..a9f9b07
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/clock_manager_s10.c
> @@ -0,0 +1,359 @@
> +/*
> + * Copyright (C) 2016-2017 Intel Corporation 
> + *
> + * SPDX-License-Identifier:GPL-2.0
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static const struct socfpga_clock_manager *clock_manager_base =
> +   (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
> +
> +/*
> + * function to write the bypass register which requires a poll of the
> + * busy bit
> + */
> +static void cm_write_bypass_mainpll(uint32_t val)
> +{
> +   writel(val, _manager_base->main_pll.bypass);
> +   cm_wait_for_fsm();
> +}

Add a new line..

> +static void cm_write_bypass_perpll(uint32_t val)
> +{
> +   writel(val, _manager_base->per_pll.bypass);
> +   cm_wait_for_fsm();
> +}
> +
> +/* function to write the ctrl register which requires a poll of the busy bit 
> */
> +static void cm_write_ctrl(uint32_t val)
> +{
> +   writel(val, _manager_base->ctrl);
> +   cm_wait_for_fsm();
> +}
> +
> +/*
> + * Setup clocks while making no assumptions about previous state of the 
> clocks.
> + *

Remove extra line

> + */
> +void cm_basic_init(const struct cm_config * const cfg)
> +{
> +   uint32_t mdiv, refclkdiv, mscnt, hscnt, vcocalib;
> +
> +   if (cfg == 0)
> +   return;
> +
> +   /* Put all plls in bypass */
> +   cm_write_bypass_mainpll(CLKMGR_BYPASS_MAINPLL_ALL);
> +   cm_write_bypass_perpll(CLKMGR_BYPASS_PERPLL_ALL);
> +
> +   /* setup main PLL dividers */
> +   /* calculate the vcocalib value */

Move the above comment to where vcocalib is getting calculated, or remove.

> +   mdiv = (cfg->main_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &
> +   CLKMGR_FDBCK_MDIV_MASK;
> +   refclkdiv = (cfg->main_pll_pllglob >> 
> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
> +CLKMGR_PLLGLOB_REFCLKDIV_MASK;
> +   mscnt = 200 / (6 + mdiv) / refclkdiv;

Where are these values, 200 and 6 coming from? Should they be a #define?

> +   hscnt = (mdiv + 6) * mscnt / refclkdiv - 9;

Same for 6 and 9 here...

> +   vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
> +  ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<
> +  CLKMGR_VCOCALIB_MSCNT_OFFSET);
> +
> +   writel((cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
> +   ~CLKMGR_PLLGLOB_RST_MASK),
> +   

Re: [U-Boot] [PATCH 02/14] arm: dts: Add dts for Stratix10 SoC

[Dinh Nguyen]

On Tue, Sep 19, 2017 at 4:22 AM,   wrote:
> From: Chin Liang See 
>
> Device tree for Stratix10 SoC
>
> Signed-off-by: Chin Liang See 
> ---
>  arch/arm/dts/Makefile|   3 +-
>  arch/arm/dts/socfpga_stratix10_socdk.dts | 141 
> +++
>  2 files changed, 143 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index fee4680..4cf5fd0 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -171,7 +171,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += 
>   \
> socfpga_cyclone5_sockit.dtb \
> socfpga_cyclone5_socrates.dtb   \
> socfpga_cyclone5_sr1500.dtb \
> -   socfpga_cyclone5_vining_fpga.dtb
> +   socfpga_cyclone5_vining_fpga.dtb\
> +   socfpga_stratix10_socdk.dtb
>
>  dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb  \
> dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb
> diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts 
> b/arch/arm/dts/socfpga_stratix10_socdk.dts
> new file mode 100644
> index 000..484c630
> --- /dev/null
> +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
> @@ -0,0 +1,141 @@
> +/*
> + * Copyright (C) 2016-2017 Intel Corporation 
> + *
> + * SPDX-License-Identifier:GPL-2.0
> + */
> +
> +/dts-v1/;
> +#include "skeleton.dtsi"
> +#include 
> +
> +/ {
> +   model = "Intel SOCFPGA Stratix 10 SoC Development Kit";
> +   compatible = "altr,socfpga-stratix10", "altr,socfpga";
> +
> +   #address-cells = <1>;
> +   #size-cells = <1>;
> +
> +   chosen {
> +   bootargs = "console=ttyS0,115200";
> +   };
> +
> +   aliases {
> +   ethernet0 = 
> +   spi0 = 
> +   };
> +
> +   memory {
> +   name = "memory";
> +   device_type = "memory";
> +   reg = <0x0 0x8000>; /* 2GB */
> +   };
> +
> +   regulator_3_3v: 3-3-v-regulator {
> +   compatible = "regulator-fixed";
> +   regulator-name = "3.3V";
> +   regulator-min-microvolt = <330>;
> +   regulator-max-microvolt = <330>;
> +   };
> +
> +   soc {
> +   #address-cells = <1>;
> +   #size-cells = <1>;
> +   compatible = "simple-bus";
> +   device_type = "soc";
> +   ranges;
> +   u-boot,dm-pre-reloc;
> +
> +   rst: rstmgr@ffd11000 {
> +   #reset-cells = <1>;
> +   compatible = "altr,rst-mgr";
> +   reg = <0xffd11000 0x100>;
> +   altr,modrst-offset = <0x20>;
> +   };

Where are the cpu nodes?

Dinh
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Re: [U-Boot] [PATCH 02/14] arm: dts: Add dts for Stratix10 SoC

[Dinh Nguyen]

On Tue, Sep 19, 2017 at 4:22 AM,   wrote:
> From: Chin Liang See 
>
> Device tree for Stratix10 SoC
>
> Signed-off-by: Chin Liang See 
> ---
>  arch/arm/dts/Makefile|   3 +-
>  arch/arm/dts/socfpga_stratix10_socdk.dts | 141 
> +++
>  2 files changed, 143 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index fee4680..4cf5fd0 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -171,7 +171,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += 
>   \
> socfpga_cyclone5_sockit.dtb \
> socfpga_cyclone5_socrates.dtb   \
> socfpga_cyclone5_sr1500.dtb \
> -   socfpga_cyclone5_vining_fpga.dtb
> +   socfpga_cyclone5_vining_fpga.dtb\
> +   socfpga_stratix10_socdk.dtb
>
>  dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb  \
> dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb
> diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts 
> b/arch/arm/dts/socfpga_stratix10_socdk.dts
> new file mode 100644
> index 000..484c630
> --- /dev/null
> +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
> @@ -0,0 +1,141 @@
> +/*
> + * Copyright (C) 2016-2017 Intel Corporation 
> + *
> + * SPDX-License-Identifier:GPL-2.0
> + */
> +
> +/dts-v1/;
> +#include "skeleton.dtsi"
> +#include 

You don't add the patch for this include file until patch 4/14, which means
the build will fail until patch 4 is applied. You need to move this patch
after 4/14.

> +
> +/ {
> +   model = "Intel SOCFPGA Stratix 10 SoC Development Kit";
> +   compatible = "altr,socfpga-stratix10", "altr,socfpga";
> +
> +   #address-cells = <1>;
> +   #size-cells = <1>;
> +
> +   chosen {
> +   bootargs = "console=ttyS0,115200";
> +   };
> +
> +   aliases {
> +   ethernet0 = 
> +   spi0 = 
> +   };
> +
> +   memory {
> +   name = "memory";
> +   device_type = "memory";
> +   reg = <0x0 0x8000>; /* 2GB */
> +   };
> +
> +   regulator_3_3v: 3-3-v-regulator {
> +   compatible = "regulator-fixed";
> +   regulator-name = "3.3V";
> +   regulator-min-microvolt = <330>;
> +   regulator-max-microvolt = <330>;
> +   };
> +
> +   soc {
> +   #address-cells = <1>;
> +   #size-cells = <1>;
> +   compatible = "simple-bus";
> +   device_type = "soc";
> +   ranges;
> +   u-boot,dm-pre-reloc;
> +
> +   rst: rstmgr@ffd11000 {
> +   #reset-cells = <1>;
> +   compatible = "altr,rst-mgr";
> +   reg = <0xffd11000 0x100>;
> +   altr,modrst-offset = <0x20>;
> +   };
> +
> +   gmac0: ethernet@ff80 {
> +   compatible = "altr,socfpga-stmmac", 
> "snps,dwmac-3.74a", "snps,dwmac";
> +   reg = <0xff80 0x2000>;
> +   interrupts = <0 90 4>;
> +   interrupt-names = "macirq";
> +   mac-address = [00 00 00 00 00 00];
> +   resets = < EMAC0_RESET>;
> +   reset-names = "stmmaceth";
> +   phy-mode = "rgmii";
> +   phy-addr = <0x>; /* probe for phy addr */
> +   max-speed = <1000>;
> +   txd0-skew-ps = <0>; /* -420ps */
> +   txd1-skew-ps = <0>; /* -420ps */
> +   txd2-skew-ps = <0>; /* -420ps */
> +   txd3-skew-ps = <0>; /* -420ps */
> +   rxd0-skew-ps = <420>; /* 0ps */
> +   rxd1-skew-ps = <420>; /* 0ps */
> +   rxd2-skew-ps = <420>; /* 0ps */
> +   rxd3-skew-ps = <420>; /* 0ps */
> +   txen-skew-ps = <0>; /* -420ps */
> +   txc-skew-ps = <1860>; /* 960ps */
> +   rxdv-skew-ps = <420>; /* 0ps */
> +   rxc-skew-ps = <1680>; /* 780ps */

These are PHY properties, which should be in a separate PHY node.

Dinh
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Re: [U-Boot] Issues with mx6 (cubox/wandboard) with 2017.09

[Fabio Estevam]

On Tue, Sep 26, 2017 at 2:50 PM, Peter Robinson  wrote:

> I tested a build with 6.4 from Fedora 25 and I saw the same issue so
> I'm not sure where the problem is coming from but I'm also
> travelling/meetings so haven't had time to dig further into the issue

In the meantime I have also built U-Boot 2017.09 for wandboard with
gcc7.2 from Buildroot and it boots fine.

If you find out more about the problem, just let us know.
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Re: [U-Boot] [PATCH] test/dm: Fix string handling issues in the eth test

[Joe Hershberger]

On Tue, Sep 26, 2017 at 1:08 PM, Tom Rini  wrote:
> Coverity scan has identified potential buffer overruns in these tests.
> Correct this by zeroing our buffer and using strncpy not strcpy.
>
> Reported-by: Coverity (CID: 155462, 155463)
> Cc: Joe Hershberger 
> Cc: Simon Glass 
> Cc: Bin Meng 
> Signed-off-by: Tom Rini 

Reviewed-by: Joe Hershberger 
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[U-Boot] [PATCH v2 13/14] log: test: Add a pytest for logging

[Simon Glass]

Add a test which tries out various filters and options to make sure that
logging works as expected.

Signed-off-by: Simon Glass 
---

Changes in v2:
- Change log levels to match new header
- Only execute log tests if CONFIG_LOG is enabled
- Rename LOGL_WARN to LOGL_WARNING

 MAINTAINERS   |   1 +
 test/py/tests/test_log.py | 107 ++
 2 files changed, 108 insertions(+)
 create mode 100644 test/py/tests/test_log.py

diff --git a/MAINTAINERS b/MAINTAINERS
index ca5224341e..eb420afa8d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -297,6 +297,7 @@ T:  git git://git.denx.de/u-boot.git
 F: common/log.c
 F: cmd/log.c
 F: test/log/log_test.c
+F: test/py/tests/test_log.py
 
 MICROBLAZE
 M: Michal Simek 
diff --git a/test/py/tests/test_log.py b/test/py/tests/test_log.py
new file mode 100644
index 00..bed040b4d7
--- /dev/null
+++ b/test/py/tests/test_log.py
@@ -0,0 +1,107 @@
+# Copyright (c) 2016, Google Inc.
+#
+# SPDX-License-Identifier:  GPL-2.0+
+#
+# U-Boot Verified Boot Test
+
+"""
+This tests U-Boot logging. It uses the 'log test' command with various options
+and checks that the output is correct.
+"""
+
+import pytest
+
+LOGL_FIRST, LOGL_WARNING, LOGL_INFO = (0, 4, 6)
+
+@pytest.mark.buildconfigspec('log')
+def test_log(u_boot_console):
+"""Test that U-Boot logging works correctly."""
+def check_log_entries(lines, mask, max_level=LOGL_INFO):
+"""Check that the expected log records appear in the output
+
+Args:
+lines: iterator containing lines to check
+mask: bit mask to select which lines to check for:
+bit 0: standard log line
+bit 1: _log line
+max_level: maximum log level to expect in the output
+"""
+for i in range(max_level):
+if mask & 1:
+assert 'log %d' % i == lines.next()
+if mask & 3:
+assert '_log %d' % i == lines.next()
+
+def run_test(testnum):
+"""Run a particular test number (the 'log test' command)
+
+Args:
+testnum: Test number to run
+Returns:
+iterator containing the lines output from the command
+"""
+
+with cons.log.section('basic'):
+   output = u_boot_console.run_command('log test %d' % testnum)
+split = output.replace('\r', '').splitlines()
+lines = iter(split)
+assert 'test %d' % testnum == lines.next()
+return lines
+
+def test0():
+lines = run_test(0)
+assert 'error' == lines.next()
+check_log_entries(lines, 3)
+
+def test1():
+lines = run_test(1)
+check_log_entries(lines, 3)
+
+def test2():
+lines = run_test(2)
+assert 'error' == lines.next()
+
+def test3():
+lines = run_test(3)
+check_log_entries(lines, 2)
+
+def test4():
+lines = run_test(4)
+assert next(lines, None) == None
+
+def test5():
+lines = run_test(5)
+check_log_entries(lines, 2)
+
+def test6():
+lines = run_test(6)
+assert 'error' == lines.next()
+check_log_entries(lines, 3)
+
+def test7():
+lines = run_test(7)
+assert 'error' == lines.next()
+check_log_entries(lines, 3, LOGL_WARNING)
+
+def test8():
+lines = run_test(8)
+assert 'error' == lines.next()
+check_log_entries(lines, 3)
+
+def test9():
+lines = run_test(8)
+assert 'error' == lines.next()
+check_log_entries(lines, 3)
+
+# TODO(s...@chromium.org): Consider structuring this as separate tests
+cons = u_boot_console
+test0()
+test1()
+test2()
+test3()
+test4()
+test5()
+test6()
+test7()
+test8()
+test9()
-- 
2.14.1.992.g2c7b836f3a-goog

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[U-Boot] [PATCH v2 12/14] log: sandbox: Enable logging

[Simon Glass]

Enable all logging features on sandbox so that the tests can be run.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v2:
- Change sandbox log level to 6

 configs/sandbox_defconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 93ea6889a0..9637d7098c 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -16,6 +16,8 @@ CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
 CONFIG_SILENT_CONSOLE=y
 CONFIG_PRE_CONSOLE_BUFFER=y
 CONFIG_PRE_CON_BUF_ADDR=0x10
+CONFIG_LOG=y
+CONFIG_LOG_MAX_LEVEL=6
 CONFIG_CMD_CPU=y
 CONFIG_CMD_LICENSE=y
 CONFIG_CMD_BOOTZ=y
@@ -64,6 +66,7 @@ CONFIG_CMD_CBFS=y
 CONFIG_CMD_CRAMFS=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_LOG=y
 CONFIG_MAC_PARTITION=y
 CONFIG_AMIGA_PARTITION=y
 CONFIG_OF_CONTROL=y
-- 
2.14.1.992.g2c7b836f3a-goog

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[U-Boot] [PATCH v2 06/14] Drop the log buffer

[Simon Glass]

This does not appear to be used by any boards. Before introducing a new
log system, remove this old one.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v2: None

 cmd/Makefile  |   1 -
 cmd/log.c | 313 --
 common/board_f.c  |  18 ---
 common/board_r.c  |  25 +--
 common/image.c|   9 --
 common/stdio.c|   6 -
 include/asm-generic/global_data.h |   2 +-
 include/logbuff.h |  49 --
 include/post.h|   4 +-
 post/post.c   |   9 --
 post/tests.c  |   4 -
 scripts/config_whitelist.txt  |   1 -
 12 files changed, 5 insertions(+), 436 deletions(-)
 delete mode 100644 cmd/log.c
 delete mode 100644 include/logbuff.h

diff --git a/cmd/Makefile b/cmd/Makefile
index 2a5b8ce825..1b13d07901 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -75,7 +75,6 @@ obj-$(CONFIG_LED_STATUS_CMD) += legacy_led.o
 obj-$(CONFIG_CMD_LED) += led.o
 obj-$(CONFIG_CMD_LICENSE) += license.o
 obj-y += load.o
-obj-$(CONFIG_LOGBUFFER) += log.o
 obj-$(CONFIG_ID_EEPROM) += mac.o
 obj-$(CONFIG_CMD_MD5SUM) += md5sum.o
 obj-$(CONFIG_CMD_MEMORY) += mem.o
diff --git a/cmd/log.c b/cmd/log.c
deleted file mode 100644
index 7a3bd5cd69..00
--- a/cmd/log.c
+++ /dev/null
@@ -1,313 +0,0 @@
-/*
- * (C) Copyright 2002-2007
- * Detlev Zundel, DENX Software Engineering, d...@denx.de.
- *
- * Code used from linux/kernel/printk.c
- * Copyright (C) 1991, 1992  Linus Torvalds
- *
- * SPDX-License-Identifier:GPL-2.0+
- *
- * Comments:
- *
- * After relocating the code, the environment variable "loglevel" is
- * copied to console_loglevel.  The functionality is similar to the
- * handling in the Linux kernel, i.e. messages logged with a priority
- * less than console_loglevel are also output to stdout.
- *
- * If you want messages with the default level (e.g. POST messages) to
- * appear on stdout also, make sure the environment variable
- * "loglevel" is set at boot time to a number higher than
- * default_message_loglevel below.
- */
-
-/*
- * Logbuffer handling routines
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Local prototypes */
-static void logbuff_putc(struct stdio_dev *dev, const char c);
-static void logbuff_puts(struct stdio_dev *dev, const char *s);
-static int logbuff_printk(const char *line);
-
-static char buf[1024];
-
-/* This combination will not print messages with the default loglevel */
-static unsigned console_loglevel = 3;
-static unsigned default_message_loglevel = 4;
-static unsigned log_version = 1;
-#ifdef CONFIG_ALT_LB_ADDR
-static volatile logbuff_t *log;
-#else
-static logbuff_t *log;
-#endif
-static char *lbuf;
-
-unsigned long __logbuffer_base(void)
-{
-   return CONFIG_SYS_SDRAM_BASE + get_effective_memsize() - LOGBUFF_LEN;
-}
-unsigned long logbuffer_base(void)
-__attribute__((weak, alias("__logbuffer_base")));
-
-void logbuff_init_ptrs(void)
-{
-   unsigned long tag, post_word;
-   char *s;
-
-#ifdef CONFIG_ALT_LB_ADDR
-   log = (logbuff_t *)CONFIG_ALT_LH_ADDR;
-   lbuf = (char *)CONFIG_ALT_LB_ADDR;
-#else
-   log = (logbuff_t *)(logbuffer_base()) - 1;
-   lbuf = (char *)log->buf;
-#endif
-
-   /* Set up log version */
-   s = env_get("logversion");
-   if (s)
-   log_version = (int)simple_strtoul(s, NULL, 10);
-
-   if (log_version == 2)
-   tag = log->v2.tag;
-   else
-   tag = log->v1.tag;
-   post_word = post_word_load();
-#ifdef CONFIG_POST
-   /* The post routines have setup the word so we can simply test it */
-   if (tag != LOGBUFF_MAGIC || (post_word & POST_COLDBOOT))
-   logbuff_reset();
-#else
-   /* No post routines, so we do our own checking*/
-   if (tag != LOGBUFF_MAGIC || post_word != LOGBUFF_MAGIC) {
-   logbuff_reset ();
-   post_word_store (LOGBUFF_MAGIC);
-   }
-#endif
-   if (log_version == 2 && (long)log->v2.start > (long)log->v2.con)
-   log->v2.start = log->v2.con;
-
-   /* Initialize default loglevel if present */
-   s = env_get("loglevel");
-   if (s)
-   console_loglevel = (int)simple_strtoul(s, NULL, 10);
-
-   gd->flags |= GD_FLG_LOGINIT;
-}
-
-void logbuff_reset(void)
-{
-#ifndef CONFIG_ALT_LB_ADDR
-   memset(log, 0, sizeof(logbuff_t));
-#endif
-   if (log_version == 2) {
-   log->v2.tag = LOGBUFF_MAGIC;
-#ifdef CONFIG_ALT_LB_ADDR
-   log->v2.start = 0;
-   log->v2.con = 0;
-   log->v2.end = 0;
-   log->v2.chars = 0;
-#endif
-   } else {
-   log->v1.tag = LOGBUFF_MAGIC;
-#ifdef CONFIG_ALT_LB_ADDR
-   log->v1.dummy = 0;
-   log->v1.start = 0;
-  

[U-Boot] [PATCH v2 04/14] Move debug and logging support to a separate header

[Simon Glass]

Before adding new features, move these definitions to a separate header
to avoid further cluttering common.h.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v2: None

 include/common.h | 64 +
 include/log.h| 79 
 2 files changed, 80 insertions(+), 63 deletions(-)
 create mode 100644 include/log.h

diff --git a/include/common.h b/include/common.h
index aaed131671..459d273389 100644
--- a/include/common.h
+++ b/include/common.h
@@ -42,69 +42,7 @@ typedef volatile unsigned char   vu_char;
 #define CONFIG_SYS_SUPPORT_64BIT_DATA
 #endif
 
-#ifdef DEBUG
-#define _DEBUG 1
-#else
-#define _DEBUG 0
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-#define _SPL_BUILD 1
-#else
-#define _SPL_BUILD 0
-#endif
-
-/* Define this at the top of a file to add a prefix to debug messages */
-#ifndef pr_fmt
-#define pr_fmt(fmt) fmt
-#endif
-
-/*
- * Output a debug text when condition "cond" is met. The "cond" should be
- * computed by a preprocessor in the best case, allowing for the best
- * optimization.
- */
-#define debug_cond(cond, fmt, args...) \
-   do {\
-   if (cond)   \
-   printf(pr_fmt(fmt), ##args);\
-   } while (0)
-
-/* Show a message if DEBUG is defined in a file */
-#define debug(fmt, args...)\
-   debug_cond(_DEBUG, fmt, ##args)
-
-/* Show a message if not in SPL */
-#define warn_non_spl(fmt, args...) \
-   debug_cond(!_SPL_BUILD, fmt, ##args)
-
-/*
- * An assertion is run-time check done in debug mode only. If DEBUG is not
- * defined then it is skipped. If DEBUG is defined and the assertion fails,
- * then it calls panic*( which may or may not reset/halt U-Boot (see
- * CONFIG_PANIC_HANG), It is hoped that all failing assertions are found
- * before release, and after release it is hoped that they don't matter. But
- * in any case these failing assertions cannot be fixed with a reset (which
- * may just do the same assertion again).
- */
-void __assert_fail(const char *assertion, const char *file, unsigned line,
-  const char *function);
-#define assert(x) \
-   ({ if (!(x) && _DEBUG) \
-   __assert_fail(#x, __FILE__, __LINE__, __func__); })
-
-#define error(fmt, args...) do {   \
-   printf("ERROR: " pr_fmt(fmt) "\nat %s:%d/%s()\n",   \
-   ##args, __FILE__, __LINE__, __func__);  \
-} while (0)
-
-#ifndef BUG
-#define BUG() do { \
-   printf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, 
__FUNCTION__); \
-   panic("BUG!"); \
-} while (0)
-#define BUG_ON(condition) do { if (unlikely((condition)!=0)) BUG(); } while(0)
-#endif /* BUG */
+#include 
 
 typedef void (interrupt_handler_t)(void *);
 
diff --git a/include/log.h b/include/log.h
new file mode 100644
index 00..4101a74161
--- /dev/null
+++ b/include/log.h
@@ -0,0 +1,79 @@
+/*
+ * Logging support
+ *
+ * Copyright (c) 2017 Google, Inc
+ * Written by Simon Glass 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __LOG_H
+#define __LOG_H
+
+#ifdef DEBUG
+#define _DEBUG 1
+#else
+#define _DEBUG 0
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define _SPL_BUILD 1
+#else
+#define _SPL_BUILD 0
+#endif
+
+/* Define this at the top of a file to add a prefix to debug messages */
+#ifndef pr_fmt
+#define pr_fmt(fmt) fmt
+#endif
+
+/*
+ * Output a debug text when condition "cond" is met. The "cond" should be
+ * computed by a preprocessor in the best case, allowing for the best
+ * optimization.
+ */
+#define debug_cond(cond, fmt, args...) \
+   do {\
+   if (cond)   \
+   printf(pr_fmt(fmt), ##args);\
+   } while (0)
+
+/* Show a message if DEBUG is defined in a file */
+#define debug(fmt, args...)\
+   debug_cond(_DEBUG, fmt, ##args)
+
+/* Show a message if not in SPL */
+#define warn_non_spl(fmt, args...) \
+   debug_cond(!_SPL_BUILD, fmt, ##args)
+
+/*
+ * An assertion is run-time check done in debug mode only. If DEBUG is not
+ * defined then it is skipped. If DEBUG is defined and the assertion fails,
+ * then it calls panic*( which may or may not reset/halt U-Boot (see
+ * CONFIG_PANIC_HANG), It is hoped that all failing assertions are found
+ * before release, and after release it is hoped that they don't matter. But
+ * in any case these failing assertions cannot be fixed with a reset (which
+ * may just do the same assertion again).
+ */
+void __assert_fail(const char *assertion, const char *file, unsigned int line,
+  const char *function);
+#define assert(x) \
+ 

[U-Boot] [PATCH v2 08/14] log: Add a console driver

[Simon Glass]

It is useful to display log messages on the console. Add a simple driver
to handle this.

Note that this driver outputs to the console, which may be serial or
video. It does not specifically select serial output.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v2:
- Update commit message to explain that this is not just for serial output

 common/Kconfig   | 20 
 common/Makefile  |  1 +
 common/log_console.c | 23 +++
 3 files changed, 44 insertions(+)
 create mode 100644 common/log_console.c

diff --git a/common/Kconfig b/common/Kconfig
index ca4a0f7f9b..7fed04a5fb 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -436,6 +436,26 @@ config SPL_LOG_MAX_LEVEL
6 - detail
7 - debug
 
+config LOG_CONSOLE
+   bool "Allow log output to the console"
+   depends on LOG
+   default y
+   help
+ Enables a log driver which writes log records to the console.
+ Generally the console is the serial port or LCD display. Only the
+ log message is shown - other details like level, category, file and
+ line number are omitted.
+
+config LOG_SPL_CONSOLE
+   bool "Allow log output to the console in SPL"
+   depends on LOG_SPL
+   default y
+   help
+ Enables a log driver which writes log records to the console.
+ Generally the console is the serial port or LCD display. Only the
+ log message is shown - other details like level, category, file and
+ line number are omitted.
+
 endmenu
 
 config DTB_RESELECT
diff --git a/common/Makefile b/common/Makefile
index 9d52c9623c..6405a4c299 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -129,5 +129,6 @@ obj-$(CONFIG_FSL_DDR_INTERACTIVE) += cli_simple.o 
cli_readline.o
 obj-$(CONFIG_CMD_DFU) += dfu.o
 obj-y += command.o
 obj-$(CONFIG_$(SPL_)LOG) += log.o
+obj-$(CONFIG_$(SPL_)LOG_CONSOLE) += log_console.o
 obj-y += s_record.o
 obj-y += xyzModem.o
diff --git a/common/log_console.c b/common/log_console.c
new file mode 100644
index 00..5af73bd8be
--- /dev/null
+++ b/common/log_console.c
@@ -0,0 +1,23 @@
+/*
+ * Logging support
+ *
+ * Copyright (c) 2017 Google, Inc
+ * Written by Simon Glass 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+
+static int log_console_emit(struct log_device *ldev, struct log_rec *rec)
+{
+   puts(rec->msg);
+
+   return 0;
+}
+
+LOG_DRIVER(console) = {
+   .name   = "console",
+   .emit   = log_console_emit,
+};
-- 
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[U-Boot] [PATCH v2 10/14] log: Add a test command

[Simon Glass]

Add a command which exercises the logging system.

Signed-off-by: Simon Glass 
---

Changes in v2:
- Fix function called when test command is selected
- Fix help output for 'log test'
- Rename LOGL_WARN to LOGL_WARNING

 MAINTAINERS |   1 +
 cmd/Kconfig |   3 +-
 cmd/log.c   |   6 ++
 common/Kconfig  |  10 +++
 include/log.h   |   3 +
 test/Makefile   |   1 +
 test/log/Makefile   |   7 ++
 test/log/log_test.c | 204 
 8 files changed, 234 insertions(+), 1 deletion(-)
 create mode 100644 test/log/Makefile
 create mode 100644 test/log/log_test.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 3ef97783c0..ca5224341e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -296,6 +296,7 @@ S:  Maintained
 T: git git://git.denx.de/u-boot.git
 F: common/log.c
 F: cmd/log.c
+F: test/log/log_test.c
 
 MICROBLAZE
 M: Michal Simek 
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 702d4f251f..9d52e4fecc 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1483,7 +1483,8 @@ config CMD_LOG
help
  This provides access to logging features. It allows the output of
  log data to be controlled to a limited extent (setting up the default
- maximum log level for emitting of records).
+ maximum log level for emitting of records). It also provides access
+ to a command used for testing the log system.
 
 config CMD_TRACE
bool "trace - Support tracing of function calls and timing"
diff --git a/cmd/log.c b/cmd/log.c
index 44e04ab16a..abc523b497 100644
--- a/cmd/log.c
+++ b/cmd/log.c
@@ -23,6 +23,9 @@ static int do_log_level(cmd_tbl_t *cmdtp, int flag, int argc,
 
 static cmd_tbl_t log_sub[] = {
U_BOOT_CMD_MKENT(level, CONFIG_SYS_MAXARGS, 1, do_log_level, "", ""),
+#ifdef CONFIG_LOG_TEST
+   U_BOOT_CMD_MKENT(test, 2, 1, do_log_test, "", ""),
+#endif
 };
 
 static int do_log(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@@ -46,6 +49,9 @@ static int do_log(cmd_tbl_t *cmdtp, int flag, int argc, char 
* const argv[])
 #ifdef CONFIG_SYS_LONGHELP
 static char log_help_text[] =
"level - get/set log level\n"
+#ifdef CONFIG_LOG_TEST
+   "log test - run log tests\n"
+#endif
;
 #endif
 
diff --git a/common/Kconfig b/common/Kconfig
index 7fed04a5fb..55d73ad71f 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -456,6 +456,16 @@ config LOG_SPL_CONSOLE
  log message is shown - other details like level, category, file and
  line number are omitted.
 
+config LOG_TEST
+   bool "Provide a test for logging"
+   depends on LOG
+   default y if SANDBOX
+   help
+ This enables a 'log test' command to test logging. It is normally
+ executed from a pytest and simply outputs logging information
+ in various different ways to test that the logging system works
+ correctly with varoius settings.
+
 endmenu
 
 config DTB_RESELECT
diff --git a/include/log.h b/include/log.h
index 9488adc8cb..7f2e84a68b 100644
--- a/include/log.h
+++ b/include/log.h
@@ -268,6 +268,9 @@ struct log_filter {
 #define LOG_DRIVER(_name) \
ll_entry_declare(struct log_driver, _name, log_driver)
 
+/* Handle the 'log test' command */
+int do_log_test(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]);
+
 /**
  * log_add_filter() - Add a new filter to a log device
  *
diff --git a/test/Makefile b/test/Makefile
index 6305afb211..40f2244b79 100644
--- a/test/Makefile
+++ b/test/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_SANDBOX) += command_ut.o
 obj-$(CONFIG_SANDBOX) += compression.o
 obj-$(CONFIG_SANDBOX) += print_ut.o
 obj-$(CONFIG_UT_TIME) += time_ut.o
+obj-$(CONFIG_$(SPL_)LOG) += log/
diff --git a/test/log/Makefile b/test/log/Makefile
new file mode 100644
index 00..b0da8dee28
--- /dev/null
+++ b/test/log/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2017 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_LOG_TEST) += log_test.o
diff --git a/test/log/log_test.c b/test/log/log_test.c
new file mode 100644
index 00..29bfe772f2
--- /dev/null
+++ b/test/log/log_test.c
@@ -0,0 +1,204 @@
+/*
+ * Logging support test program
+ *
+ * Copyright (c) 2017 Google, Inc
+ * Written by Simon Glass 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+
+/* emit some sample log records in different ways, for testing */
+static int log_run(enum log_category_t cat, const char *file)
+{
+   int i;
+
+   debug("debug\n");
+   error("error\n");
+   for (i = LOGL_FIRST; i < LOGL_COUNT; i++) {
+   log(cat, i, "log %d\n", i);
+   _log(cat, i, file, 100 + i, "func", "_log %d\n", i);
+   }
+
+   return 0;
+}
+
+static int log_test(int testnum)
+{
+   int ret;
+
+   printf("test %d\n", testnum);
+   switch (testnum) {
+   case 0: {
+   /* Check a category filter using the 

[U-Boot] [PATCH v2 14/14] log: Add documentation

[Simon Glass]

Add documentation for the log system.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v2:
- Drop the special log() functions from the README

 doc/README.log | 214 +
 1 file changed, 214 insertions(+)
 create mode 100644 doc/README.log

diff --git a/doc/README.log b/doc/README.log
new file mode 100644
index 00..f653fe7d79
--- /dev/null
+++ b/doc/README.log
@@ -0,0 +1,214 @@
+Logging in U-Boot
+=
+
+Introduction
+
+
+U-Boot's internal operation involves many different steps and actions. From
+setting up the board to displaying a start-up screen to loading an Operating
+System, there are many component parts each with many actions.
+
+Most of the time this internal detail is not useful. Displaying it on the
+console would delay booting (U-Boot's primary purpose) and confuse users.
+
+But for digging into what is happening in a particular area, or for debugging
+a problem it is often useful to see what U-Boot is doing in more detail than
+is visible from the basic console output.
+
+U-Boot's logging feature aims to satisfy this goal for both users and
+developers.
+
+
+Logging levels
+--
+
+There are a number logging levels available, in increasing order of verbosity:
+
+   LOGL_EMERG  - Printed before U-Boot halts
+   LOGL_ALERT  - Indicates action must be taken immediate or U-Boot will crash
+   LOGL_CRIT   - Indicates a critical error that will cause boot failure
+   LOGL_ERR- Indicates an error that may cause boot failure
+   LOGL_WARNING- Warning about an unexpected condition
+   LOGL_NOTE   - Important information about progress
+   LOGL_INFO   - Information about normal boot progress
+   LOGL_DEBUG  - Debug information (useful for debugging a driver or subsystem)
+   LOGL_DEBUG_CONTENT  - Debug message showing full message content
+   LOGL_DEBUG_IO   - Debug message showing hardware I/O access
+
+
+Logging category
+
+
+Logging can come from a wide variety of places within U-Boot. Each log message
+has a category which is intended to allow messages to be filtered according to
+their source.
+
+The following main categories are defined:
+
+   LOGC_NONE   - Unknown category (e.g. a debug() statement)
+   UCLASS_...  - Related to a particular uclass (e.g. UCLASS_USB)
+   LOGC_ARCH   - Related to architecture-specific code
+   LOGC_BOARD  - Related to board-specific code
+   LOGC_CORE   - Related to core driver-model support
+   LOGC_DT - Related to device tree control
+
+
+Enabling logging
+
+
+The following options are used to enable logging at compile time:
+
+   CONFIG_LOG  - Enables the logging system
+   CONFIG_MAX_LOG_LEVEL - Max log level to build (anything higher is compiled
+   out)
+   CONFIG_LOG_CONSOLE  - Enable writing log records to the console
+
+If CONFIG_LOG is not set, then no logging will be available.
+
+The above have SPL versions also, e.g. CONFIG_SPL_MAX_LOG_LEVEL.
+
+
+Using DEBUG
+---
+
+U-Boot has traditionally used a #define called DEBUG to enable debugging on a
+file-by-file basis. The debug() macro compiles to a printf() statement if
+DEBUG is enabled, and an empty statement if not.
+
+With logging enabled, debug() statements are interpreted as logging output
+with a level of LOGL_DEBUG and a category of LOGC_NONE.
+
+The logging facilities are intended to replace DEBUG, but if DEBUG is defined
+at the top of a file, then it takes precedence. This means that debug()
+statements will result in output to the console and this output will not be
+logged.
+
+
+Logging destinations
+
+
+If logging information goes nowhere then it serves no purpose. U-Boot provides
+several possible determinations for logging information, all of which can be
+enabled or disabled independently:
+
+   console - goes to stdout
+
+
+Filters
+---
+
+Filters are attached to log drivers to control what those drivers emit. Only
+records that pass through the filter make it to the driver.
+
+Filters can be based on several criteria:
+
+   - maximum log level
+   - in a set of categories
+   - in a set of files
+
+If no filters are attached to a driver then a default filter is used, which
+limits output to records with a level less than CONFIG_LOG_MAX_LEVEL.
+
+
+Logging statements
+--
+
+The main logging function is:
+
+   log(category, level, format_string, ...)
+
+Also debug() and error() will generate log records  - these use LOG_CATEGORY
+as the category, so you should #define this right at the top of the source
+file to ensure the category is correct.
+
+
+Code size
+-
+
+Code size impact depends largely on what is enabled. The following numbers are
+for snow, which is a Thumb-2 board:
+
+This series: adds bss +20.0 data +4.0 rodata +4.0 text +44.0
+CONFIG_LOG: bss -52.0 data +92.0 rodata -635.0 text 

[U-Boot] [PATCH v2 05/14] mtdparts: Correct use of debug()

[Simon Glass]

The debug() macro now evaluates its expression so does not need #ifdef
protection. In fact the current code causes a warning with the new log
implementation. Adjust the code to fix this.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v2: None

 cmd/mtdparts.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/cmd/mtdparts.c b/cmd/mtdparts.c
index 3275eb919b..13677faf4b 100644
--- a/cmd/mtdparts.c
+++ b/cmd/mtdparts.c
@@ -873,15 +873,12 @@ static int device_parse(const char *const mtd_dev, const 
char **ret, struct mtd_
return 1;
}
 
-#ifdef DEBUG
pend = strchr(p, ';');
-#endif
debug("dev type = %d (%s), dev num = %d, mtd-id = %s\n",
id->type, MTD_DEV_TYPE(id->type),
id->num, id->mtd_id);
debug("parsing partitions %.*s\n", (int)(pend ? pend - p : strlen(p)), 
p);
 
-
/* parse partitions */
num_parts = 0;
 
-- 
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[U-Boot] [PATCH v2 09/14] log: Add a 'log level' command

[Simon Glass]

Add a command for adjusting the log level.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v2: None

 cmd/Kconfig  |  7 +++
 cmd/Makefile |  1 +
 cmd/log.c| 55 +++
 3 files changed, 63 insertions(+)
 create mode 100644 cmd/log.c

diff --git a/cmd/Kconfig b/cmd/Kconfig
index d6d130edfa..702d4f251f 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1478,6 +1478,13 @@ config CMD_KGDB
  single-stepping, inspecting variables, etc. This is supported only
  on PowerPC at present.
 
+config CMD_LOG
+   bool "log - Generation, control and access to logging"
+   help
+ This provides access to logging features. It allows the output of
+ log data to be controlled to a limited extent (setting up the default
+ maximum log level for emitting of records).
+
 config CMD_TRACE
bool "trace - Support tracing of function calls and timing"
help
diff --git a/cmd/Makefile b/cmd/Makefile
index 1b13d07901..f09278da24 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -75,6 +75,7 @@ obj-$(CONFIG_LED_STATUS_CMD) += legacy_led.o
 obj-$(CONFIG_CMD_LED) += led.o
 obj-$(CONFIG_CMD_LICENSE) += license.o
 obj-y += load.o
+obj-$(CONFIG_CMD_LOG) += log.o
 obj-$(CONFIG_ID_EEPROM) += mac.o
 obj-$(CONFIG_CMD_MD5SUM) += md5sum.o
 obj-$(CONFIG_CMD_MEMORY) += mem.o
diff --git a/cmd/log.c b/cmd/log.c
new file mode 100644
index 00..44e04ab16a
--- /dev/null
+++ b/cmd/log.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2017 Google, Inc
+ * Written by Simon Glass 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+static int do_log_level(cmd_tbl_t *cmdtp, int flag, int argc,
+   char * const argv[])
+{
+   if (argc > 1)
+   gd->default_log_level = simple_strtol(argv[1], NULL, 10);
+   else
+   printf("Default log level: %d\n", gd->default_log_level);
+
+   return 0;
+}
+
+static cmd_tbl_t log_sub[] = {
+   U_BOOT_CMD_MKENT(level, CONFIG_SYS_MAXARGS, 1, do_log_level, "", ""),
+};
+
+static int do_log(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+   cmd_tbl_t *cp;
+
+   if (argc < 2)
+   return CMD_RET_USAGE;
+
+   /* drop initial "log" arg */
+   argc--;
+   argv++;
+
+   cp = find_cmd_tbl(argv[0], log_sub, ARRAY_SIZE(log_sub));
+   if (cp)
+   return cp->cmd(cmdtp, flag, argc, argv);
+
+   return CMD_RET_USAGE;
+}
+
+#ifdef CONFIG_SYS_LONGHELP
+static char log_help_text[] =
+   "level - get/set log level\n"
+   ;
+#endif
+
+U_BOOT_CMD(
+   log, CONFIG_SYS_MAXARGS, 1, do_log,
+   "log system", log_help_text
+);
-- 
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[U-Boot] [PATCH v2 11/14] log: Plumb logging into the init sequence

[Simon Glass]

Set up logging both before and after relocation.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v2: None

 common/board_f.c  | 5 -
 common/board_r.c  | 2 ++
 common/log.c  | 1 +
 include/asm-generic/global_data.h | 1 +
 4 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/common/board_f.c b/common/board_f.c
index 1e8bf63ec1..e46eceda7d 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -751,6 +751,7 @@ static const init_fnc_t init_sequence_f[] = {
trace_early_init,
 #endif
initf_malloc,
+   log_init,
initf_bootstage,/* uses its own timer, so does not need DM */
initf_console_record,
 #if defined(CONFIG_HAVE_FSP)
@@ -932,8 +933,10 @@ void board_init_f_r(void)
 * The pre-relocation drivers may be using memory that has now gone
 * away. Mark serial as unavailable - this will fall back to the debug
 * UART if available.
+*
+* Do the same with log drivers since the memory may not be available.
 */
-   gd->flags &= ~GD_FLG_SERIAL_READY;
+   gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY);
 #ifdef CONFIG_TIMER
gd->timer = NULL;
 #endif
diff --git a/common/board_r.c b/common/board_r.c
index 02ac43d39c..fb56b7d997 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -703,6 +703,7 @@ static init_fnc_t init_sequence_r[] = {
 #endif
initr_barrier,
initr_malloc,
+   log_init,
initr_bootstage,/* Needs malloc() but has its own timer */
initr_console_record,
 #ifdef CONFIG_SYS_NONCACHED_MEMORY
@@ -899,6 +900,7 @@ void board_init_r(gd_t *new_gd, ulong dest_addr)
 #if !defined(CONFIG_X86) && !defined(CONFIG_ARM) && !defined(CONFIG_ARM64)
gd = new_gd;
 #endif
+   gd->flags &= ~GD_FLG_LOG_READY;
 
 #ifdef CONFIG_NEEDS_MANUAL_RELOC
for (i = 0; i < ARRAY_SIZE(init_sequence_r); i++)
diff --git a/common/log.c b/common/log.c
index a7d9a548f2..c94a3c1759 100644
--- a/common/log.c
+++ b/common/log.c
@@ -238,6 +238,7 @@ int log_init(void)
  (struct list_head *)>log_head);
drv++;
}
+   gd->flags |= GD_FLG_LOG_READY;
gd->default_log_level = LOGL_INFO;
 
return 0;
diff --git a/include/asm-generic/global_data.h 
b/include/asm-generic/global_data.h
index 77755dbb06..73e036d6fd 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -146,5 +146,6 @@ typedef struct global_data {
 #define GD_FLG_RECORD  0x01000 /* Record console  */
 #define GD_FLG_ENV_DEFAULT 0x02000 /* Default variable flag   */
 #define GD_FLG_SPL_EARLY_INIT  0x04000 /* Early SPL init is done  */
+#define GD_FLG_LOG_READY   0x08000 /* Log system is ready for use */
 
 #endif /* __ASM_GENERIC_GBL_DATA_H */
-- 
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[U-Boot] [PATCH v2 03/14] Revert "sandbox: Drop special case console code for sandbox"

[Simon Glass]

While sandbox works OK without the special-case code, it does result in
console output being stored in the pre-console buffer while sandbox starts
up. If there is a crash or a problem then there is no indication of what
is going on.

For ease of debugging it seems better to revert this change also.

This reverts commit d8c6fb8cedbc35eee27730a7fa544e499b3c81cc.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 common/console.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/common/console.c b/common/console.c
index f83528ca60..18457aab3c 100644
--- a/common/console.c
+++ b/common/console.c
@@ -482,6 +482,13 @@ static inline void print_pre_console_buffer(int 
flushpoint) {}
 
 void putc(const char c)
 {
+#ifdef CONFIG_SANDBOX
+   /* sandbox can send characters to stdout before it has a console */
+   if (!gd || !(gd->flags & GD_FLG_SERIAL_READY)) {
+   os_putc(c);
+   return;
+   }
+#endif
 #ifdef CONFIG_DEBUG_UART
/* if we don't have a console yet, use the debug UART */
if (!gd || !(gd->flags & GD_FLG_SERIAL_READY)) {
-- 
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[U-Boot] [PATCH v2 01/14] Revert "sandbox: remove os_putc() and os_puts()"

[Simon Glass]

While sandbox works OK without the special-case code, it does result in
console output being stored in the pre-console buffer while sandbox starts
up. If there is a crash or a problem then there is no indication of what
is going on.

For ease of debugging it seems better to revert this change.

This reverts commit 47b98ad0f6779485d0f0c14f337c3eece273eb54.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 arch/sandbox/cpu/os.c | 11 +++
 include/os.h  | 20 
 2 files changed, 31 insertions(+)

diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c
index 22d6aab534..7243bfc1b1 100644
--- a/arch/sandbox/cpu/os.c
+++ b/arch/sandbox/cpu/os.c
@@ -413,6 +413,17 @@ int os_get_filesize(const char *fname, loff_t *size)
return 0;
 }
 
+void os_putc(int ch)
+{
+   putchar(ch);
+}
+
+void os_puts(const char *str)
+{
+   while (*str)
+   os_putc(*str++);
+}
+
 int os_write_ram_buf(const char *fname)
 {
struct sandbox_state *state = state_get_current();
diff --git a/include/os.h b/include/os.h
index 2bf4bdb1b8..049b248c5b 100644
--- a/include/os.h
+++ b/include/os.h
@@ -240,6 +240,26 @@ const char *os_dirent_get_typename(enum os_dirent_t type);
  */
 int os_get_filesize(const char *fname, loff_t *size);
 
+/**
+ * Write a character to the controlling OS terminal
+ *
+ * This bypasses the U-Boot console support and writes directly to the OS
+ * stdout file descriptor.
+ *
+ * @param ch   Character to write
+ */
+void os_putc(int ch);
+
+/**
+ * Write a string to the controlling OS terminal
+ *
+ * This bypasses the U-Boot console support and writes directly to the OS
+ * stdout file descriptor.
+ *
+ * @param str  String to write (note that \n is not appended)
+ */
+void os_puts(const char *str);
+
 /**
  * Write the sandbox RAM buffer to a existing file
  *
-- 
2.14.1.992.g2c7b836f3a-goog

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[U-Boot] [PATCH v2 07/14] log: Add an implemention of logging

[Simon Glass]

Add the logging header file and implementation with some configuration
options to control it.

Signed-off-by: Simon Glass 
---

Changes in v2:
- Add a comment as to why CONFIG_LOG_MAX_LEVEL is not defined
- Drop MAINTAINERS entries for files not added by this patch
- Drop the use of 'continue' in the macro
- Fix LOG_SPL_MAX_LEVEL typo (should be SPL_LOG_MAX_LEVEL)
- Fix up bad use of #if CONFIG_VAL() - use #ifdef instead
- Line up log levels with Linux

 MAINTAINERS   |   7 ++
 common/Kconfig|  56 +
 common/Makefile   |   1 +
 common/log.c  | 244 
 include/asm-generic/global_data.h |   5 +
 include/log.h | 252 --
 6 files changed, 556 insertions(+), 9 deletions(-)
 create mode 100644 common/log.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 04acf2b89d..3ef97783c0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -290,6 +290,13 @@ S: Maintained
 T: git git://git.denx.de/u-boot-i2c.git
 F: drivers/i2c/
 
+LOGGING
+M: Simon Glass 
+S: Maintained
+T: git git://git.denx.de/u-boot.git
+F: common/log.c
+F: cmd/log.c
+
 MICROBLAZE
 M: Michal Simek 
 S: Maintained
diff --git a/common/Kconfig b/common/Kconfig
index 540ccb..ca4a0f7f9b 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -382,6 +382,62 @@ config SYS_STDIO_DEREGISTER
 
 endmenu
 
+menu "Logging"
+
+config LOG
+   bool "Enable logging support"
+   help
+ This enables support for logging of status and debug messages. These
+ can be displayed on the console, recorded in a memory buffer, or
+ discarded if not needed. Logging supports various categories and
+ levels of severity.
+
+config SPL_LOG
+   bool "Enable logging support in SPL"
+   help
+ This enables support for logging of status and debug messages. These
+ can be displayed on the console, recorded in a memory buffer, or
+ discarded if not needed. Logging supports various categories and
+ levels of severity.
+
+config LOG_MAX_LEVEL
+   int "Maximum log level to record"
+   depends on LOG
+   default 5
+   help
+ This selects the maximum log level that will be recorded. Any value
+ higher than this will be ignored. If possible log statements below
+ this level will be discarded at build time. Levels:
+
+   0 - panic
+   1 - critical
+   2 - error
+   3 - warning
+   4 - note
+   5 - info
+   6 - detail
+   7 - debug
+
+config SPL_LOG_MAX_LEVEL
+   int "Maximum log level to record in SPL"
+   depends on SPL_LOG
+   default 3
+   help
+ This selects the maximum log level that will be recorded. Any value
+ higher than this will be ignored. If possible log statements below
+ this level will be discarded at build time. Levels:
+
+   0 - panic
+   1 - critical
+   2 - error
+   3 - warning
+   4 - note
+   5 - info
+   6 - detail
+   7 - debug
+
+endmenu
+
 config DTB_RESELECT
bool "Support swapping dtbs at a later point in boot"
depends on FIT_EMBED
diff --git a/common/Makefile b/common/Makefile
index 801ea3191f..9d52c9623c 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -128,5 +128,6 @@ obj-y += cli.o
 obj-$(CONFIG_FSL_DDR_INTERACTIVE) += cli_simple.o cli_readline.o
 obj-$(CONFIG_CMD_DFU) += dfu.o
 obj-y += command.o
+obj-$(CONFIG_$(SPL_)LOG) += log.o
 obj-y += s_record.o
 obj-y += xyzModem.o
diff --git a/common/log.c b/common/log.c
new file mode 100644
index 00..a7d9a548f2
--- /dev/null
+++ b/common/log.c
@@ -0,0 +1,244 @@
+/*
+ * Logging support
+ *
+ * Copyright (c) 2017 Google, Inc
+ * Written by Simon Glass 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct log_device *log_device_find_by_name(const char *drv_name)
+{
+   struct log_device *ldev;
+
+   list_for_each_entry(ldev, >log_head, sibling_node) {
+   if (!strcmp(drv_name, ldev->drv->name))
+   return ldev;
+   }
+
+   return NULL;
+}
+
+/**
+ * log_has_cat() - check if a log category exists within a list
+ *
+ * @cat_list: List of categories to check, at most LOGF_MAX_CATEGORIES entries
+ * long, terminated by LC_END if fewer
+ * @cat: Category to search for
+ * @return true if @cat is in @cat_list, else false
+ */
+static bool log_has_cat(enum log_category_t cat_list[], enum log_category_t 
cat)
+{
+   int i;
+
+   for (i = 0; i < LOGF_MAX_CATEGORIES && cat_list[i] != LOGC_END; i++) {
+   if (cat_list[i] == cat)
+   return true;
+   }
+
+   return false;
+}
+
+/**
+ * 

[U-Boot] [PATCH v2 02/14] sandbox: Adjust pre-console address to avoid conflict

[Simon Glass]

We cannot use sandbox memory at 0 since other things use memory at that
address. Move it up out of the way.

Note that the pre-console buffer is currently disabled with sandbox, but
this change will avoid confusion if it is manually enabled.

Signed-off-by: Simon Glass 
---

Changes in v2:
- Split pre-console address change into a separate patch

 configs/sandbox_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 310b8acc29..93ea6889a0 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -15,7 +15,7 @@ CONFIG_CONSOLE_RECORD=y
 CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
 CONFIG_SILENT_CONSOLE=y
 CONFIG_PRE_CONSOLE_BUFFER=y
-CONFIG_PRE_CON_BUF_ADDR=0
+CONFIG_PRE_CON_BUF_ADDR=0x10
 CONFIG_CMD_CPU=y
 CONFIG_CMD_LICENSE=y
 CONFIG_CMD_BOOTZ=y
-- 
2.14.1.992.g2c7b836f3a-goog

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[U-Boot] [PATCH v2 00/14] log: Add a new logging feature

[Simon Glass]

U-Boot currently has fairly rudimentary logging features. A basic printf()
provides console output and debug() provides debug output which is
activated if DEBUG is defined in the file containing the debug()
statements.

It would be useful to have a few more features:

- control of debug output at runtime, so  problems can potentially be
debugged without recompiling U-Boot
- control of which subsystems output debug information, so that (for
example) it is possible to enable debugging for MMC or SATA at runtime
- indication of severity with each message, so that the user can control
whether just errors are displayed, warnings, or all debug messages
- sending logging information to different destinations, such as console,
memory, linux, etc,

At present U-Boot has a logbuffer feature which records output in a memory
buffer for later display or storage. This is useful but is not at present
enabled for any board.

This series introduced a new logging system which supports:
- various log levels from panic to debug
- log categories including all uclasses and a few others
- log drivers to which all log records can be sent
- log filters which control which log records make it to which drivers

Enabling logging with the default options does not add much to code size.
By default the maximum recorded log level is LOGL_INFO, meaning that debug
messages (and above) are discarded a build-time. Increasing this level
provides more run-time flexibility to enable/disable logging at the cost
of increased code size.

This feature is by no means finished. The README provides a long list of
features and clean-ups that could be done. But hopefully this is a
starting point for improving this important area in U-Boot.

The series is available at u-boot-dm/log-working

Changes in v2:
- Add a comment as to why CONFIG_LOG_MAX_LEVEL is not defined
- Change log levels to match new header
- Change sandbox log level to 6
- Drop MAINTAINERS entries for files not added by this patch
- Drop the special log() functions from the README
- Drop the use of 'continue' in the macro
- Fix LOG_SPL_MAX_LEVEL typo (should be SPL_LOG_MAX_LEVEL)
- Fix function called when test command is selected
- Fix help output for 'log test'
- Fix up bad use of #if CONFIG_VAL() - use #ifdef instead
- Line up log levels with Linux
- Only execute log tests if CONFIG_LOG is enabled
- Rename LOGL_WARN to LOGL_WARNING
- Split pre-console address change into a separate patch
- Update commit message to explain that this is not just for serial output

Simon Glass (14):
  Revert "sandbox: remove os_putc() and os_puts()"
  sandbox: Adjust pre-console address to avoid conflict
  Revert "sandbox: Drop special case console code for sandbox"
  Move debug and logging support to a separate header
  mtdparts: Correct use of debug()
  Drop the log buffer
  log: Add an implemention of logging
  log: Add a console driver
  log: Add a 'log level' command
  log: Add a test command
  log: Plumb logging into the init sequence
  log: sandbox: Enable logging
  log: test: Add a pytest for logging
  log: Add documentation

 MAINTAINERS   |   9 ++
 arch/sandbox/cpu/os.c |  11 ++
 cmd/Kconfig   |   8 +
 cmd/Makefile  |   2 +-
 cmd/log.c | 326 +-
 cmd/mtdparts.c|   3 -
 common/Kconfig|  86 ++
 common/Makefile   |   2 +
 common/board_f.c  |  23 +--
 common/board_r.c  |  27 +---
 common/console.c  |   7 +
 common/image.c|   9 --
 common/log.c  | 245 
 common/log_console.c  |  23 +++
 common/stdio.c|   6 -
 configs/sandbox_defconfig |   5 +-
 doc/README.log| 214 +
 include/asm-generic/global_data.h |   8 +-
 include/common.h  |  64 +---
 include/log.h | 316 
 include/logbuff.h |  49 --
 include/os.h  |  20 +++
 include/post.h|   4 +-
 post/post.c   |   9 --
 post/tests.c  |   4 -
 scripts/config_whitelist.txt  |   1 -
 test/Makefile |   1 +
 test/log/Makefile |   7 +
 test/log/log_test.c   | 204 
 test/py/tests/test_log.py | 107 +
 30 files changed, 1320 insertions(+), 480 deletions(-)
 create mode 100644 common/log.c
 create mode 100644 common/log_console.c
 create mode 100644 doc/README.log
 create mode 100644 include/log.h
 delete mode 100644 include/logbuff.h
 create mode 100644 test/log/Makefile
 create mode 100644 test/log/log_test.c
 create mode 100644 test/py/tests/test_log.py

-- 
2.14.1.992.g2c7b836f3a-goog

Re: [U-Boot] [PATCH] test/overlay: Fix various malloc/free leaks

[Tom Rini]

On Tue, Sep 26, 2017 at 06:28:40PM +, Langer, Thomas wrote:
> Hello Tom,
> 
> I just read some days ago about the kernel Coding-Style:
> 
> 
> Choose label names which say what the goto does or why the goto exists.  An
> example of a good name could be ``out_free_buffer:`` if the goto frees 
> ``buffer``.
> Avoid using GW-BASIC names like ``err1:`` and ``err2:``, as you would have to
> renumber them if you ever add or remove exit paths, and they make correctness
> difficult to verify anyway.
> 
> 
> Does is make sense to follow this for U-Boot also and fix the names of the 
> labels below?
> 
> > 
> > free(fdt_overlay_stacked_copy);
> > +err3:
> > free(fdt_overlay_copy);
> > +err2:
> > free(fdt_base_copy);
> > +err1:
> > free(uts);
> > 

We have in U-Boot a number of cases of both, and the majority (from a
quick read on 'git grep goto' is of the less descriptive case.  I can
certainly see how descriptive goto labels make more sense in the case of
large functions and especially complicated short-cuts.  Do you think
'malloc_base_copy_failed', 'malloc_overlay_copy_failed' and
'malloc_stacked_copy_failed' make the code more readable?

-- 
Tom


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Re: [U-Boot] [PATCH] test/dm: Fix string handling issues in the eth test

[Simon Glass]

On 26 September 2017 at 12:08, Tom Rini  wrote:
> Coverity scan has identified potential buffer overruns in these tests.
> Correct this by zeroing our buffer and using strncpy not strcpy.
>
> Reported-by: Coverity (CID: 155462, 155463)
> Cc: Joe Hershberger 
> Cc: Simon Glass 
> Cc: Bin Meng 
> Signed-off-by: Tom Rini 
> ---
>  test/dm/eth.c | 8 +---
>  1 file changed, 5 insertions(+), 3 deletions(-)

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH 06/13] log: Add an implemention of logging

[Simon Glass]

Hi Masahiro,

On 20 September 2017 at 11:19, Masahiro Yamada
 wrote:
> Hi Simon,
>
>
> 2017-09-20 22:49 GMT+09:00 Simon Glass :
>> Hi Masahiro,
>>
>> On 19 September 2017 at 20:51, Masahiro Yamada
>>  wrote:
>>> Hi Simon,
>>>
>>>
>>> 2017-09-17 6:23 GMT+09:00 Simon Glass :
>>>

 +menu "Logging"
 +
 +config LOG
 +   bool "Enable logging support"
 +   help
 + This enables support for logging of status and debug messages. 
 These
 + can be displayed on the console, recorded in a memory buffer, or
 + discarded if not needed. Logging supports various categories and
 + levels of severity.
 +
 +config SPL_LOG
 +   bool "Enable logging support in SPL"
 +   help
 + This enables support for logging of status and debug messages. 
 These
 + can be displayed on the console, recorded in a memory buffer, or
 + discarded if not needed. Logging supports various categories and
 + levels of severity.
>>>
>>>
>>> Please note CONFIG_IS_ENABLED(LOG) is never enabled for TPL_BUILD.
>>>
>>> Since commit f1c6e1922eb57f4a212c09709801a1cc7920ffa9,
>>> CONFIG_IS_ENABLED(LOG) is expanded to CONFIG_TPL_LOG
>>> when building for TPL.
>>>
>>> Since that commit, if you add SPL_ prefixed option,
>>> you need to add a TPL_ one as well.
>>>
>>> I cannot believe why such a commit was accepted.
>>
>> Well either way is strange. it is strange that SPL is enabled for TPL
>> when really they are separate.
>>
>> We could revert that commit. But how do you think all of this SPL/TPL
>> control should actually work? What is intended?
>>
>> But I'm OK with not having logging in TPL until we need it.
>
> I will explain it in another mail.
>
>
>>>
>>>
>>>
>>>
 +config LOG_MAX_LEVEL
 +   int "Maximum log level to record"
 +   depends on LOG
 +   default 5
 +   help
 + This selects the maximum log level that will be recorded. Any 
 value
 + higher than this will be ignored. If possible log statements 
 below
 + this level will be discarded at build time. Levels:
 +
 +   0 - panic
 +   1 - critical
 +   2 - error
 +   3 - warning
 +   4 - note
 +   5 - info
 +   6 - detail
 +   7 - debug
>>>
>>>
>>> Please do not invent our own for U-Boot.
>>> Just use Linux log level.
>>>
>>> 0 (KERN_EMERG)  system is unusable
>>> 1 (KERN_ALERT)  action must be taken 
>>> immediately
>>> 2 (KERN_CRIT)   critical conditions
>>> 3 (KERN_ERR)error conditions
>>> 4 (KERN_WARNING)warning conditions
>>> 5 (KERN_NOTICE) normal but significant 
>>> condition
>>> 6 (KERN_INFO)   informational
>>> 7 (KERN_DEBUG)  debug-level messages
>>
>> Yes I looked hard at that. The first three seem hard to distinguish in
>> U-Boot, but we can keep them I suppose. But most of my problem is with
>> the last two. INFO is what I plan to use for normal printf() output.
>> DEBUG is obviously for debugging and often involves vaste amounts of
>> stuff (e.g. logging every access to an MMC peripheral). We need
>> something in between. It could list the accesses to device at a high
>> level (e.g API calls) but not every little register access.
>>
>> So I don't think the Linux levels are suitable at the high end. We
>> could go up to 8 I suppose, instead of trying to save one at the
>> bottom?
>
>
> In fact, Linux has one more for debug.
>  dev_vdbg() is widely used in Linux.
>
> If you like, we can add one more level:
>
>  8 (KERN_VDEBUG)   verbose debug messages
>
>
> Perhaps, logging every access to an MMC peripheral
> might belong to the vdbg level.

I like the idea of having a log level for message contents (bytes) and
another for I/O access. So I will add two more in v2.

>
>
>
> BTW, what do you mean "INFO is what I plan to use for normal printf() output"
>
> Is that mean printf() is equivalent to pr_info()?
> If loglevel is 6 or smaller, will all print() be silent?
> If so, probably we can not use command line interface.

I mean that I want to (later) add a feature that logs normal printf()
output. If the console is silent then it would still be logged. Maybe
one day log functions will be used instead of printf(), but for now
this provides a useful way to make things wok.

>
>
>
>
>
>>>
>>>
>>>
>>>
 +
 +/**
 + * log_dispatch() - Send a log record to all log devices for processing
 + *
 + * The log record is sent to each log device in turn, skipping those 

Re: [U-Boot] [PATCH 07/13] log: Add a console driver

[Simon Glass]

Hi Bin,

On 17 September 2017 at 23:45, Bin Meng  wrote:
> On Sun, Sep 17, 2017 at 5:23 AM, Simon Glass  wrote:
>> It is useful to display log messages on the console. Add a simple driver
>> to handle this.
>>
>> Signed-off-by: Simon Glass 
>> ---
>>
>>  common/Kconfig   | 20 
>>  common/Makefile  |  1 +
>>  common/log_console.c | 23 +++
>>  3 files changed, 44 insertions(+)
>>  create mode 100644 common/log_console.c
>>
>
> Reviewed-by: Bin Meng 
>
> But isn't it possible to get this stuff into the serial-uclass driver?

It could do but then it would not be the console. The console is
controlled by stdout and might be set to output to an LCD, or perhaps
both LCD and serial.

Regards,
Simon
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Re: [U-Boot] [PATCH] test/overlay: Fix various malloc/free leaks

[Langer, Thomas]

Hello Tom,

I just read some days ago about the kernel Coding-Style:


Choose label names which say what the goto does or why the goto exists.  An
example of a good name could be ``out_free_buffer:`` if the goto frees 
``buffer``.
Avoid using GW-BASIC names like ``err1:`` and ``err2:``, as you would have to
renumber them if you ever add or remove exit paths, and they make correctness
difficult to verify anyway.


Does is make sense to follow this for U-Boot also and fix the names of the 
labels below?

> 
>   free(fdt_overlay_stacked_copy);
> +err3:
>   free(fdt_overlay_copy);
> +err2:
>   free(fdt_base_copy);
> +err1:
>   free(uts);
> 

Best regards,
Thomas

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[U-Boot] [PATCH] test/dm: Fix string handling issues in the eth test

[Tom Rini]

Coverity scan has identified potential buffer overruns in these tests.
Correct this by zeroing our buffer and using strncpy not strcpy.

Reported-by: Coverity (CID: 155462, 155463)
Cc: Joe Hershberger 
Cc: Simon Glass 
Cc: Bin Meng 
Signed-off-by: Tom Rini 
---
 test/dm/eth.c | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/test/dm/eth.c b/test/dm/eth.c
index 122fab924d6a..67fd660ee4f5 100644
--- a/test/dm/eth.c
+++ b/test/dm/eth.c
@@ -110,6 +110,7 @@ static int dm_test_eth_act(struct unit_test_state *uts)
char ethaddr[DM_TEST_ETH_NUM][18];
int i;
 
+   memset(ethaddr, '\0', sizeof(ethaddr));
net_ping_ip = string_to_ip("1.1.2.2");
 
/* Prepare the test scenario */
@@ -119,7 +120,7 @@ static int dm_test_eth_act(struct unit_test_state *uts)
ut_assertok(device_remove(dev[i], DM_REMOVE_NORMAL));
 
/* Invalidate MAC address */
-   strcpy(ethaddr[i], env_get(addrname[i]));
+   strncpy(ethaddr[i], env_get(addrname[i]), 17);
/* Must disable access protection for ethaddr before clearing */
env_set(".flags", addrname[i]);
env_set(addrname[i], NULL);
@@ -187,7 +188,8 @@ static int dm_test_eth_rotate(struct unit_test_state *uts)
net_ping_ip = string_to_ip("1.1.2.2");
 
/* Invalidate eth1's MAC address */
-   strcpy(ethaddr, env_get("eth1addr"));
+   memset(ethaddr, '\0', sizeof(ethaddr));
+   strncpy(ethaddr, env_get("eth1addr"), 17);
/* Must disable access protection for eth1addr before clearing */
env_set(".flags", "eth1addr");
env_set("eth1addr", NULL);
@@ -200,7 +202,7 @@ static int dm_test_eth_rotate(struct unit_test_state *uts)
 
if (!retval) {
/* Invalidate eth0's MAC address */
-   strcpy(ethaddr, env_get("ethaddr"));
+   strncpy(ethaddr, env_get("ethaddr"), 17);
/* Must disable access protection for ethaddr before clearing */
env_set(".flags", "ethaddr");
env_set("ethaddr", NULL);
-- 
1.9.1

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[U-Boot] [PATCH 6/6] usb: Drop the EHCI RCar Gen3

[Marek Vasut]

Since we use EHCI generic driver on RCar Gen3 , this driver is useless.
Remove it.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu 
---
 drivers/usb/host/Kconfig  |   8 ---
 drivers/usb/host/Makefile |   1 -
 drivers/usb/host/ehci-rcar_gen3.c | 106 --
 3 files changed, 115 deletions(-)
 delete mode 100644 drivers/usb/host/ehci-rcar_gen3.c

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index f797a2568c..f5f19ed775 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -157,14 +157,6 @@ config USB_EHCI_PCI
help
  Enables support for the PCI-based EHCI controller.
 
-config USB_EHCI_RCAR_GEN3
-   bool "Support for Renesas RCar M3/H3 EHCI USB controller"
-   depends on RCAR_GEN3
-   default y
-   ---help---
- Enables support for the on-chip EHCI controller on Renesas
- R8A7795 and R8A7796 SoCs.
-
 config USB_EHCI_ZYNQ
bool "Support for Xilinx Zynq on-chip EHCI USB controller"
depends on ARCH_ZYNQ
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 29afb7cf1d..83903fcf99 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -46,7 +46,6 @@ obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
 obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
 obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o
 obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
-obj-$(CONFIG_USB_EHCI_RCAR_GEN3) += ehci-rcar_gen3.o
 obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
 
 # xhci
diff --git a/drivers/usb/host/ehci-rcar_gen3.c 
b/drivers/usb/host/ehci-rcar_gen3.c
deleted file mode 100644
index 525e7f3573..00
--- a/drivers/usb/host/ehci-rcar_gen3.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * drivers/usb/host/ehci-rcar_gen3.
- * This file is EHCI HCD (Host Controller Driver) for USB.
- *
- * Copyright (C) 2015-2017 Renesas Electronics Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include "ehci.h"
-
-#define RCAR_GEN3_USB_BASE(n)  (0xEE08 + ((n) * 0x2))
-
-#define EHCI_USBCMD0x120
-
-#define CORE_SPD_RSM_TIMSET0x30c
-#define CORE_OC_TIMSET 0x310
-
-/* Register offset */
-#define AHB_OFFSET 0x200
-
-#define BASE_HSUSB 0xE659
-#define REG_LPSTS  (BASE_HSUSB + 0x0102)   /* 16bit */
-#define SUSPM  0x4000
-#define SUSPM_NORMAL   BIT(14)
-#define REG_UGCTRL2(BASE_HSUSB + 0x0184)   /* 32bit */
-#define USB0SEL0x0030
-#define USB0SEL_EHCI   0x0010
-
-#define SMSTPCR7   0xE615014C
-#define SMSTPCR700 BIT(0)  /* EHCI3 */
-#define SMSTPCR701 BIT(1)  /* EHCI2 */
-#define SMSTPCR702 BIT(2)  /* EHCI1 */
-#define SMSTPCR703 BIT(3)  /* EHCI0 */
-#define SMSTPCR704 BIT(4)  /* HSUSB */
-
-#define AHB_PLL_RSTBIT(1)
-
-#define USBH_INTBENBIT(2)
-#define USBH_INTAENBIT(1)
-
-#define AHB_INT_ENABLE 0x200
-#define AHB_USBCTR 0x20c
-
-int ehci_hcd_stop(int index)
-{
-#if defined(CONFIG_R8A7795)
-   const u32 mask = SMSTPCR703 | SMSTPCR702 | SMSTPCR701 | SMSTPCR700;
-#else
-   const u32 mask = SMSTPCR703 | SMSTPCR702;
-#endif
-   const u32 base = RCAR_GEN3_USB_BASE(index);
-   int ret;
-
-   /* Reset EHCI */
-   setbits_le32((uintptr_t)(base + EHCI_USBCMD), CMD_RESET);
-   ret = wait_for_bit("ehci-rcar", (void *)(uintptr_t)base + EHCI_USBCMD,
-  CMD_RESET, false, 10, true);
-   if (ret) {
-   printf("ehci-rcar: reset failed (index=%i, ret=%i).\n",
-  index, ret);
-   }
-
-   setbits_le32(SMSTPCR7, BIT(3 - index));
-
-   if ((readl(SMSTPCR7) & mask) == mask)
-   setbits_le32(SMSTPCR7, SMSTPCR704);
-
-   return 0;
-}
-
-int ehci_hcd_init(int index, enum usb_init_type init,
- struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
-   const void __iomem *base =
-   (void __iomem *)(uintptr_t)RCAR_GEN3_USB_BASE(index);
-   struct usb_ehci *ehci = (struct usb_ehci *)(uintptr_t)base;
-
-   clrbits_le32(SMSTPCR7, BIT(3 - index));
-   clrbits_le32(SMSTPCR7, SMSTPCR704);
-
-   *hccr = (struct ehci_hccr *)((uintptr_t)>caplength);
-   *hcor = (struct ehci_hcor *)((uintptr_t)*hccr +
-   HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
-
-   /* Enable interrupt */
-   setbits_le32(base + AHB_INT_ENABLE, USBH_INTBEN | USBH_INTAEN);
-   writel(0x014e029b, base + CORE_SPD_RSM_TIMSET);
-   writel(0x000209ab, base + CORE_OC_TIMSET);
-
-   /* Choice USB0SEL */
-   clrsetbits_le32(REG_UGCTRL2, USB0SEL, USB0SEL_EHCI);
-
-   /* Clock & Reset */
-   clrbits_le32(base + AHB_USBCTR, AHB_PLL_RST);
-
-   /* low 

[U-Boot] [PATCH 3/6] ARM: rmobile: Move HSUSB configuration to board on ULCB

[Marek Vasut]

In order to use ehci-generic driver, move the configuration of HSUSB
block into the board file. This configuration should not have been in
the Gen3 EHCI USB driver in the first place, so move it to the board
file until there is a proper infrastructure and driver for the HSUSB
block.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu 
---
 board/renesas/ulcb/ulcb.c | 16 
 1 file changed, 16 insertions(+)

diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c
index dc23228f4f..578b14be7b 100644
--- a/board/renesas/ulcb/ulcb.c
+++ b/board/renesas/ulcb/ulcb.c
@@ -53,6 +53,7 @@ void s_init(void)
 #define SD0_MSTP314BIT(14)
 #define SD1_MSTP313BIT(13)
 #define SD2_MSTP312BIT(12) /* either MMC0 */
+#define HSUSB_MSTP704  BIT(4)  /* HSUSB */
 
 #define SD0CKCR0xE6150074
 #define SD1CKCR0xE6150078
@@ -90,6 +91,13 @@ int board_early_init_f(void)
 /* -/W 32 Power resume control register 2 (3DG) */
 #defineSYSC_PWRONCR2   0xE618010C
 
+/* HSUSB block registers */
+#define HSUSB_REG_LPSTS0xE6590102
+#define HSUSB_REG_LPSTS_SUSPM_NORMAL   BIT(14)
+#define HSUSB_REG_UGCTRL2  0xE6590184
+#define HSUSB_REG_UGCTRL2_USB0SEL  0x30
+#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
+
 int board_init(void)
 {
/* adress of boot parameters */
@@ -105,6 +113,14 @@ int board_init(void)
/* USB1 pull-up */
setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
 
+   /* Configure the HSUSB block */
+   mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
+   /* Choice USB0SEL */
+   clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
+   HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
+   /* low power status */
+   setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
+
 #ifdef CONFIG_RENESAS_RAVB
/* EtherAVB Enable */
/* GPSR2 */
-- 
2.11.0

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[U-Boot] [PATCH 2/6] ARM: rmobile: Move HSUSB configuration to board on Salvator-X

[Marek Vasut]

In order to use ehci-generic driver, move the configuration of HSUSB
block into the board file. This configuration should not have been in
the Gen3 EHCI USB driver in the first place, so move it to the board
file until there is a proper infrastructure and driver for the HSUSB
block.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu 
---
 board/renesas/salvator-x/salvator-x.c | 16 
 1 file changed, 16 insertions(+)

diff --git a/board/renesas/salvator-x/salvator-x.c 
b/board/renesas/salvator-x/salvator-x.c
index e260117802..37fcbbd448 100644
--- a/board/renesas/salvator-x/salvator-x.c
+++ b/board/renesas/salvator-x/salvator-x.c
@@ -55,6 +55,7 @@ void s_init(void)
 #define SD1_MSTP313BIT(13)
 #define SD2_MSTP312BIT(12) /* either MMC0 */
 #define SD3_MSTP311BIT(11) /* either MMC1 */
+#define HSUSB_MSTP704  BIT(4)  /* HSUSB */
 
 #define SD0CKCR0xE6150074
 #define SD1CKCR0xE6150078
@@ -92,6 +93,13 @@ int board_early_init_f(void)
 /* -/W 32 Power resume control register 2 (3DG) */
 #defineSYSC_PWRONCR2   0xE618010C
 
+/* HSUSB block registers */
+#define HSUSB_REG_LPSTS0xE6590102
+#define HSUSB_REG_LPSTS_SUSPM_NORMAL   BIT(14)
+#define HSUSB_REG_UGCTRL2  0xE6590184
+#define HSUSB_REG_UGCTRL2_USB0SEL  0x30
+#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
+
 int board_init(void)
 {
/* adress of boot parameters */
@@ -116,6 +124,14 @@ int board_init(void)
/* USB1 pull-up */
setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
 
+   /* Configure the HSUSB block */
+   mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
+   /* Choice USB0SEL */
+   clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
+   HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
+   /* low power status */
+   setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
+
 #ifdef CONFIG_RENESAS_RAVB
/* EtherAVB Enable */
/* GPSR2 */
-- 
2.11.0

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[U-Boot] [PATCH 4/6] ARM: rmobile: Enable EHCI generic on Salvator-X

[Marek Vasut]

Enable the EHCI generic driver, which is superior to ad-hoc SoC specific one.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu 
---
 configs/r8a7795_salvator-x_defconfig | 1 +
 configs/r8a7796_salvator-x_defconfig | 1 +
 2 files changed, 2 insertions(+)

diff --git a/configs/r8a7795_salvator-x_defconfig 
b/configs/r8a7795_salvator-x_defconfig
index 271b15da42..585eb64973 100644
--- a/configs/r8a7795_salvator-x_defconfig
+++ b/configs/r8a7795_salvator-x_defconfig
@@ -34,5 +34,6 @@ CONFIG_SCIF_CONSOLE=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_STORAGE=y
 CONFIG_SMBIOS_MANUFACTURER=""
diff --git a/configs/r8a7796_salvator-x_defconfig 
b/configs/r8a7796_salvator-x_defconfig
index 921fdf77ff..302e8999a6 100644
--- a/configs/r8a7796_salvator-x_defconfig
+++ b/configs/r8a7796_salvator-x_defconfig
@@ -35,5 +35,6 @@ CONFIG_SCIF_CONSOLE=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_STORAGE=y
 CONFIG_SMBIOS_MANUFACTURER=""
-- 
2.11.0

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[U-Boot] [PATCH] ARM: rmobile: Move CONFIG_CMD_ from rcar-gen3-common to configs

[Marek Vasut]

Just move those config options from macros to configs.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu 
---
 configs/r8a7795_salvator-x_defconfig | 4 
 configs/r8a7795_ulcb_defconfig   | 5 +
 configs/r8a7796_salvator-x_defconfig | 4 
 configs/r8a7796_ulcb_defconfig   | 5 +
 include/configs/rcar-gen3-common.h   | 4 
 5 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/configs/r8a7795_salvator-x_defconfig 
b/configs/r8a7795_salvator-x_defconfig
index 585eb64973..c5f86464d6 100644
--- a/configs/r8a7795_salvator-x_defconfig
+++ b/configs/r8a7795_salvator-x_defconfig
@@ -19,7 +19,11 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_CLK=y
diff --git a/configs/r8a7795_ulcb_defconfig b/configs/r8a7795_ulcb_defconfig
index 6f30c8d870..63fdb8d697 100644
--- a/configs/r8a7795_ulcb_defconfig
+++ b/configs/r8a7795_ulcb_defconfig
@@ -18,6 +18,11 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_CLK=y
diff --git a/configs/r8a7796_salvator-x_defconfig 
b/configs/r8a7796_salvator-x_defconfig
index 302e8999a6..4273f4186f 100644
--- a/configs/r8a7796_salvator-x_defconfig
+++ b/configs/r8a7796_salvator-x_defconfig
@@ -20,7 +20,11 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_CLK=y
diff --git a/configs/r8a7796_ulcb_defconfig b/configs/r8a7796_ulcb_defconfig
index 2ff91dfbf3..77a5018dc7 100644
--- a/configs/r8a7796_ulcb_defconfig
+++ b/configs/r8a7796_ulcb_defconfig
@@ -19,6 +19,11 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_CLK=y
diff --git a/include/configs/rcar-gen3-common.h 
b/include/configs/rcar-gen3-common.h
index 49b1b5ade4..745291a971 100644
--- a/include/configs/rcar-gen3-common.h
+++ b/include/configs/rcar-gen3-common.h
@@ -12,10 +12,6 @@
 
 #include 
 
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
-
 #define CONFIG_REMAKE_ELF
 
 /* boot option */
-- 
2.11.0

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[U-Boot] [PATCH] mmc: uniphier-sd: Update the file to match V3 patchset

[Marek Vasut]

Old version of the uniphier-sd 64bit IO support patchset V1 was
applied by the maintainer, update the uniphier-sd.c with the
changes from the V3 of the patchset.

Signed-off-by: Marek Vasut 
Cc: Masahiro Yamada 
Cc: Jaehoon Chung 
---
 drivers/mmc/uniphier-sd.c | 83 ---
 1 file changed, 42 insertions(+), 41 deletions(-)

diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c
index 0786ad0d5f..3c52161067 100644
--- a/drivers/mmc/uniphier-sd.c
+++ b/drivers/mmc/uniphier-sd.c
@@ -135,7 +135,7 @@ struct uniphier_sd_priv {
 #define UNIPHIER_SD_CAP_64BIT  BIT(3)  /* Controller is 64bit */
 };
 
-static u64 uniphier_sd_readq(struct uniphier_sd_priv *priv, const u32 reg)
+static u64 uniphier_sd_readq(struct uniphier_sd_priv *priv, unsigned int reg)
 {
if (priv->caps & UNIPHIER_SD_CAP_64BIT)
return readq(priv->regbase + (reg << 1));
@@ -144,7 +144,7 @@ static u64 uniphier_sd_readq(struct uniphier_sd_priv *priv, 
const u32 reg)
 }
 
 static void uniphier_sd_writeq(struct uniphier_sd_priv *priv,
-  const u64 val, const u32 reg)
+  u64 val, unsigned int reg)
 {
if (priv->caps & UNIPHIER_SD_CAP_64BIT)
writeq(val, priv->regbase + (reg << 1));
@@ -152,7 +152,7 @@ static void uniphier_sd_writeq(struct uniphier_sd_priv 
*priv,
writeq(val, priv->regbase + reg);
 }
 
-static u32 uniphier_sd_readl(struct uniphier_sd_priv *priv, const u32 reg)
+static u32 uniphier_sd_readl(struct uniphier_sd_priv *priv, unsigned int reg)
 {
if (priv->caps & UNIPHIER_SD_CAP_64BIT)
return readl(priv->regbase + (reg << 1));
@@ -161,7 +161,7 @@ static u32 uniphier_sd_readl(struct uniphier_sd_priv *priv, 
const u32 reg)
 }
 
 static void uniphier_sd_writel(struct uniphier_sd_priv *priv,
-  const u32 val, const u32 reg)
+  u32 val, unsigned int reg)
 {
if (priv->caps & UNIPHIER_SD_CAP_64BIT)
writel(val, priv->regbase + (reg << 1));
@@ -246,7 +246,7 @@ static int uniphier_sd_wait_for_irq(struct udevice *dev, 
unsigned int reg,
return 0;
 }
 
-static int uniphier_sd_pio_read_one_block(struct udevice *dev, u32 **pbuf,
+static int uniphier_sd_pio_read_one_block(struct udevice *dev, char *pbuf,
  uint blocksize)
 {
struct uniphier_sd_priv *priv = dev_get_priv(dev);
@@ -264,36 +264,33 @@ static int uniphier_sd_pio_read_one_block(struct udevice 
*dev, u32 **pbuf,
 */
uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2);
 
-   if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) {
-   if (priv->caps & UNIPHIER_SD_CAP_64BIT) {
+   if (priv->caps & UNIPHIER_SD_CAP_64BIT) {
+   u64 *buf = (u64 *)pbuf;
+   if (likely(IS_ALIGNED((uintptr_t)buf, 8))) {
for (i = 0; i < blocksize / 8; i++) {
-   u64 data;
-   data = uniphier_sd_readq(priv,
-UNIPHIER_SD_BUF);
-   *(*pbuf)++ = data;
-   *(*pbuf)++ = data >> 32;
+   *buf++ = uniphier_sd_readq(priv,
+  UNIPHIER_SD_BUF);
}
} else {
-   for (i = 0; i < blocksize / 4; i++) {
-   u32 data;
-   data = uniphier_sd_readl(priv, UNIPHIER_SD_BUF);
-   *(*pbuf)++ = data;
-   }
-   }
-   } else {
-   if (priv->caps & UNIPHIER_SD_CAP_64BIT) {
for (i = 0; i < blocksize / 8; i++) {
u64 data;
data = uniphier_sd_readq(priv,
 UNIPHIER_SD_BUF);
-   put_unaligned(data, (*pbuf)++);
-   put_unaligned(data >> 32, (*pbuf)++);
+   put_unaligned(data, buf++);
+   }
+   }
+   } else {
+   u32 *buf = (u32 *)pbuf;
+   if (likely(IS_ALIGNED((uintptr_t)buf, 4))) {
+   for (i = 0; i < blocksize / 4; i++) {
+   *buf++ = uniphier_sd_readl(priv,
+  UNIPHIER_SD_BUF);
}
} else {
for (i = 0; i < blocksize / 4; i++) {
u32 data;
data = uniphier_sd_readl(priv, UNIPHIER_SD_BUF);
-   

[U-Boot] [PATCH 5/6] ARM: rmobile: Enable EHCI generic on ULCB

[Marek Vasut]

Enable the EHCI generic driver, which is superior to ad-hoc SoC specific one.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu 
---
 configs/r8a7795_ulcb_defconfig | 1 +
 configs/r8a7796_ulcb_defconfig | 1 +
 2 files changed, 2 insertions(+)

diff --git a/configs/r8a7795_ulcb_defconfig b/configs/r8a7795_ulcb_defconfig
index 832998083a..6f30c8d870 100644
--- a/configs/r8a7795_ulcb_defconfig
+++ b/configs/r8a7795_ulcb_defconfig
@@ -30,5 +30,6 @@ CONFIG_SCIF_CONSOLE=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_STORAGE=y
 CONFIG_SMBIOS_MANUFACTURER=""
diff --git a/configs/r8a7796_ulcb_defconfig b/configs/r8a7796_ulcb_defconfig
index 5846147348..2ff91dfbf3 100644
--- a/configs/r8a7796_ulcb_defconfig
+++ b/configs/r8a7796_ulcb_defconfig
@@ -31,5 +31,6 @@ CONFIG_SCIF_CONSOLE=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_STORAGE=y
 CONFIG_SMBIOS_MANUFACTURER=""
-- 
2.11.0

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[U-Boot] [PATCH 1/6] ARM: rmobile: dts: Add EHCI USB nodes to r8a7796

[Marek Vasut]

The R8A7796 EHCI USB nodes are missing from r8a7796 dtsi, add them.
These nodes don't come from mainline Linux, yet the DT binding is
similar enough to R8A7795 which already has those in mainline and
once the nodes hit mainline, this DT should be resynched.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu 
---
 arch/arm/dts/r8a7796.dtsi | 51 ++-
 1 file changed, 46 insertions(+), 5 deletions(-)

diff --git a/arch/arm/dts/r8a7796.dtsi b/arch/arm/dts/r8a7796.dtsi
index c0cb4a952f..7e3b1d82a1 100644
--- a/arch/arm/dts/r8a7796.dtsi
+++ b/arch/arm/dts/r8a7796.dtsi
@@ -1106,7 +1106,17 @@
};
 
hsusb: usb@e659 {
-   /* placeholder */
+   compatible = "renesas,usbhs-r8a7796",
+"renesas,rcar-gen3-usbhs";
+   reg = <0 0xe659 0 0x100>;
+   interrupts = ;
+   clocks = < CPG_MOD 704>;
+   renesas,buswait = <11>;
+   phys = <_phy0>;
+   phy-names = "usb";
+   power-domains = < R8A7796_PD_ALWAYS_ON>;
+   resets = < 704>;
+   status = "disabled";
};
 
xhci0: usb@ee00 {
@@ -1118,11 +1128,27 @@
};
 
ehci0: usb@ee080100 {
-   /* placeholder */
+   compatible = "generic-ehci";
+   reg = <0 0xee080100 0 0x100>;
+   interrupts = ;
+   clocks = < CPG_MOD 703>;
+   phys = <_phy0>;
+   phy-names = "usb";
+   power-domains = < R8A7796_PD_ALWAYS_ON>;
+   resets = < 703>;
+   status = "disabled";
};
 
usb2_phy0: usb-phy@ee080200 {
-   /* placeholder */
+   compatible = "renesas,usb2-phy-r8a7796",
+"renesas,rcar-gen3-usb2-phy";
+   reg = <0 0xee080200 0 0x700>;
+   interrupts = ;
+   clocks = < CPG_MOD 703>;
+   power-domains = < R8A7796_PD_ALWAYS_ON>;
+   resets = < 703>;
+   #phy-cells = <0>;
+   status = "disabled";
};
 
ohci1: usb@ee0a {
@@ -1130,11 +1156,26 @@
};
 
ehci1: usb@ee0a0100 {
-   /* placeholder */
+   compatible = "generic-ehci";
+   reg = <0 0xee0a0100 0 0x100>;
+   interrupts = ;
+   clocks = < CPG_MOD 702>;
+   phys = <_phy1>;
+   phy-names = "usb";
+   power-domains = < R8A7796_PD_ALWAYS_ON>;
+   resets = < 702>;
+   status = "disabled";
};
 
usb2_phy1: usb-phy@ee0a0200 {
-   /* placeholder */
+   compatible = "renesas,usb2-phy-r8a7796",
+"renesas,rcar-gen3-usb2-phy";
+   reg = <0 0xee0a0200 0 0x700>;
+   clocks = < CPG_MOD 702>;
+   power-domains = < R8A7796_PD_ALWAYS_ON>;
+   resets = < 702>;
+   #phy-cells = <0>;
+   status = "disabled";
};
 
sdhi0: sd@ee10 {
-- 
2.11.0

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[U-Boot] [PATCH] ARM: rmobile: Switch to UniPhier SD driver on Gen3

[Marek Vasut]

The UniPhier SD driver handles the same Matsushita IP as is used
in the Renesas RCar SoCs, yet the driver is significantly better
than the SH SDHI one. Switch over to the Uniphier driver.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu 
---
 configs/r8a7795_salvator-x_defconfig | 2 +-
 configs/r8a7795_ulcb_defconfig   | 2 +-
 configs/r8a7796_salvator-x_defconfig | 2 +-
 configs/r8a7796_ulcb_defconfig   | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/configs/r8a7795_salvator-x_defconfig 
b/configs/r8a7795_salvator-x_defconfig
index 62b16b7a1c..271b15da42 100644
--- a/configs/r8a7795_salvator-x_defconfig
+++ b/configs/r8a7795_salvator-x_defconfig
@@ -25,7 +25,7 @@ CONFIG_ENV_IS_IN_MMC=y
 CONFIG_CLK=y
 CONFIG_CLK_RENESAS=y
 CONFIG_DM_MMC=y
-CONFIG_SH_SDHI=y
+CONFIG_MMC_UNIPHIER=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
diff --git a/configs/r8a7795_ulcb_defconfig b/configs/r8a7795_ulcb_defconfig
index a3dba70305..832998083a 100644
--- a/configs/r8a7795_ulcb_defconfig
+++ b/configs/r8a7795_ulcb_defconfig
@@ -23,7 +23,7 @@ CONFIG_ENV_IS_IN_MMC=y
 CONFIG_CLK=y
 CONFIG_CLK_RENESAS=y
 CONFIG_DM_MMC=y
-CONFIG_SH_SDHI=y
+CONFIG_MMC_UNIPHIER=y
 CONFIG_DM_ETH=y
 CONFIG_RENESAS_RAVB=y
 CONFIG_SCIF_CONSOLE=y
diff --git a/configs/r8a7796_salvator-x_defconfig 
b/configs/r8a7796_salvator-x_defconfig
index aa231b65e0..921fdf77ff 100644
--- a/configs/r8a7796_salvator-x_defconfig
+++ b/configs/r8a7796_salvator-x_defconfig
@@ -26,7 +26,7 @@ CONFIG_ENV_IS_IN_MMC=y
 CONFIG_CLK=y
 CONFIG_CLK_RENESAS=y
 CONFIG_DM_MMC=y
-CONFIG_SH_SDHI=y
+CONFIG_MMC_UNIPHIER=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
diff --git a/configs/r8a7796_ulcb_defconfig b/configs/r8a7796_ulcb_defconfig
index f222a6833c..5846147348 100644
--- a/configs/r8a7796_ulcb_defconfig
+++ b/configs/r8a7796_ulcb_defconfig
@@ -24,7 +24,7 @@ CONFIG_ENV_IS_IN_MMC=y
 CONFIG_CLK=y
 CONFIG_CLK_RENESAS=y
 CONFIG_DM_MMC=y
-CONFIG_SH_SDHI=y
+CONFIG_MMC_UNIPHIER=y
 CONFIG_DM_ETH=y
 CONFIG_RENESAS_RAVB=y
 CONFIG_SCIF_CONSOLE=y
-- 
2.11.0

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Re: [U-Boot] Issues with mx6 (cubox/wandboard) with 2017.09

[Peter Robinson]

>>> I'm seeing some issues with some of the i.MX6 devices with the latest
>>> stable release. It loads the SPL and then just seems to loop:
>>>
>>> U-Boot SPL 2017.09 (Sep 25 2017 - 18:42:10)
>>> Trying to boot from MMC1
>>>
>>> U-Boot SPL 2017.09 (Sep 25 2017 - 18:42:10)
>>> Trying to boot from MMC1
>>>
>>> U-Boot SPL 2017.09 (Sep 25 2017 - 18:42:10)
>>> Trying to boot from MMC1
>>>
>>> This is built on Fedora with latest gcc7 so I'm not sure if that's a
>>> possible issue. Is this something people are aware of and I've missed
>>> the fix.
>>
>> I haven't tested it with gcc7 yet, but if I use gcc6 I do not see the 
>> problem:
>>
>> U-Boot SPL 2017.09 (Sep 25 2017 - 15:55:59)
>> Trying to boot from MMC1
>>
>>
>> U-Boot 2017.09 (Sep 25 2017 - 15:55:59 -0300)
>>
>> CPU:   Freescale i.MX6Q rev1.2 at 792 MHz
>> Reset cause: POR
>> Board: Wandboard rev B1
>> I2C:   ready
>> DRAM:  2 GiB
>> MMC:   FSL_SDHC: 0, FSL_SDHC: 1
>> No panel detected: default to HDMI
>> Display: HDMI (1024x768)
>> In:serial
>> Out:   serial
>> Err:   serial
>> Net:   FEC [PRIME]
>> Hit any key to stop autoboot:  0
>> =>
>>
>> So maybe this issue could be related to gcc7?
>
> I've tested building U-Boot for Wandboard using GCC 7 from linaro.org:
> https://releases.linaro.org/components/toolchain/binaries/

I tested a build with 6.4 from Fedora 25 and I saw the same issue so
I'm not sure where the problem is coming from but I'm also
travelling/meetings so haven't had time to dig further into the issue
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Re: [U-Boot] ZynqMP qspi

[Liam Beguin]

Hi,

On 26/09/17 01:28 AM, Siva Durga Prasad Paladugu wrote:
> Hi,
> 
>> -Original Message-
>> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
>> Sent: Tuesday, September 26, 2017 10:17 AM
>> To: Liam Beguin 
>> Cc: u-boot@lists.denx.de; Michal Simek ; Siva Durga
>> Prasad Paladugu 
>> Subject: Re: [U-Boot] ZynqMP qspi
>>
>> On Tue, Sep 26, 2017 at 9:07 AM, Liam Beguin 
>> wrote:
>>>
>>> Resending with proper CC since the email came back.
>>>
>>> On 24/09/17 09:36 PM, Liam Beguin wrote:
 Hi,

 I'm testing a new Xilinx zynqmp dev board and was not able to probe
 the qspi with the latest mainline U-Boot. I see that there is a
>> 'zynqmp_qspi'
 driver in the Xilinx tree [1] but nothing in mainline. After a little
 digging, I found a thread on the list [2] (and [3]) and was wondering
 in what state this was now.
> 
> I am planning to send the new series in 1-2 weeks, probably you can wait till 
> then or
> you can try with the patch[2] and see if you are able to get it working with 
> those( those
> are known to be working when I sent ). Also, please note that as of now iam  
> targeting
> only for qspi single mode not the dual modes.
> 

Great, I'll wait for your series and test it as soon as it comes out.

Thanks,
Liam

> Thanks,
> Siva
> 

 [1]
 https://github.com/Xilinx/u-boot-
>> xlnx/blob/master/drivers/spi/zynqmp_
 qspi.c [2]
 https://lists.denx.de/pipermail/u-boot/2016-July/261003.html
 [3] https://lists.denx.de/pipermail/u-boot/2016-
>> November/273650.html
>>
>> I think, Siva is working on it. and he would be best to comment this.
>>
>> thanks!
>> --
>> Jagan Teki
>> Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream
>> Maintainer Hyderabad, India.
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[U-Boot] [PATCH RESEND] DW SPI: Get clock value from Device Tree

[Eugeniy Paltsev]

Add option to set spi controller clock frequency via device tree
using standard clock bindings.
Old way of setting spi controller clock frequency (via implementation
of 'cm_get_spi_controller_clk_hz' function in platform specific code)
remains supported.

Signed-off-by: Eugeniy Paltsev 
---
 Resending due to previously sent one was discarded by mailing list.

 drivers/spi/designware_spi.c | 68 +++-
 1 file changed, 67 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 5aa507b..c70697e 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -11,6 +11,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -94,6 +95,7 @@ struct dw_spi_priv {
void __iomem *regs;
unsigned int freq;  /* Default frequency */
unsigned int mode;
+   unsigned long bus_clk_rate;
 
int bits_per_word;
u8 cs;  /* chip select pin */
@@ -176,14 +178,78 @@ static void spi_hw_init(struct dw_spi_priv *priv)
debug("%s: fifo_len=%d\n", __func__, priv->fifo_len);
 }
 
+/*
+ * cm_get_spi_controller_clk_hz function is old way to set spi controller
+ * frequency. If it isn't implemented and spi controller frequency isn't set 
via
+ * device tree we will get into next default function.
+ */
+__weak unsigned int cm_get_spi_controller_clk_hz(void)
+{
+   error("SPI clock is defined neither via device tree nor via 
cm_get_spi_controller_clk_hz!");
+
+   return 0;
+}
+
+static int dw_spi_of_get_clk(struct udevice *bus)
+{
+#if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(CLK)
+   struct dw_spi_priv *priv = dev_get_priv(bus);
+   unsigned long clk_rate;
+   struct clk clk;
+   int ret;
+
+   ret = clk_get_by_index(bus, 0, );
+   if (ret)
+   return -EINVAL;
+
+   ret = clk_enable();
+   if (ret && ret != -ENOSYS)
+   return ret;
+
+   clk_rate = clk_get_rate();
+   if (!clk_rate)
+   return -EINVAL;
+
+   priv->bus_clk_rate = clk_rate;
+
+   clk_free();
+
+   return 0;
+#endif
+
+   return -ENOSYS;
+}
+
+static int dw_spi_get_clk(struct udevice *bus)
+{
+   struct dw_spi_priv *priv = dev_get_priv(bus);
+
+   /* Firstly try to get clock frequency from device tree */
+   if (!dw_spi_of_get_clk(bus))
+   return 0;
+
+   /* In case of failure rollback to cm_get_spi_controller_clk_hz */
+   priv->bus_clk_rate = cm_get_spi_controller_clk_hz();
+
+   if (!priv->bus_clk_rate)
+   return -EINVAL;
+
+   return 0;
+}
+
 static int dw_spi_probe(struct udevice *bus)
 {
struct dw_spi_platdata *plat = dev_get_platdata(bus);
struct dw_spi_priv *priv = dev_get_priv(bus);
+   int ret;
 
priv->regs = plat->regs;
priv->freq = plat->frequency;
 
+   ret = dw_spi_get_clk(bus);
+   if (ret)
+   return ret;
+
/* Currently only bits_per_word == 8 supported */
priv->bits_per_word = 8;
 
@@ -369,7 +435,7 @@ static int dw_spi_set_speed(struct udevice *bus, uint speed)
spi_enable_chip(priv, 0);
 
/* clk_div doesn't support odd number */
-   clk_div = cm_get_spi_controller_clk_hz() / speed;
+   clk_div = priv->bus_clk_rate / speed;
clk_div = (clk_div + 1) & 0xfffe;
dw_writel(priv, DW_SPI_BAUDR, clk_div);
 
-- 
2.9.3

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Re: [U-Boot] ZynqMP qspi

[Siva Durga Prasad Paladugu]

Hi,

> -Original Message-
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> Sent: Tuesday, September 26, 2017 10:17 AM
> To: Liam Beguin 
> Cc: u-boot@lists.denx.de; Michal Simek ; Siva Durga
> Prasad Paladugu 
> Subject: Re: [U-Boot] ZynqMP qspi
> 
> On Tue, Sep 26, 2017 at 9:07 AM, Liam Beguin 
> wrote:
> >
> > Resending with proper CC since the email came back.
> >
> > On 24/09/17 09:36 PM, Liam Beguin wrote:
> >> Hi,
> >>
> >> I'm testing a new Xilinx zynqmp dev board and was not able to probe
> >> the qspi with the latest mainline U-Boot. I see that there is a
> 'zynqmp_qspi'
> >> driver in the Xilinx tree [1] but nothing in mainline. After a little
> >> digging, I found a thread on the list [2] (and [3]) and was wondering
> >> in what state this was now.

I am planning to send the new series in 1-2 weeks, probably you can wait till 
then or
you can try with the patch[2] and see if you are able to get it working with 
those( those
are known to be working when I sent ). Also, please note that as of now iam  
targeting
only for qspi single mode not the dual modes.

Thanks,
Siva

> >>
> >> [1]
> >> https://github.com/Xilinx/u-boot-
> xlnx/blob/master/drivers/spi/zynqmp_
> >> qspi.c [2]
> >> https://lists.denx.de/pipermail/u-boot/2016-July/261003.html
> >> [3] https://lists.denx.de/pipermail/u-boot/2016-
> November/273650.html
> 
> I think, Siva is working on it. and he would be best to comment this.
> 
> thanks!
> --
> Jagan Teki
> Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream
> Maintainer Hyderabad, India.
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Re: [U-Boot] ZynqMP qspi

[Liam Beguin]

Resending with proper CC since the email came back.

On 24/09/17 09:36 PM, Liam Beguin wrote:
> Hi,
> 
> I'm testing a new Xilinx zynqmp dev board and was not able to probe the
> qspi with the latest mainline U-Boot. I see that there is a 'zynqmp_qspi'
> driver in the Xilinx tree [1] but nothing in mainline. After a little
> digging, I found a thread on the list [2] (and [3]) and was wondering in
> what state this was now.
> 
> [1] 
> https://github.com/Xilinx/u-boot-xlnx/blob/master/drivers/spi/zynqmp_qspi.c
> [2] https://lists.denx.de/pipermail/u-boot/2016-July/261003.html
> [3] https://lists.denx.de/pipermail/u-boot/2016-November/273650.html
> 
> Thanks,
> Liam
> 

Thanks,
Liam
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Re: [U-Boot] [PATCH] ARM: zynq: Add support for SYZYGY Hub board

[Tom McLeod]

Hi Michal,

I wanted to check in and see if you've had a chance to review this patch
yet. Please let me know if you need me to make any changes or if it's good
to go.

Thanks,
-Tom

On Tue, Sep 12, 2017 at 11:05 AM, Tom McLeod 
wrote:

> Add the Zynq-based SYZYGY Hub board from Opal Kelly. The board
> contains a Xilinx Zynq xc7z012s SoC, 1GB DDR3 RAM, and supports
> booting from SD.
>
> Signed-off-by: Tom McLeod 
> ---
>  arch/arm/dts/Makefile  |1 +
>  arch/arm/dts/zynq-syzygy-hub.dts   |   72 ++
>  board/opalkelly/zynq/MAINTAINERS   |6 +
>  board/opalkelly/zynq/Makefile  |9 +
>  board/opalkelly/zynq/board.c   |1 +
>  .../opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c  | 1078
> 
>  .../opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h  |  103 ++
>  configs/syzygy_hub_defconfig   |   57 ++
>  include/configs/syzygy_hub.h   |   72 ++
>  9 files changed, 1399 insertions(+)
>  create mode 100644 arch/arm/dts/zynq-syzygy-hub.dts
>  create mode 100644 board/opalkelly/zynq/MAINTAINERS
>  create mode 100644 board/opalkelly/zynq/Makefile
>  create mode 100644 board/opalkelly/zynq/board.c
>  create mode 100644 board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
>  create mode 100644 board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h
>  create mode 100644 configs/syzygy_hub_defconfig
>  create mode 100644 include/configs/syzygy_hub.h
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 1d6cee2..c15d94f 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -126,6 +126,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
> zynq-zc706.dtb \
> zynq-zed.dtb \
> zynq-zybo.dtb \
> +   zynq-syzygy-hub.dtb \
> zynq-microzed.dtb \
> zynq-picozed.dtb \
> zynq-topic-miami.dtb \
> diff --git a/arch/arm/dts/zynq-syzygy-hub.dts b/arch/arm/dts/zynq-syzygy-
> hub.dts
> new file mode 100644
> index 000..c98ef01
> --- /dev/null
> +++ b/arch/arm/dts/zynq-syzygy-hub.dts
> @@ -0,0 +1,72 @@
> +/*
> + * SYZYGY Hub DTS
> + *
> + *  Copyright (C) 2011 - 2015 Xilinx
> + *  Copyright (C) 2017 Opal Kelly Inc.
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +/dts-v1/;
> +/include/ "zynq-7000.dtsi"
> +
> +/ {
> +   model = "SYZYGY Hub";
> +   compatible = "xlnx,zynq-7000";
> +
> +   aliases {
> +   ethernet0 = 
> +   serial0 = 
> +   mmc0 = 
> +   };
> +
> +   memory@0 {
> +   device_type = "memory";
> +   reg = <0x0 0x4000>;
> +   };
> +
> +   chosen {
> +   bootargs = "";
> +   stdout-path = "serial0:115200n8";
> +   };
> +
> +   usb_phy0: phy0 {
> +   #phy-cells = <0>;
> +   compatible = "usb-nop-xceiv";
> +   reset-gpios = < 47 1>;
> +   };
> +};
> +
> + {
> +   ps-clk-frequency = <5000>;
> +};
> +
> + {
> +   status = "okay";
> +   phy-mode = "rgmii-id";
> +   phy-handle = <_phy>;
> +
> +   ethernet_phy: ethernet-phy@0 {
> +   reg = <0>;
> +   device_type = "ethernet-phy";
> +   };
> +};
> +
> + {
> +   status = "okay";
> +};
> +
> + {
> +   u-boot,dm-pre-reloc;
> +   status = "okay";
> +};
> +
> + {
> +   u-boot,dm-pre-reloc;
> +   status = "okay";
> +};
> +
> + {
> +   status = "okay";
> +   dr_mode = "otg";
> +   usb-phy = <_phy0>;
> +};
> diff --git a/board/opalkelly/zynq/MAINTAINERS b/board/opalkelly/zynq/
> MAINTAINERS
> new file mode 100644
> index 000..df4b9b6
> --- /dev/null
> +++ b/board/opalkelly/zynq/MAINTAINERS
> @@ -0,0 +1,6 @@
> +ZYNQ BOARD
> +M: Tom McLeod 
> +S: Maintained
> +F: board/opalkelly/zynq/
> +F: include/configs/syzygy_hub.h
> +F: configs/syzygy_hub_defconfig
> diff --git a/board/opalkelly/zynq/Makefile b/board/opalkelly/zynq/Makefile
> new file mode 100644
> index 000..09fc788
> --- /dev/null
> +++ b/board/opalkelly/zynq/Makefile
> @@ -0,0 +1,9 @@
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +obj-y  := board.o
> +
> +hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))
> +
> +obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o
> diff --git a/board/opalkelly/zynq/board.c b/board/opalkelly/zynq/board.c
> new file mode 100644
> index 000..a95c9d1
> --- /dev/null
> +++ b/board/opalkelly/zynq/board.c
> @@ -0,0 +1 @@
> +#include "../../xilinx/zynq/board.c"
> diff --git a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
> b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
> new file mode 100644
> index 000..2b111d0
> --- /dev/null
> +++ b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
> @@ -0,0 +1,1078 @@
> 

Re: [U-Boot] [PATCH 00/15] spl: atf: update booting images via ATF to use info from FIT images

[Michal Simek]

Hi Philipp,

On 13.9.2017 21:29, Philipp Tomsich wrote:
> 
> A number of things about how we boot the RK3368 and RK3399 through ATF
> are less than ideal today, especially when considering future
> platforms that will follow a similar boot concept:
> - the auto-detection of images from the FIT images was limited (i.e.
>   the start address of the BL33 image could not automatically retrieved)
> - no implementation for the platform-specific parameters exists (and
>   there is a danger that we'll end up with highly different, proprietary
>   platform parameters for different SOCs and boards, even though the
>   ATF code base already has FDT support)
> 
> This series tries to put us into a better position to support various
> boot scenarios (e.g. loading an OPTEE from the FIT image; and: booting
> a Linux kernel via ATF) in the future... and it establishes the FDT as
> a mechanism to pass boot-info to later stages.
> 
> For a practical example, refer to how we use this on the RK3399-Q7:
> * the ATF can read the full U-Boot's FDT to determine how to best issue
>   a cold-reset for the board
> * we inject information on where we loaded the M0 firmware into the
>   same FDT that is now visible to the ATF, so the ATF can relocate it
>   to its final destination---and we no longer need to overwrite parts
>   of the SPL binary during bootup
> 
> Note that there are still some limitations (e.g. the support for
> passing OPTEE as a BL3-2, is not in this version ... and there isn't
> support for booting Linux directly via ATF yet, either), but these can
> now be plugged cleanly into this infrastructure.


can you please send also sent your bootlogs?
I would like to see your flow also with pmu-firmware loading.

Thanks,
Michal
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Re: [U-Boot] Issues with mx6 (cubox/wandboard) with 2017.09

[Diego Dorta]

Hi Peter,

2017-09-25 16:00 GMT-03:00 Fabio Estevam :
> Hi Peter,
>
> On Mon, Sep 25, 2017 at 3:54 PM, Peter Robinson  wrote:
>> Hi Fabio,
>>
>> I'm seeing some issues with some of the i.MX6 devices with the latest
>> stable release. It loads the SPL and then just seems to loop:
>>
>> U-Boot SPL 2017.09 (Sep 25 2017 - 18:42:10)
>> Trying to boot from MMC1
>>
>> U-Boot SPL 2017.09 (Sep 25 2017 - 18:42:10)
>> Trying to boot from MMC1
>>
>> U-Boot SPL 2017.09 (Sep 25 2017 - 18:42:10)
>> Trying to boot from MMC1
>>
>> This is built on Fedora with latest gcc7 so I'm not sure if that's a
>> possible issue. Is this something people are aware of and I've missed
>> the fix.
>
> I haven't tested it with gcc7 yet, but if I use gcc6 I do not see the problem:
>
> U-Boot SPL 2017.09 (Sep 25 2017 - 15:55:59)
> Trying to boot from MMC1
>
>
> U-Boot 2017.09 (Sep 25 2017 - 15:55:59 -0300)
>
> CPU:   Freescale i.MX6Q rev1.2 at 792 MHz
> Reset cause: POR
> Board: Wandboard rev B1
> I2C:   ready
> DRAM:  2 GiB
> MMC:   FSL_SDHC: 0, FSL_SDHC: 1
> No panel detected: default to HDMI
> Display: HDMI (1024x768)
> In:serial
> Out:   serial
> Err:   serial
> Net:   FEC [PRIME]
> Hit any key to stop autoboot:  0
> =>
>
> So maybe this issue could be related to gcc7?

I've tested building U-Boot for Wandboard using GCC 7 from linaro.org:
https://releases.linaro.org/components/toolchain/binaries/

I've used this package:
gcc-linaro-7.1.1-2017.08-x86_64_arm-linux-gnueabi.tar.xz

I could not reproduce your error. It seems to work on my board,
here is the log:

U-Boot SPL 2017.09-00342-ge35454b (Sep 26 2017 - 14:08:10)
Trying to boot from MMC1


U-Boot 2017.09-00342-ge35454b (Sep 26 2017 - 14:08:10 -0300)

CPU:   Freescale i.MX6Q rev1.2 at 792 MHz
Reset cause: WDOG
Board: Wandboard rev B1
I2C:   ready
DRAM:  2 GiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
No panel detected: default to HDMI
Display: HDMI (1024x768)
In:serial
Out:   serial
Err:   serial
Net:   FEC [PRIME]
Hit any key to stop autoboot:  0

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Diego
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Re: [U-Boot] [PATCH v2 3/9] dm: clk: add clk driver support for stm32h7 SoCs

[Vikas MANOCHA]

Thanks Patrice,

> -Original Message-
> From: Patrice CHOTARD
> Sent: Tuesday, September 26, 2017 5:27 AM
> To: Vikas MANOCHA ; u-boot@lists.denx.de; 
> albert.u.b...@aribaud.net; s...@chromium.org
> Cc: Patrick DELAUNAY ; Christophe KERELLO 
> 
> Subject: Re: [PATCH v2 3/9] dm: clk: add clk driver support for stm32h7 SoCs
> 
> Hi Vikas
> 
> On 09/26/2017 10:51 AM, Patrice CHOTARD wrote:
> > Hi Vikas
> >
> > On 09/25/2017 09:51 AM, Patrice CHOTARD wrote:
> >> Hi Vikas
> >>
> >> On 09/20/2017 03:39 AM, Vikas Manocha wrote:
> >>> Hi Patrice,
> >>>
> >>> On 09/13/2017 09:00 AM, patrice.chot...@st.com wrote:
>  From: Patrice Chotard 
> 
>  This driver implements basic clock setup, only clock gating is
>  implemented.
> 
>  This driver doesn't implement .of_match as it's binded by MFD RCC
>  driver.
> 
>  Files include/dt-bindings/clock/stm32h7-clks.h and
>  doc/device-tree-bindings/clock/st,stm32h7-rcc.txt
>  will be available soon in a kernel tag, as all the bindings have
>  been acked by Rob Herring [1].
> 
>  [1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html
> 
>  Signed-off-by: Patrice Chotard 
>  ---
> >
> > [...]
> >
>  +
>  +#define PWR_CR3    0x0c #define PWR_CR3_SDEN
>  +BIT(2)
> >>>
> >>> Can we use SCUEN suffix to match the Ref Manual.
> >>
> >> Which version of reference manual do you use ? in mine its SDEN, but
> >> i propably use a too old ref manual.
> >>
> >
> > I have found the last version of STM32H7 ref manual, mine was too old,
> > ok i will update the PWR_CR3_SDEN to PWR_CR3_SCUEN
> 
> After double check, in the STM32H7x3 reference manual available on st.com 
> (DocID029587 Rev 2), bit 2 of PWR_CR3 reg is described as
> following:
> 
> "Bit 2 SCUEN: Supply configuration update enable This bit is read-only:
> 0: Supply configuration update locked.
> 1: Single write enabled to Supply configuration (LDOEN and BYPASS)"
> 
> Whereas in the one i used, bit 2 of PWR_CR3 is described as:
> 
> "Bit 2 SDEN (1)(2) : SD converter Enable
> 0: Step down converter disabled
> 1: Step down converter enabled. (Default)"
> 
> If i follow ref manual DocID029587 Rev 2, this bit is read-only, so the write 
> access of PWR_CR3 bit(2) in clk_stm32h7.c is useless. But
> after write access removal, the both STM32H7 disco and eval board doesn't 
> boot.
> 
> The reference manual is wrong regarding with at least this bit. I will 
> contact PWR architect to solve this point.

Ok, By the Rev3 of the Ref manual is also available online but does not matter 
for this bit. Even the explanation for this bit does not make sense if system 
does not boot without it.

Cheers,
Vikas

> 
> Patrice
> 
> 
> >
> > thanks
> >
> > Patrice
> >
> >>>
>  +#define PWR_D3CR    0x18
>  +#define PWR_D3CR_VOS_MASK    GENMASK(15, 14) #define
>  +PWR_D3CR_VOS_SHIFT    14 #define    VOS_SCALE_3    1
>  +#define    VOS_SCALE_2    2 #define    VOS_SCALE_1
>  +3 #define PWR_D3CR_VOSREADY    BIT(13)
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[U-Boot] "usb storage" command issues

[Stefan Roese]

Hi,

I'm currently testing USB on my x86 platform. And noticed, that
the "usb storage" command does not work as expected:

=> usb reset  
resetting USB...
USB0:   Register 7000820 NbrPorts 7
Starting the controller
USB XHCI 1.00
scanning bus 0 for devices... 5 USB Device(s) found
   scanning usb for storage devices... 1 Storage Device(s) found
=> usb tree
USB device tree:
  1  Hub (5 Gb/s, 0mA)
  |  U-Boot XHCI Host Controller 
  |
  +-2  Mass Storage (480 Mb/s, 224mA)
  |SanDisk Ultra 4C530001010620110505
  |  
  +-3  Hub (480 Mb/s, 0mA)
|
+-4  Hub (480 Mb/s, 100mA)
  |
  +-5  Hub (12 Mb/s, 100mA)
 
=> usb storage
Card did not respond to voltage select!
mmc_init: -95, time 28
No storage devices, perhaps not 'usb start'ed..?


While debugging I found, that usb_stor_info() calls 
blk_first_device(IF_TYPE_USB, )
which calls uclass_first_device(UCLASS_BLK, devp). With my current DM tree:

=> dm tree
 Class   Probed   Name

 root[ + ]root_driver
...
 mmc [ + ]|   |-- pci_mmc
 blk [   ]|   |   `-- pci_mmc.blk
 mmc [ + ]|   |-- pci_mmc
 blk [   ]|   |   `-- pci_mmc.blk


the first BLK device is a MMC device. With uclass_first_device() its
probe function is called here, which fails in this case. Resulting in
an abort for the loop over all BLK devices.

How should this be handled for the "usb storage" command. Probing
all BLK devices while running this command seems a bit too much.

Any suggestions on how to fix this?

Thanks,
Stefan
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[U-Boot] [PATCH] test/overlay: Fix various malloc/free leaks

[Tom Rini]

With the overlay tests now being built in sandbox Coverity has found a
number of issues in the tests.  In short, if malloc ever failed we would
leak the previous mallocs, so we need to do the usual goto pattern to
free each in turn.  Finally, we always looked at the free()d location to
see how many tests had failed for the return code.

Reported-by: Coverity (CID: 167224, 167227, 167230, 167236)
Signed-off-by: Tom Rini 
---
 test/overlay/cmd_ut_overlay.c | 16 
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/test/overlay/cmd_ut_overlay.c b/test/overlay/cmd_ut_overlay.c
index 24891ee82901..c730a11f5188 100644
--- a/test/overlay/cmd_ut_overlay.c
+++ b/test/overlay/cmd_ut_overlay.c
@@ -226,6 +226,7 @@ int do_ut_overlay(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
void *fdt_overlay = &__dtb_test_fdt_overlay_begin;
void *fdt_overlay_stacked = &__dtb_test_fdt_overlay_stacked_begin;
void *fdt_base_copy, *fdt_overlay_copy, *fdt_overlay_stacked_copy;
+   int ret = -ENOMEM;
 
uts = calloc(1, sizeof(*uts));
if (!uts)
@@ -236,16 +237,16 @@ int do_ut_overlay(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
 
fdt_base_copy = malloc(FDT_COPY_SIZE);
if (!fdt_base_copy)
-   return -ENOMEM;
+   goto err1;
uts->priv = fdt_base_copy;
 
fdt_overlay_copy = malloc(FDT_COPY_SIZE);
if (!fdt_overlay_copy)
-   return -ENOMEM;
+   goto err2;
 
fdt_overlay_stacked_copy = malloc(FDT_COPY_SIZE);
if (!fdt_overlay_stacked_copy)
-   return -ENOMEM;
+   goto err3;
 
/*
 * Resize the FDT to 4k so that we have room to operate on
@@ -293,11 +294,18 @@ int do_ut_overlay(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
}
 
printf("Failures: %d\n", uts->fail_count);
+   if (!uts->fail_count)
+   ret = 0;
+   else
+   ret = CMD_RET_FAILURE;
 
free(fdt_overlay_stacked_copy);
+err3:
free(fdt_overlay_copy);
+err2:
free(fdt_base_copy);
+err1:
free(uts);
 
-   return uts->fail_count ? CMD_RET_FAILURE : 0;
+   return ret;
 }
-- 
1.9.1

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[U-Boot] Please pull u-boot-cfi-flash/master

[Stefan Roese]

Hi Tom,

please pull the following 2 patches from Marek for the CFI driver.

Thanks,
Stefan

The following changes since commit 1f6049e2501b5c35c61435dbc05ba96743202674:

  tools/mkimage: Make the path to the dtc binary that mkimage calls 
configurable (2017-09-24 07:33:03 -0400)

are available in the git repository at:

  git://www.denx.de/git/u-boot-cfi-flash.git 

for you to fetch changes up to 72443c7f7d2174903e73ee88dcb4364e0387bbb2:

  mtd: cfi: Add support for status register polling (2017-09-26 10:57:53 +0200)


Marek Vasut (2):
  mtd: cfi: Zap cfi_flash_base in DM case
  mtd: cfi: Add support for status register polling

 drivers/mtd/cfi_flash.c | 25 +++--
 include/flash.h |  5 +
 include/mtd/cfi_flash.h |  1 +
 3 files changed, 25 insertions(+), 6 deletions(-)
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Re: [U-Boot] [PATCH] mtd: cfi: Add support for status register polling

[Stefan Roese]

On 12.09.2017 19:09, Marek Vasut wrote:

The status register is optional in the AMD command sets, but it's
presence can be checked by reading out CFI table entry 0xc bit 0.
If the register is present, prefer using it's bit 7 to determine
if the flash is busy over reading the flash ; this is needed ie.
on Hyperflash memories.

Signed-off-by: Marek Vasut 


Applied to u-boot-cfi-flash/master.

Thanks,
Stefan
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Re: [U-Boot] [PATCH] mtd: cfi: Zap cfi_flash_base in DM case

[Stefan Roese]

On 12.09.2017 19:09, Marek Vasut wrote:

Embed the flash base into struct flash_info instead of having ad-hoc
static array in the code. This does not only remove static variable,
but also allows CFI-like controllers, ie. HyperFlash ones, to use most
of the CFI flash code by populating the flash_info with matching base
address.

Signed-off-by: Marek Vasut 


Applied to u-boot-cfi-flash/master.

Thanks,
Stefan
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Re: [U-Boot] [PATCH V3 1/5] mmc: uniphier-sd: Factor out register IO

[Masahiro Yamada]

2017-09-22 22:54 GMT+09:00 Jaehoon Chung :
> On 08/21/2017 12:11 AM, Marek Vasut wrote:
>> This patch prepares the driver to support controller(s) with registers
>> at locations shifted by constant. Pull out the readl()/writel() from
>> the driver into separate functions, where the adjustment of the register
>> offset can be easily contained.
>
> Sorry for late. Applied to u-boot-mmc about [PATCH 1/5~5/5].
> (After fixing some conflict - i did.)


What is worse, Jaehoon picked up wrong ones.
(seems v1)




-- 
Best Regards
Masahiro Yamada
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Re: [U-Boot] u-boot-usb/master sandbox unit test failure

[Bin Meng]

+Simon,

On Tue, Sep 26, 2017 at 10:14 PM, Bin Meng  wrote:
> On Tue, Sep 26, 2017 at 5:32 PM, Bin Meng  wrote:
>> Hi Stephen,
>>
>> On Tue, Sep 26, 2017 at 1:11 AM, Stephen Warren  
>> wrote:
>>> On 09/25/2017 10:40 AM, Marek Vasut wrote:

 On 09/25/2017 06:13 PM, Stephen Warren wrote:
>
> Marek,


 +CC Bin

 I will drop the xhci patchset and hope to get a fixed one from him.
>>>
>>>
>>> The latest branch content (0184c6fb34b4 "usb: dwc2: Align size of
>>> invalidating dcache before starting DMA") passes the tests.
>>>
>>
>> My tests shows that 'ut dm usb_flash' fails, and should have failed
>> for quite a long time.
>>
>> $ ./u-boot -d arch/sandbox/dts/test.dtb
>>
>>
>> U-Boot 2017.09-00337-g0184c6f (Sep 26 2017 - 17:29:31 +0800)
>>
>> Model: sandbox
>> DRAM:  128 MiB
>> MMC:   ** First descriptor is NOT a primary desc on 0:1 **
>> ** First descriptor is NOT a primary desc on 1:1 **
>> ** First descriptor is NOT a primary desc on 2:1 **
>> mmc2: 2 (SD), mmc1: 1 (SD), mmc0: 0 (SD)
>> Using default environment
>>
>> In:serial
>> Out:   vidconsole
>> Err:   vidconsole
>> Model: sandbox
>> SCSI:  Net:   eth0: eth@10002000, eth5: eth@10003000, eth3: sbe5,
>> eth1: eth@10004000
>> IDE:   Bus 0: not available
>> => ut dm usb_flash
>> Test: dm_test_usb_flash: usb.c
>> test/dm/usb.c:53, dm_test_usb_flash(): 2 == blk_dread(dev_desc, 0, 2,
>> cmp): Expected 2, got 0
>> Test: dm_test_usb_flash: usb.c (flat tree)
>> test/dm/usb.c:48, dm_test_usb_flash(): 0 ==
>> blk_get_device_by_str("usb", "0", _desc): Expected 0, got -2
>> Failures: 2
>>
>>>
> The latest u-boot-usb master branch breaks the following unit tests for
> the sandbox target (as run by test/py):
>
> 8 failed
> ... test_ut[ut_dm_blk_usb]
> ... test_ut[ut_dm_usb_flash]
> ... test_ut[ut_dm_usb_keyb]
> ... test_ut[ut_dm_usb_multi]
> ... test_ut[ut_dm_usb_remove]
> ... test_ut[ut_dm_usb_tree]
> ... test_ut[ut_dm_usb_tree_remove]
> ... test_ut[ut_dm_usb_tree_reorder]
>>
>> I've fixed all test failures except 'ut dm usb_flash'.
>>
>
> Looks I was jumping to conclusions. Previously I was just marking
> sandbox as an exception in the 'usb_stop', and all tests were passed.
> But I feel that's inconsistent. Now with a proper fix for sandbox, the
> 'usb remove' test no longer passed because I was trying to delete the
> "/usb@1/hub/hub-emul/flash-stick@1" node from device tree but a
> follow-up 'usb_init()' will fail. I am new to the sandbox emulator and
> still investigating this. Any hints?
>

Please check my WIP patch @
http://git.denx.de/?p=u-boot/u-boot-x86.git;a=commitdiff;h=e8481c91c295027f7ae2f4c59853c1c36f2e64f4
for fixing sandbox 'usb remove' issues.

Below are my test logs on Sandbox:

=> usb start
starting USB...
USB0:   scanning bus 1 for devices... 5 USB Device(s) found
   scanning usb for storage devices... 3 Storage Device(s) found
=> usb stop
stopping USB..
=> fdt addr -c
The address of the fdt is 0x5986ba0
=> fdt addr 0x5986ba0
=> fdt rm "/usb@1/hub/hub-emul/flash-stick@1"
=> usb start
starting USB...
USB0:   scanning bus 1 for devices...
  USB device not accepting new address (error=8000)
failed, error -2
   scanning usb for storage devices... 0 Storage Device(s) found

Any hints?

Regards,
Bin
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Re: [U-Boot] [PATCH v2 4/4] fs-test: Add test for a filename using '..' to go back to the root

[Tom Rini]

On Mon, Sep 25, 2017 at 10:06:34PM +0300, Tuomas Tynkkynen wrote:

> The previous commit fixed a problem in FAT code where going back to the
> root directory using '..' wouldn't work correctly on FAT12 or FAT16.
> Add a test to exercise this case (which was once fixed in commit
> 18a10d46f26 "fat: handle paths that include ../" but reintroduced due to
> the directory iterator refactoring).
> 
> This test only very barely catches the problem - without the fix the
> size command still gives valid output but the additional spurious
> "Invalid FAT entry" error message makes it not get caught in the
> 'egrep -A3 ' output. I tried to make a proper test that grows the root
> directory to two clusters lots of with dummy files but that causes the
> write tests to crash the sandbox totally...
> 
> Signed-off-by: Tuomas Tynkkynen 

Reviewed-by: Tom Rini 

-- 
Tom


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Re: [U-Boot] [PATCH v2 2/4] fs-test: Add FAT16 support

[Tom Rini]

On Mon, Sep 25, 2017 at 10:06:32PM +0300, Tuomas Tynkkynen wrote:

> Currently we can only test FAT32 which is the default FAT version that
> mkfs.vfat creates by default. Instead make it explicitly create either a
> FAT16 or a FAT32 volume. This allows us to exercise more code, for
> instance the root directory handling is done differently in FAT32 than
> the older FATs.
> 
> Adding FAT12 support is a much bigger job since the test creates a 2.5GB
> file and the FAT12 maximum partition size is way smaller than that.
> 
> Signed-off-by: Tuomas Tynkkynen 

Reviewed-by: Tom Rini 

-- 
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Re: [U-Boot] [PATCH v2 1/4] fs/ext4: Fix group descriptor checksum calculation

[Tom Rini]

On Mon, Sep 25, 2017 at 10:06:31PM +0300, Tuomas Tynkkynen wrote:
> The current code doesn't compute the group descriptor checksum correctly
> for the filesystems that e2fsprogs 1.43.4 creates (they have
> 'Group descriptor size: 64' as reported by tune2fs). Extend the checksum
> calculation to be done as ext4_group_desc_csum() does in Linux.
> 
> This fixes these errors in dmesg from running fs-test.sh and makes it
> succeed again:
> 
> [1671902.620699] EXT4-fs (loop1): ext4_check_descriptors: Checksum for group 
> 0 failed (35782!=10965)
> [1671902.620706] EXT4-fs (loop1): group descriptors corrupted!
> 
> Signed-off-by: Tuomas Tynkkynen 
> ---
> v2: New patch
> ---
>  fs/ext4/ext4_common.c | 4 
>  1 file changed, 4 insertions(+)
> 
> diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
> index 621c61e5c7..31952f48b9 100644
> --- a/fs/ext4/ext4_common.c
> +++ b/fs/ext4/ext4_common.c
> @@ -432,6 +432,10 @@ uint16_t ext4fs_checksum_update(uint32_t i)
>   crc = ext2fs_crc16(crc, desc, offset);
>   offset += sizeof(desc->bg_checksum);/* skip checksum */
>   assert(offset == sizeof(*desc));
> + if (offset < fs->gdsize) {
> + crc = ext2fs_crc16(crc, (__u8 *)desc + offset,
> +fs->gdsize - offset);
> + }

This would be feb0ab32a57e4e6c8b24f6fb68f0ce08efe4603c from the kernel?
So shouldn't we have le16_to_cpu on fs->gdsize ?  Or did I read over the
'git log -p' output in the kernel too quickly?  Thanks!

-- 
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Re: [U-Boot] strange behaviors with setexpr syntax error and '==' != '-eq"

[Clément Péron]

Dear Wolfgang Denk,

Thanks a lot for your explanations !
Clement

> I'm tempted to rephrase: you made some errors :-)


>> The first one is when I try to do a mask from a memory address and
>> store it to an env variable.
>>
>> => setexpr toto *{loadaddr} & 0xFF
>> syntax error
>> => setexpr toto *{loadaddr} & 0x3F
>> syntax error
>> => setexpr toto  0x3F & *{loadaddr}
>> syntax error
>
> This has nothing to dowith the setexpr command - the error message
> comes from the shell.  It will issue the same error for other uses
> of an (unmasked) ampersand:
>
> ->  echo a & echo b
> syntax error
>
>
> Note: you must always escape special characters.
>
> Also, you probably want to write ${loadaddr} (mind the dollar
> character).
>
> So try:
>
> setexpr toto *${loadaddr} '&' 0xFF
>
>> The second one is the difference between '==' and '-eq'
>>
>> => setenv a 1
>> => setenv b 2
>> => if test ${a} -eq ${b}; then echo toto; fi;
>> => if test ${a} == ${b}; then echo toto; fi;
>> toto
>>
>> Which doesn't seem logic.
>
> Well, did you read the man page for the test command?
>
> == is operating on STRING arguments, while -eq is operating on
> INTEGER arguments.  So depending on the content of your variables
> the result may be the same or different.
>
>
>
> Best regards,
>
> Wolfgang Denk
>
> --
> DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
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Re: [U-Boot] [PATCH] fs/fat: Fix 'CACHE: Misaligned operation at range' warnings

[Tom Rini]

On Tue, Sep 26, 2017 at 03:21:25PM +0300, Tuomas Tynkkynen wrote:

> The 'block' field of fat_itr needs to be properly aligned for DMA and
> while it does have '__aligned(ARCH_DMA_MINALIGN)', the fat_itr structure
> itself needs to be properly aligned as well.
> 
> While at it use malloc_cache_aligned() for other aligned allocations in
> the file.
> 
> Fixes: 2460098cffacd1 ("fs/fat: Reduce stack usage")
> Signed-off-by: Tuomas Tynkkynen 
> ---
>  fs/fat/fat.c | 10 +-
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/fs/fat/fat.c b/fs/fat/fat.c
> index 3d3e17e8fa..35941c1498 100644
> --- a/fs/fat/fat.c
> +++ b/fs/fat/fat.c
> @@ -495,7 +495,7 @@ read_bootsectandvi(boot_sector *bs, volume_info *volinfo, 
> int *fatsize)
>   return -1;
>   }
>  
> - block = memalign(ARCH_DMA_MINALIGN, cur_dev->blksz);
> + block = malloc_cache_aligned(cur_dev->blksz);
>   if (block == NULL) {
>   debug("Error: allocating block\n");
>   return -1;
> @@ -599,7 +599,7 @@ static int get_fs_info(fsdata *mydata)
>  
>   mydata->fatbufnum = -1;
>   mydata->fat_dirty = 0;
> - mydata->fatbuf = memalign(ARCH_DMA_MINALIGN, FATBUFSIZE);
> + mydata->fatbuf = malloc_cache_aligned(FATBUFSIZE);
>   if (mydata->fatbuf == NULL) {
>   debug("Error: allocating memory\n");
>   return -1;
> @@ -1038,7 +1038,7 @@ int fat_exists(const char *filename)
>   fat_itr *itr;
>   int ret;
>  
> - itr = malloc(sizeof(fat_itr));
> + itr = malloc_cache_aligned(sizeof(fat_itr));
>   ret = fat_itr_root(itr, );
>   if (ret)
>   return 0;

Coverity has informed me that I also introduced a resource leak here by
not freeing on failure of fat_itr_root (in each case).  Can you please
v2 where those are freed and add Reported-by: Coverity (CID: 167225,
167233, 167234) ?  Thanks!

-- 
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Re: [U-Boot] [PATCHv2] GPT: fix memory leaks identified by Coverity

[Tom Rini]

On Tue, Sep 26, 2017 at 07:42:28AM -0700, ali...@peloton-tech.com wrote:
> From: Alison Chaiken 
> 
> Create a common exit for most of the error handling code in
> do_rename_gpt_parts.   Delete the list elements in disk_partitions
> before calling INIT_LIST_HEAD from get_gpt_info() a second time.
> 
> The SIZEOF_MISMATCH error is not addressed, since that problem was
> already fixed by "GPT: incomplete initialization in
> allocate_disk_part".
> 
> Signed-off-by: Alison Chaiken 

Reported-by: Coverity (CID: 167222, 167235, 167237)

Reviewed-by: Tom Rini 

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[U-Boot] [PATCHv2] GPT: fix memory leaks identified by Coverity

[alison]

From: Alison Chaiken 

Create a common exit for most of the error handling code in
do_rename_gpt_parts.   Delete the list elements in disk_partitions
before calling INIT_LIST_HEAD from get_gpt_info() a second time.

The SIZEOF_MISMATCH error is not addressed, since that problem was
already fixed by "GPT: incomplete initialization in
allocate_disk_part".

Signed-off-by: Alison Chaiken 

---

 v2: Fix comment-formatting problems in v1.

 cmd/gpt.c | 87 ++-
 1 file changed, 69 insertions(+), 18 deletions(-)

diff --git a/cmd/gpt.c b/cmd/gpt.c
index d4406e3120..9e04affc06 100644
--- a/cmd/gpt.c
+++ b/cmd/gpt.c
@@ -633,6 +633,21 @@ static int do_disk_guid(struct blk_desc *dev_desc, char * 
const namestr)
 }
 
 #ifdef CONFIG_CMD_GPT_RENAME
+/*
+ * There are 3 malloc() calls in set_gpt_info() and there is no info about 
which
+ * failed.
+ */
+static void set_gpt_cleanup(char **str_disk_guid,
+   disk_partition_t **partitions)
+{
+#ifdef CONFIG_RANDOM_UUID
+   if (str_disk_guid)
+   free(str_disk_guid);
+#endif
+   if (partitions)
+   free(partitions);
+}
+
 static int do_rename_gpt_parts(struct blk_desc *dev_desc, char *subcomm,
   char *name1, char *name2)
 {
@@ -651,19 +666,27 @@ static int do_rename_gpt_parts(struct blk_desc *dev_desc, 
char *subcomm,
ret = get_disk_guid(dev_desc, disk_guid);
if (ret < 0)
return ret;
+   /*
+* Allocates disk_partitions, requiring matching call to del_gpt_info()
+* if successful.
+*/
numparts = get_gpt_info(dev_desc);
if (numparts <=  0)
return numparts ? numparts : -ENODEV;
 
partlistlen = calc_parts_list_len(numparts);
partitions_list = malloc(partlistlen);
-   if (partitions_list == NULL)
+   if (!partitions_list) {
+   del_gpt_info();
return -ENOMEM;
+   }
memset(partitions_list, '\0', partlistlen);
 
ret = create_gpt_partitions_list(numparts, disk_guid, partitions_list);
-   if (ret < 0)
+   if (ret < 0) {
+   free(partitions_list);
return ret;
+   }
/*
 * Uncomment the following line to print a string that 'gpt write'
 * or 'gpt verify' will accept as input.
@@ -671,15 +694,23 @@ static int do_rename_gpt_parts(struct blk_desc *dev_desc, 
char *subcomm,
debug("OLD partitions_list is %s with %u chars\n", partitions_list,
  (unsigned)strlen(partitions_list));
 
+   /* set_gpt_info allocates new_partitions and str_disk_guid */
ret = set_gpt_info(dev_desc, partitions_list, _disk_guid,
   _partitions, _count);
-   if (ret < 0)
-   return ret;
+   if (ret < 0) {
+   del_gpt_info();
+   free(partitions_list);
+   if (ret == -ENOMEM)
+   set_gpt_cleanup(_disk_guid, _partitions);
+   else
+   goto out;
+   }
 
if (!strcmp(subcomm, "swap")) {
if ((strlen(name1) > PART_NAME_LEN) || (strlen(name2) > 
PART_NAME_LEN)) {
printf("Names longer than %d characters are 
truncated.\n", PART_NAME_LEN);
-   return -EINVAL;
+   ret = -EINVAL;
+   goto out;
}
list_for_each(pos, _partitions) {
curr = list_entry(pos, struct disk_part, list);
@@ -693,21 +724,24 @@ static int do_rename_gpt_parts(struct blk_desc *dev_desc, 
char *subcomm,
}
if ((ctr1 + ctr2 < 2) || (ctr1 != ctr2)) {
printf("Cannot swap partition names except in 
pairs.\n");
-   return -EINVAL;
+   ret = -EINVAL;
+   goto out;
}
} else { /* rename */
if (strlen(name2) > PART_NAME_LEN) {
printf("Names longer than %d characters are 
truncated.\n", PART_NAME_LEN);
-   return -EINVAL;
+   ret = -EINVAL;
+   goto out;
}
partnum = (int)simple_strtol(name1, NULL, 10);
if ((partnum < 0) || (partnum > numparts)) {
printf("Illegal partition number %s\n", name1);
-   return -EINVAL;
+   ret = -EINVAL;
+   goto out;
}
ret = part_get_info(dev_desc, partnum, new_partitions);
if (ret < 0)
-   return ret;
+   goto out;
 
/* U-Boot partition numbering starts at 1 */
list_for_each(pos, _partitions) {
@@ -722,33 +756,50 @@ static int 

Re: [U-Boot] [PATCHv2] GPT: fix memory leaks identified by Coverity

[Bin Meng]

Hi,

On Tue, Sep 26, 2017 at 10:39 PM,   wrote:
> From: Alison Chaiken 
>
> Create a common exit for most of the error handling code in
> do_rename_gpt_parts.   Delete the list elements in disk_partitions
> before calling INIT_LIST_HEAD from get_gpt_info() a second time.
>
> The SIZEOF_MISMATCH error is not addressed, since that problem was
> already fixed by "GPT: incomplete initialization in
> allocate_disk_part".
>
> Signed-off-by: Alison Chaiken 
>
> v2: Fix comment-formatting problems in v1.

Please move the change log below ---

>
> ---

Regards,
Bin
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Re: [U-Boot] strange behaviors with setexpr syntax error and '==' != '-eq"

[Wolfgang Denk]

Dear Clément Péron,

In message  
you wrote:
> 
> I write a script on u-boot but i found 2 strange behaviors.

I'm tempted to rephrase: you made some errors :-)

> The first one is when I try to do a mask from a memory address and
> store it to an env variable.
> 
> => setexpr toto *{loadaddr} & 0xFF
> syntax error
> => setexpr toto *{loadaddr} & 0x3F
> syntax error
> => setexpr toto  0x3F & *{loadaddr}
> syntax error

This has nothing to dowith the setexpr command - the error message
comes from the shell.  It will issue the same error for other uses
of an (unmasked) ampersand:

->  echo a & echo b
syntax error


Note: you must always escape special characters.

Also, you probably want to write ${loadaddr} (mind the dollar
character).

So try:

setexpr toto *${loadaddr} '&' 0xFF

> The second one is the difference between '==' and '-eq'
> 
> => setenv a 1
> => setenv b 2
> => if test ${a} -eq ${b}; then echo toto; fi;
> => if test ${a} == ${b}; then echo toto; fi;
> toto
> 
> Which doesn't seem logic.

Well, did you read the man page for the test command?

== is operating on STRING arguments, while -eq is operating on
INTEGER arguments.  So depending on the content of your variables
the result may be the same or different.



Best regards,

Wolfgang Denk

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[U-Boot] [PATCHv2] GPT: fix memory leaks identified by Coverity

[alison]

From: Alison Chaiken 

Create a common exit for most of the error handling code in
do_rename_gpt_parts.   Delete the list elements in disk_partitions
before calling INIT_LIST_HEAD from get_gpt_info() a second time.

The SIZEOF_MISMATCH error is not addressed, since that problem was
already fixed by "GPT: incomplete initialization in
allocate_disk_part".

Signed-off-by: Alison Chaiken 

v2: Fix comment-formatting problems in v1.

---
 cmd/gpt.c | 87 ++-
 1 file changed, 69 insertions(+), 18 deletions(-)

diff --git a/cmd/gpt.c b/cmd/gpt.c
index d4406e3120..9e04affc06 100644
--- a/cmd/gpt.c
+++ b/cmd/gpt.c
@@ -633,6 +633,21 @@ static int do_disk_guid(struct blk_desc *dev_desc, char * 
const namestr)
 }
 
 #ifdef CONFIG_CMD_GPT_RENAME
+/*
+ * There are 3 malloc() calls in set_gpt_info() and there is no info about 
which
+ * failed.
+ */
+static void set_gpt_cleanup(char **str_disk_guid,
+   disk_partition_t **partitions)
+{
+#ifdef CONFIG_RANDOM_UUID
+   if (str_disk_guid)
+   free(str_disk_guid);
+#endif
+   if (partitions)
+   free(partitions);
+}
+
 static int do_rename_gpt_parts(struct blk_desc *dev_desc, char *subcomm,
   char *name1, char *name2)
 {
@@ -651,19 +666,27 @@ static int do_rename_gpt_parts(struct blk_desc *dev_desc, 
char *subcomm,
ret = get_disk_guid(dev_desc, disk_guid);
if (ret < 0)
return ret;
+   /*
+* Allocates disk_partitions, requiring matching call to del_gpt_info()
+* if successful.
+*/
numparts = get_gpt_info(dev_desc);
if (numparts <=  0)
return numparts ? numparts : -ENODEV;
 
partlistlen = calc_parts_list_len(numparts);
partitions_list = malloc(partlistlen);
-   if (partitions_list == NULL)
+   if (!partitions_list) {
+   del_gpt_info();
return -ENOMEM;
+   }
memset(partitions_list, '\0', partlistlen);
 
ret = create_gpt_partitions_list(numparts, disk_guid, partitions_list);
-   if (ret < 0)
+   if (ret < 0) {
+   free(partitions_list);
return ret;
+   }
/*
 * Uncomment the following line to print a string that 'gpt write'
 * or 'gpt verify' will accept as input.
@@ -671,15 +694,23 @@ static int do_rename_gpt_parts(struct blk_desc *dev_desc, 
char *subcomm,
debug("OLD partitions_list is %s with %u chars\n", partitions_list,
  (unsigned)strlen(partitions_list));
 
+   /* set_gpt_info allocates new_partitions and str_disk_guid */
ret = set_gpt_info(dev_desc, partitions_list, _disk_guid,
   _partitions, _count);
-   if (ret < 0)
-   return ret;
+   if (ret < 0) {
+   del_gpt_info();
+   free(partitions_list);
+   if (ret == -ENOMEM)
+   set_gpt_cleanup(_disk_guid, _partitions);
+   else
+   goto out;
+   }
 
if (!strcmp(subcomm, "swap")) {
if ((strlen(name1) > PART_NAME_LEN) || (strlen(name2) > 
PART_NAME_LEN)) {
printf("Names longer than %d characters are 
truncated.\n", PART_NAME_LEN);
-   return -EINVAL;
+   ret = -EINVAL;
+   goto out;
}
list_for_each(pos, _partitions) {
curr = list_entry(pos, struct disk_part, list);
@@ -693,21 +724,24 @@ static int do_rename_gpt_parts(struct blk_desc *dev_desc, 
char *subcomm,
}
if ((ctr1 + ctr2 < 2) || (ctr1 != ctr2)) {
printf("Cannot swap partition names except in 
pairs.\n");
-   return -EINVAL;
+   ret = -EINVAL;
+   goto out;
}
} else { /* rename */
if (strlen(name2) > PART_NAME_LEN) {
printf("Names longer than %d characters are 
truncated.\n", PART_NAME_LEN);
-   return -EINVAL;
+   ret = -EINVAL;
+   goto out;
}
partnum = (int)simple_strtol(name1, NULL, 10);
if ((partnum < 0) || (partnum > numparts)) {
printf("Illegal partition number %s\n", name1);
-   return -EINVAL;
+   ret = -EINVAL;
+   goto out;
}
ret = part_get_info(dev_desc, partnum, new_partitions);
if (ret < 0)
-   return ret;
+   goto out;
 
/* U-Boot partition numbering starts at 1 */
list_for_each(pos, _partitions) {
@@ -722,33 +756,50 @@ static int 

Re: [U-Boot] [PATCH] sunxi: clk: fix N formula for CPUX clocks

[Maxime Ripard]

On Tue, Sep 26, 2017 at 02:02:47PM +, Quentin Schulz wrote:
> As explained in arch/arm/mach-sunxi/clock_sun8i_a83t.c, clk for CPU
> clusters is computed as clk = 24*n. However, the current formula is clk
> = 24*(n-1).
> 
> This results in a clock set to a frequency that isn't specified as
> possible for CPUs.
> 
> Let's use the correct formula.
> 
> Fixes: f542948b1e8c ("sunxi: clk: add basic clocks for A83T")
> Signed-off-by: Quentin Schulz 

Acked-by: Maxime Ripard 

Maxime

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[U-Boot] strange behaviors with setexpr syntax error and '==' != '-eq"

[Clément Péron]

Hi,

I write a script on u-boot but i found 2 strange behaviors.

The first one is when I try to do a mask from a memory address and
store it to an env variable.

=> setexpr toto *{loadaddr} & 0xFF
syntax error
=> setexpr toto *{loadaddr} & 0x3F
syntax error
=> setexpr toto  0x3F & *{loadaddr}
syntax error

The second one is the difference between '==' and '-eq'

=> setenv a 1
=> setenv b 2
=> if test ${a} -eq ${b}; then echo toto; fi;
=> if test ${a} == ${b}; then echo toto; fi;
toto

Which doesn't seem logic.

Could you please explain me these behaviors ?

Thanks,
Clement
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Re: [U-Boot] u-boot-usb/master sandbox unit test failure

[Bin Meng]

On Tue, Sep 26, 2017 at 5:32 PM, Bin Meng  wrote:
> Hi Stephen,
>
> On Tue, Sep 26, 2017 at 1:11 AM, Stephen Warren  wrote:
>> On 09/25/2017 10:40 AM, Marek Vasut wrote:
>>>
>>> On 09/25/2017 06:13 PM, Stephen Warren wrote:

 Marek,
>>>
>>>
>>> +CC Bin
>>>
>>> I will drop the xhci patchset and hope to get a fixed one from him.
>>
>>
>> The latest branch content (0184c6fb34b4 "usb: dwc2: Align size of
>> invalidating dcache before starting DMA") passes the tests.
>>
>
> My tests shows that 'ut dm usb_flash' fails, and should have failed
> for quite a long time.
>
> $ ./u-boot -d arch/sandbox/dts/test.dtb
>
>
> U-Boot 2017.09-00337-g0184c6f (Sep 26 2017 - 17:29:31 +0800)
>
> Model: sandbox
> DRAM:  128 MiB
> MMC:   ** First descriptor is NOT a primary desc on 0:1 **
> ** First descriptor is NOT a primary desc on 1:1 **
> ** First descriptor is NOT a primary desc on 2:1 **
> mmc2: 2 (SD), mmc1: 1 (SD), mmc0: 0 (SD)
> Using default environment
>
> In:serial
> Out:   vidconsole
> Err:   vidconsole
> Model: sandbox
> SCSI:  Net:   eth0: eth@10002000, eth5: eth@10003000, eth3: sbe5,
> eth1: eth@10004000
> IDE:   Bus 0: not available
> => ut dm usb_flash
> Test: dm_test_usb_flash: usb.c
> test/dm/usb.c:53, dm_test_usb_flash(): 2 == blk_dread(dev_desc, 0, 2,
> cmp): Expected 2, got 0
> Test: dm_test_usb_flash: usb.c (flat tree)
> test/dm/usb.c:48, dm_test_usb_flash(): 0 ==
> blk_get_device_by_str("usb", "0", _desc): Expected 0, got -2
> Failures: 2
>
>>
 The latest u-boot-usb master branch breaks the following unit tests for
 the sandbox target (as run by test/py):

 8 failed
 ... test_ut[ut_dm_blk_usb]
 ... test_ut[ut_dm_usb_flash]
 ... test_ut[ut_dm_usb_keyb]
 ... test_ut[ut_dm_usb_multi]
 ... test_ut[ut_dm_usb_remove]
 ... test_ut[ut_dm_usb_tree]
 ... test_ut[ut_dm_usb_tree_remove]
 ... test_ut[ut_dm_usb_tree_reorder]
>
> I've fixed all test failures except 'ut dm usb_flash'.
>

Looks I was jumping to conclusions. Previously I was just marking
sandbox as an exception in the 'usb_stop', and all tests were passed.
But I feel that's inconsistent. Now with a proper fix for sandbox, the
'usb remove' test no longer passed because I was trying to delete the
"/usb@1/hub/hub-emul/flash-stick@1" node from device tree but a
follow-up 'usb_init()' will fail. I am new to the sandbox emulator and
still investigating this. Any hints?

Regards,
Bin
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[U-Boot] [PATCH] sunxi: clk: fix N formula for CPUX clocks

[Quentin Schulz]

As explained in arch/arm/mach-sunxi/clock_sun8i_a83t.c, clk for CPU
clusters is computed as clk = 24*n. However, the current formula is clk
= 24*(n-1).

This results in a clock set to a frequency that isn't specified as
possible for CPUs.

Let's use the correct formula.

Fixes: f542948b1e8c ("sunxi: clk: add basic clocks for A83T")

Signed-off-by: Quentin Schulz 
---
 arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h 
b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h
index 5e1346e524..c4f5f5f958 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h
@@ -158,7 +158,7 @@ struct sunxi_ccm_reg {
 #define CPU_CLK_SRC_OSC24M 0
 #define CPU_CLK_SRC_PLL1   1
 
-#define CCM_PLL1_CTRL_N(n) n) - 1) & 0xff) << 8)
+#define CCM_PLL1_CTRL_N(n) (((n) & 0xff) << 8)
 #define CCM_PLL1_CTRL_P(n) (((n) & 0x1) << 16)
 #define CCM_PLL1_CTRL_EN   (0x1 << 31)
 #define CMM_PLL1_CLOCK_TIME_2  (0x2 << 24)
-- 
2.11.0

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Re: [U-Boot] [PATCH v2 3/9] dm: clk: add clk driver support for stm32h7 SoCs

[Patrice CHOTARD]

Hi Vikas

On 09/26/2017 10:51 AM, Patrice CHOTARD wrote:
> Hi Vikas
> 
> On 09/25/2017 09:51 AM, Patrice CHOTARD wrote:
>> Hi Vikas
>>
>> On 09/20/2017 03:39 AM, Vikas Manocha wrote:
>>> Hi Patrice,
>>>
>>> On 09/13/2017 09:00 AM, patrice.chot...@st.com wrote:
 From: Patrice Chotard 

 This driver implements basic clock setup, only clock gating
 is implemented.

 This driver doesn't implement .of_match as it's binded
 by MFD RCC driver.

 Files include/dt-bindings/clock/stm32h7-clks.h and
 doc/device-tree-bindings/clock/st,stm32h7-rcc.txt
 will be available soon in a kernel tag, as all the
 bindings have been acked by Rob Herring [1].

 [1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html

 Signed-off-by: Patrice Chotard 
 ---
> 
> [...]
> 
 +
 +#define PWR_CR3    0x0c
 +#define PWR_CR3_SDEN    BIT(2)
>>>
>>> Can we use SCUEN suffix to match the Ref Manual.
>>
>> Which version of reference manual do you use ? in mine its SDEN, but i 
>> propably use a too old ref manual.
>>
> 
> I have found the last version of STM32H7 ref manual, mine was too old,
> ok i will update the PWR_CR3_SDEN to PWR_CR3_SCUEN

After double check, in the STM32H7x3 reference manual available on 
st.com (DocID029587 Rev 2), bit 2 of PWR_CR3 reg is described as following:

"Bit 2 SCUEN: Supply configuration update enable
This bit is read-only:
0: Supply configuration update locked.
1: Single write enabled to Supply configuration (LDOEN and BYPASS)"

Whereas in the one i used, bit 2 of PWR_CR3 is described as:

"Bit 2 SDEN (1)(2) : SD converter Enable
0: Step down converter disabled
1: Step down converter enabled. (Default)"

If i follow ref manual DocID029587 Rev 2, this bit is read-only, so the 
write access of PWR_CR3 bit(2) in clk_stm32h7.c is useless. But after 
write access removal, the both STM32H7 disco and eval board doesn't boot.

The reference manual is wrong regarding with at least this bit. I will
contact PWR architect to solve this point.

Patrice


> 
> thanks
> 
> Patrice
> 
>>>
 +#define PWR_D3CR    0x18
 +#define PWR_D3CR_VOS_MASK    GENMASK(15, 14)
 +#define PWR_D3CR_VOS_SHIFT    14
 +#define    VOS_SCALE_3    1
 +#define    VOS_SCALE_2    2
 +#define    VOS_SCALE_1    3
 +#define PWR_D3CR_VOSREADY    BIT(13)
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Re: [U-Boot] [PULL] u-boot-usb/master

[Tom Rini]

On Mon, Sep 25, 2017 at 06:41:58PM +0200, Marek Vasut wrote:

> The following changes since commit 1f6049e2501b5c35c61435dbc05ba96743202674:
> 
>   tools/mkimage: Make the path to the dtc binary that mkimage calls
> configurable (2017-09-24 07:33:03 -0400)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-usb.git master
> 
> for you to fetch changes up to 0184c6fb34b49f0bb1ffc7b0e35a597de339353e:
> 
>   usb: dwc2: Align size of invalidating dcache before starting DMA
> (2017-09-24 18:45:56 +0200)
> 

This breaks building of vyasa-rk3288 and introduces a bunch of warnings
over stuff that's in Kconfig being re-added to config.h files.  And I
guess the rockusb stuff was applied oddly, all of the comments below the
'---' are in the commit message rather than discarded as usual.  Sorry,
thanks!

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[U-Boot] [PATCH] fs/fat: Fix 'CACHE: Misaligned operation at range' warnings

[Tuomas Tynkkynen]

The 'block' field of fat_itr needs to be properly aligned for DMA and
while it does have '__aligned(ARCH_DMA_MINALIGN)', the fat_itr structure
itself needs to be properly aligned as well.

While at it use malloc_cache_aligned() for other aligned allocations in
the file.

Fixes: 2460098cffacd1 ("fs/fat: Reduce stack usage")
Signed-off-by: Tuomas Tynkkynen 
---
 fs/fat/fat.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index 3d3e17e8fa..35941c1498 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -495,7 +495,7 @@ read_bootsectandvi(boot_sector *bs, volume_info *volinfo, 
int *fatsize)
return -1;
}
 
-   block = memalign(ARCH_DMA_MINALIGN, cur_dev->blksz);
+   block = malloc_cache_aligned(cur_dev->blksz);
if (block == NULL) {
debug("Error: allocating block\n");
return -1;
@@ -599,7 +599,7 @@ static int get_fs_info(fsdata *mydata)
 
mydata->fatbufnum = -1;
mydata->fat_dirty = 0;
-   mydata->fatbuf = memalign(ARCH_DMA_MINALIGN, FATBUFSIZE);
+   mydata->fatbuf = malloc_cache_aligned(FATBUFSIZE);
if (mydata->fatbuf == NULL) {
debug("Error: allocating memory\n");
return -1;
@@ -1038,7 +1038,7 @@ int fat_exists(const char *filename)
fat_itr *itr;
int ret;
 
-   itr = malloc(sizeof(fat_itr));
+   itr = malloc_cache_aligned(sizeof(fat_itr));
ret = fat_itr_root(itr, );
if (ret)
return 0;
@@ -1055,7 +1055,7 @@ int fat_size(const char *filename, loff_t *size)
fat_itr *itr;
int ret;
 
-   itr = malloc(sizeof(fat_itr));
+   itr = malloc_cache_aligned(sizeof(fat_itr));
ret = fat_itr_root(itr, );
if (ret)
return ret;
@@ -1089,7 +1089,7 @@ int file_fat_read_at(const char *filename, loff_t pos, 
void *buffer,
fat_itr *itr;
int ret;
 
-   itr = malloc(sizeof(fat_itr));
+   itr = malloc_cache_aligned(sizeof(fat_itr));
ret = fat_itr_root(itr, );
if (ret)
return ret;
-- 
2.13.0

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Re: [U-Boot] [GIT PULL] Please pull u-boot-mmc master

[Tom Rini]

On Mon, Sep 25, 2017 at 02:31:03PM +0900, Jaehoon Chung wrote:

> Dear Tom,
> 
> Could you pull these patches into u-boot/master?
> If there is a problem, let me know, plz.
> 
> Other patches needs to check more, so i didn't apply them.
> If i need to send PR again, i will send the PR as "take v2" for other patches.
> (Patches relevant to HS200 and omap_hsmmc.)
> 
> The following changes since commit e884656c2c0b2406b9bf99ea76f5a8c75128a331:
> 
>   Merge git://www.denx.de/git/u-boot-imx (2017-09-20 12:32:34 -0400)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-mmc.git master
> 
> for you to fetch changes up to 8ff7763d62d09c541e398239b7e4e3a5e732d273:
> 
>   regulator: pbias: Add PBIAS regulator for proper voltage switching on MMC1 
> (2017-09-22 23:23:54 +0900)
> 

Applied to u-boot/master, thanks!

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Re: [U-Boot] Pull request: u-boot-spi/master

[Tom Rini]

On Mon, Sep 25, 2017 at 01:21:35PM +0530, Jagan Teki wrote:

> Hi Tom,
> 
> Please pull this PR.
> 
> thanks!
> Jagan.
> 
> The following changes since commit 1f6049e2501b5c35c61435dbc05ba96743202674:
> 
>   tools/mkimage: Make the path to the dtc binary that mkimage calls 
> configurable (2017-09-24 07:33:03 -0400)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-spi.git master
> 
> for you to fetch changes up to db10809c17c7cd8960d0c45248bbef6e76251ad7:
> 
>   Fix s25fl256s position in spi_flash_ids list (2017-09-25 13:00:34 +0530)
> 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH v2 2/2] wandboard: Add support for the MX6QP variant

[Stefano Babic]

On 26/09/2017 13:19, Fabio Estevam wrote:
> Hi Stefano,
> 
> On Wed, Sep 20, 2017 at 8:17 PM, Fabio Estevam  wrote:
>> From: Fabio Estevam 
>>
>> Add support for the latest MX6QP wandboard variant.
>>
>> Based on Richard Hu's work from Technexion's U-Boot tree.
>>
>> Signed-off-by: Fabio Estevam 
>> ---
>> Changes since v1:
>> - None
> 
> Please disconsider this one as I noticed an issue. Patch 1/2 is
> working fine, but 2/2 is not, so I will have to debug it.
> 

Ok, thanks, I'll do.

Stefano

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Re: [U-Boot] u-boot Boot issue about rk3188

[Paweł Jarosz]

Hi,


W dniu 25.09.2017 o 12:29, Heiko Stübner pisze:

Hi Andy,

Am Montag, 25. September 2017, 17:45:03 CEST schrieb Andy Yan:

On 2017年09月22日 13:56, Heiko Stuebner wrote:

Am Freitag, 22. September 2017, 08:50:49 CEST schrieb Andy Yan:

Hi Heiko:

On 2017年09月22日 08:24, Andy Yan wrote:

Hi Heiko:

On 2017年09月21日 22:55, Heiko Stübner wrote:

Hi Andy,

Am Donnerstag, 21. September 2017, 22:03:32 CEST schrieb Andy Yan:

Hi Heiko:
I try to boot the upstream u-boot-rockchip branch  on my rk3188 board
with(rock_defconfig)

But I got this error:
early_init()
nit_and_scan() returned error -22
early_init() failed: -22
ERROR ### Please RESET the board ###

the current commit head is: 782088d("rockchip: imply ADC and
SARADC_ROCKCHIP
on supported SoCs") Do you ever meet something like this?

that is very strange. When testing Philipp's branch, I was also
testing the
commit you mention to see if anything broke since I last changed u-boot
on my radxa rock. And the above commit started just fine, when starting
from an sd-card.

Not sure from which medium you're starting though. But from what I
remember Pawel got nand working in his rk3066 series, but that is not
yet merged.


  I boot from emmc, I will go on hack on it.
  

   I finally can boot it with the rock_defconfig. But the way to

package the tpl spl u-boot a little different.

   cat ${DIR}/out/tpl/u-boot-tpl.bin > tplspl.bin
   truncate -s 1020 tplspl.bin
  
  sed -i "/^/{1s/^/RK31/}" tplspl.bin

  cat ${DIR}/out/spl/u-boot-spl.bin > spl.bin
  truncate -s %2048 spl.bin
  cat spl.bin >> tplspl.bin
  
  Then the tplspl.bin + u-boot.bin should package by


boot_merger(tplsplb.in for FLashData, u-boot.bin for FlashBoot) from

rockchip downstream u-boot repo:
  ./tools/boot_merger ./tools/rk_tools/RKBOOT/RK310BMINIALL.ini
  
  download to emmc by "upgrade_tool ul" command. According to our


bootrom code author, the rk31(maybe include rk30) bootrom has a
limitation that the idbblock
couldn't accessed by upgrade_tool wl command.

I do have a script handling that [0]. At least for the sd-card variant
a simple "openssl rc4" works just as well as the legacy boot_merger :-)

Heiko

[0]
https://github.com/mmind/u-boot-rockchip/commit/81458bde873d6cf588e082ccf
556e818f46ad9df

 Is there a way to download the out that generated by[0] to
emmc/flash? It seems that the upgrate_tool can't access 0x40 of the
emmc/nand on rk3188.

you have the @rock-chips.com address, so I'd guess you might even have
the better resources to find out ;-)  .

In any case, as I said I haven't looked at all at the internal storage on
my radxarock so far.

But as the rk3066 and rk3188 are so similar I've added Paweł.

@Paweł: you had uboot starting from nand on your rk3066 board, maybe you
could describe how you wrote it to the board so maybe Andy can check if
he needs to adapt anything?
Almost all knowledge i had about rk3066 boot process was from Heiko and 
bootrom disassembly.


Andy, do you have any output on serial console ? (TPL, Uboot-spl or 
anything else)
Can you compile u-boot with #define DEBUG in rk3188_common and send the 
output?
Also you can check size of u-boot tpl (less than 1kb), u-boot spl + tpl 
(less than sram size on rk3188, i think it's 32KB)? This is important as 
you wont get any output on serial console if you don't meet this conditions.
Also on rk3066 bootmerger FlashBoot size + FlashData size should be less 
than 256KB (32KB for FlashData, and the rest for FlashBoot, if it's more 
than 256KB, you get few lines of errors when flashing with upgrade_tool 
and might have no output on serial console)


One more thing ... to boot from usb with openssl rc4 method on rk3066 i 
think only one back to bootrom is needed, two if you are booting from nand.


Cheers
Paweł

Thanks
Heiko


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Re: [U-Boot] [PATCH v2 2/2] wandboard: Add support for the MX6QP variant

[Fabio Estevam]

Hi Stefano,

On Wed, Sep 20, 2017 at 8:17 PM, Fabio Estevam  wrote:
> From: Fabio Estevam 
>
> Add support for the latest MX6QP wandboard variant.
>
> Based on Richard Hu's work from Technexion's U-Boot tree.
>
> Signed-off-by: Fabio Estevam 
> ---
> Changes since v1:
> - None

Please disconsider this one as I noticed an issue. Patch 1/2 is
working fine, but 2/2 is not, so I will have to debug it.

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Re: [U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for programing FPGA from flash

[Marek Vasut]

On 09/26/2017 11:52 AM, Chee, Tien Fong wrote:
> On Isn, 2017-09-25 at 11:14 +0200, Marek Vasut wrote:
>> On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
>>>
>>> From: Tien Fong Chee 
>>>
>>> These drivers handle FPGA program operation from flash loading
>>> RBF to memory and then to program FPGA.
>>>
>>> Signed-off-by: Tien Fong Chee 

[...]

>>> +const char *get_cff_devpart(const void *fdt, int *len)
>>> +{
>>> +   const char *cff_devpart = NULL;
>>> +   const char *cell;
>>> +   int nodeoffset;
>>> +   nodeoffset = fdtdec_next_compatible(fdt, 0,
>>> +    COMPAT_ALTERA_SOCFPGA_FPGA0);
>>> +
>>> +   cell = fdt_getprop(fdt, nodeoffset, "bitstream_devpart",
>>> len);
>>> +
>>> +   if (cell)
>>> +   cff_devpart = cell;
>>> +
>>> +   return cff_devpart;
>>> +}
>> Take a look at splash*.c , I believe that can be reworked into
>> generic
>> firmware loader , which you could then use here.
>>
> the devpart is hard coded in splash*.c. The function here is getting
> devpart info from DTS. So, is there any similar function in splash*.c?
> May be you can share more about your idea.

The generic loader could use some work of course ...

[...]

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Re: [U-Boot] [PATCH v2 19/19] arm: socfpga: Enable SPL loading U-boot to DDR and booting U-boot

[Marek Vasut]

On 09/26/2017 06:31 AM, Chee, Tien Fong wrote:
> On Isn, 2017-09-25 at 11:24 +0200, Marek Vasut wrote:
>> On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
>>>
>>> From: Tien Fong Chee 
>>>
>>> Enable SPL loading U-boot from SDMMC to DDR and booting U-boot.
>> This patch seems to be doing more than just one thing ...
>>
> I can split into two patches:
> 1) Enable DDR up by configuring FPGA so SPL able loading U-boot to DDR
> 2) Setting up configs so SPL can boot U-boot from FAT.

Split it so that one patch does one thing.

>>>
>>> Signed-off-by: Tien Fong Chee 
>>> ---
>>>  arch/arm/mach-socfpga/spl.c   | 55
>>> +
>>>  common/spl/spl_mmc.c  |  2 +-
>>>  configs/socfpga_arria10_defconfig | 57
>>> ++-
>>>  include/spl.h |  2 ++
>>>  4 files changed, 108 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-
>>> socfpga/spl.c
>>> index aba116d..9b381bb 100644
>>> --- a/arch/arm/mach-socfpga/spl.c
>>> +++ b/arch/arm/mach-socfpga/spl.c
>>> @@ -15,6 +15,7 @@
>>>  #include 
>>>  #include 
>>>  #include 
>>> +#include 
>>>  #include 
>>>  #include 
>>>  #include 
>>> @@ -22,6 +23,10 @@
>>>  #include 
>>>  #include 
>>>  #include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>>  #include 
>>>  #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>>>  #include 
>>> @@ -29,6 +34,9 @@
>>>  
>>>  DECLARE_GLOBAL_DATA_PTR;
>>>  
>>> +#define BSIZE  4096
>>> +#define PERIPH_RBF 0
>>> +
>>>  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>>  static struct pl310_regs *const pl310 =
>>>     (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
>>> @@ -197,6 +205,12 @@ void board_init_f(ulong dummy)
>>>  #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>>>  void spl_board_init(void)
>>>  {
>>> +   int rval = 0;
>>> +   int len = 0;
>>> +   u32 buffer[BSIZE] __aligned(ARCH_DMA_MINALIGN);
>>> +   struct spl_boot_device bootdev;
>>> +   fpga_fs_info fpga_fsinfo;
>>> +
>>>     /* configuring the clock based on handoff */
>>>     cm_basic_init(gd->fdt_blob);
>>>     WATCHDOG_RESET();
>>> @@ -214,6 +228,47 @@ void spl_board_init(void)
>>>  
>>>     /* Add device descriptor to FPGA device table */
>>>     socfpga_fpga_add();
>>> +
>>> +   bootdev.boot_device = spl_boot_device();
>>> +
>>> +   if (BOOT_DEVICE_MMC1 == bootdev.boot_device) {
>>> +   struct mmc *mmc = NULL;
>>> +   int err = 0;
>>> +
>>> +   spl_mmc_find_device(, bootdev.boot_device);
>>> +
>>> +   err = mmc_init(mmc);
>>> +
>>> +   if (err) {
>>> +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
>>> +   printf("spl: mmc init failed with error:
>>> %d\n", err);
>>> +#endif
>>> +   }
>>> +
>>> +   fpga_fsinfo.dev_part = (char *)get_cff_devpart(gd-
 fdt_blob,
>>> +    &
>>> len);
>>> +
>>> +   fpga_fsinfo.filename = (char
>>> *)get_cff_filename(gd->fdt_blob,
>>> +    &
>>> len,
>>> +   PE
>>> RIPH_RBF);
>>> +
>>> +   fpga_fsinfo.interface = "mmc";
>>> +
>>> +   fpga_fsinfo.fstype = FS_TYPE_FAT;
>>> +   } else {
>>> +   printf("Invalid boot device!\n");
>>> +   return;
>>> +   }
>>> +
>>> +   /* Program peripheral RBF */
>>> +   if (fpga_fsinfo.filename && fpga_fsinfo.dev_part && (len >
>>> 0))
>>> +   rval = fpga_fsload(0, buffer, BSIZE,
>>> _fsinfo);
>>> +
>>> +   if (rval > 0) {
>>> +   config_pins(gd->fdt_blob, "shared");
>>> +
>>> +   ddr_calibration_sequence();
>>> +   }
>>>  }
>>>  
>>>  void board_init_f(ulong dummy)
>>> diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
>>> index b26..159443f 100644
>>> --- a/common/spl/spl_mmc.c
>>> +++ b/common/spl/spl_mmc.c
>>> @@ -113,7 +113,7 @@ static int spl_mmc_get_device_index(u32
>>> boot_device)
>>>     return -ENODEV;
>>>  }
>>>  
>>> -static int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)
>>> +int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)
>>>  {
>>>  #if CONFIG_IS_ENABLED(DM_MMC)
>>>     struct udevice *dev;
>>> diff --git a/configs/socfpga_arria10_defconfig
>>> b/configs/socfpga_arria10_defconfig
>>> index 4c73d73..2ff9801 100644
>>> --- a/configs/socfpga_arria10_defconfig
>>> +++ b/configs/socfpga_arria10_defconfig
>>> @@ -2,33 +2,76 @@ CONFIG_ARM=y
>>>  CONFIG_ARCH_SOCFPGA=y
>>>  CONFIG_SYS_MALLOC_F_LEN=0x2000
>>>  CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
>>> +CONFIG_SPL_STACK_R_ADDR=0x0080
>>>  CONFIG_IDENT_STRING="socfpga_arria10"
>>>  CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
>>> -CONFIG_USE_BOOTARGS=y
>>> -CONFIG_BOOTARGS="console=ttyS0,115200"
>>>  CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb"
>>> +CONFIG_FIT=y
>>> +CONFIG_SYS_CONSOLE_IS_IN_ENV=y
>>> 

Re: [U-Boot] [PATCH v2 11/19] arm: socfpga: Add DRAM bank size initialization function

[Marek Vasut]

On 09/26/2017 10:20 AM, Chee, Tien Fong wrote:
> On Isn, 2017-09-25 at 11:15 +0200, Marek Vasut wrote:
>> On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
>>>
>>> From: Tien Fong Chee 
>>>
>>> Add function for both multiple DRAM bank and single DRAM bank size
>>> initialization. This common functionality could be used by every
>>> single
>>> SOCFPGA board.
>>>
>>> Signed-off-by: Tien Fong Chee 
>> I'd like TB on Gen5.
>>
> What is TB?

Tested-by

>>>
>>> ---
>>>  arch/arm/mach-socfpga/board.c| 7 +++
>>>  include/configs/socfpga_common.h | 1 +
>>>  2 files changed, 8 insertions(+)
>>>
>>> diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-
>>> socfpga/board.c
>>> index a41d089..965f9dc 100644
>>> --- a/arch/arm/mach-socfpga/board.c
>>> +++ b/arch/arm/mach-socfpga/board.c
>>> @@ -29,6 +29,13 @@ int board_init(void)
>>>     return 0;
>>>  }
>>>  
>>> +int dram_init_banksize(void)
>>> +{
>>> +   fdtdec_setup_memory_banksize();
>>> +
>>> +   return 0;
>>> +}
>>> +
>>>  #ifdef CONFIG_USB_GADGET
>>>  struct dwc2_plat_otg_data socfpga_otg_data = {
>>>     .usb_gusbcfg= 0x1417,
>>> diff --git a/include/configs/socfpga_common.h
>>> b/include/configs/socfpga_common.h
>>> index eadce2d..7549ee8 100644
>>> --- a/include/configs/socfpga_common.h
>>> +++ b/include/configs/socfpga_common.h
>>> @@ -47,6 +47,7 @@
>>>     (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
>>>  
>>>  #define CONFIG_SYS_SDRAM_BASE  PHYS_SDRAM_1
>>> +#define CONFIG_SYS_SDRAM_SIZE  PHYS_SDRAM_1_SIZE
>>>  #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
>>>  #define CONFIG_SYS_TEXT_BASE   0x0840
>>>  #else
>>>


-- 
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Re: [U-Boot] [PATCH v2 10/19] arm: socfpga: Rename the gen5 sdram driver to more specific name

[Marek Vasut]

On 09/26/2017 10:23 AM, Chee, Tien Fong wrote:
> On Isn, 2017-09-25 at 11:15 +0200, Marek Vasut wrote:
>> On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
>>>
>>> From: Tien Fong Chee 
>>>
>>> Current sdram driver is only applied to gen5 device, hence it is
>>> better
>>> to rename sdram driver to more specific name which is related to
>>> gen5
>>> device.
>>>
>>> Signed-off-by: Tien Fong Chee 
>>> ---
>>>  arch/arm/mach-socfpga/include/mach/sdram.h | 434 +--
>>> --
>>>  .../include/mach/{sdram.h => sdram_gen5.h} |   6 +-
>>>  drivers/ddr/altera/Makefile|   2 +-
>>>  drivers/ddr/altera/{sdram.c => sdram_gen5.c}   |   0
>>>  4 files changed, 8 insertions(+), 434 deletions(-)
>>>  copy arch/arm/mach-socfpga/include/mach/{sdram.h => sdram_gen5.h}
>>> (99%)
>>>  rename drivers/ddr/altera/{sdram.c => sdram_gen5.c} (100%)
>>>
>>> diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h
>>> b/arch/arm/mach-socfpga/include/mach/sdram.h
>>> index b11228f..4a9754e 100644
>>> --- a/arch/arm/mach-socfpga/include/mach/sdram.h
>>> +++ b/arch/arm/mach-socfpga/include/mach/sdram.h
>>> @@ -1,5 +1,5 @@
>>>  /*
>>> - * Copyright Altera Corporation (C) 2014-2015
>>> + * Copyright (C) 2017 Intel Corporation 
>> Retain the old copyright ?
>>
> Okay.
>>>
>>>   *
>>>   * SPDX-License-Identifier:GPL-2.0+
>>>   */
>>> @@ -8,435 +8,9 @@
>>>  
>>>  #ifndef __ASSEMBLY__
>> What's with this massive deletion here ?
>>
> Move to sdram_gen5.h . This header should contain common stuff.

Then where did the + part go ?

>>>
>>> -unsigned long sdram_calculate_size(void);
>>> -int sdram_mmr_init_full(unsigned int sdr_phy_reg);
>>> -int sdram_calibration_full(void);
>>> -
>>> -const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
>>> -
>>> -void socfpga_get_seq_ac_init(const u32 **init, unsigned int
>>> *nelem);
>>> -void socfpga_get_seq_inst_init(const u32 **init, unsigned int
>>> *nelem);
>>> -const struct socfpga_sdram_rw_mgr_config
>>> *socfpga_get_sdram_rwmgr_config(void);
>> [...]


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Re: [U-Boot] [PATCH v2 12/19] arm: socfpga: Add DDR driver for Arria 10

[Marek Vasut]

On 09/26/2017 10:20 AM, Chee, Tien Fong wrote:
> On Isn, 2017-09-25 at 11:19 +0200, Marek Vasut wrote:
>> On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
>>>
>>> From: Tien Fong Chee 
>>>
>>> Add DDR driver suppport for Arria 10.
>>>
>>> Signed-off-by: Tien Fong Chee 
>>> ---
>>>  arch/arm/mach-socfpga/include/mach/sdram.h |   2 +
>>>  arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 103 ++-
>>>  drivers/ddr/altera/sdram_arria10.c | 735
>>> +
>>>  3 files changed, 839 insertions(+), 1 deletion(-)
>>>  create mode 100644 drivers/ddr/altera/sdram_arria10.c
>>>
>>> diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h
>>> b/arch/arm/mach-socfpga/include/mach/sdram.h
>>> index 4a9754e..b833fc2 100644
>>> --- a/arch/arm/mach-socfpga/include/mach/sdram.h
>>> +++ b/arch/arm/mach-socfpga/include/mach/sdram.h
>>> @@ -10,6 +10,8 @@
>>>  
>>>  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>>  #include 
>>> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>>> +#include 
>>>  #endif
>>>  
>>>  #endif
>>> diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
>>> b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
>>> index 1d7b7c1..7af9431 100644
>>> --- a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
>>> +++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
>>> @@ -1,5 +1,5 @@
>>>  /*
>>> - * Copyright (C) 2015-2017 Intel Corporation 
>>> + * Copyright (C) 2017 Intel Corporation 
>>>   *
>>>   * SPDX-License-Identifier:GPL-2.0
>>>   */
>>> @@ -8,6 +8,7 @@
>>>  #define _SOCFPGA_SDRAM_ARRIA10_H_
>>>  
>>>  #ifndef __ASSEMBLY__
>>> +int ddr_calibration_sequence(void);
>>>  
>>>  struct socfpga_ecc_hmc {
>>>     u32 ip_rev_id;
>>> @@ -204,6 +205,106 @@ struct socfpga_io48_mmr {
>>>     u32 niosreserve1;
>>>     u32 niosreserve2;
>>>  };
>>> +
>>> +union dramaddrw_reg {
>>> +   struct {
>>> +   u32 cfg_col_addr_width:5;
>>> +   u32 cfg_row_addr_width:5;
>>> +   u32 cfg_bank_addr_width:4;
>>> +   u32 cfg_bank_group_addr_width:2;
>>> +   u32 cfg_cs_addr_width:3;
>>> +   u32 reserved:13;
>>> +   };
>> Use regular macros for bitfields, not this crap.
>>
> Why regular macros is prefered? Above implementation improve
> readability, simplify the implementation and saving memory.

Because that's how U-Boot does it (and the above afair breaks on
different endianness).

>>>
>>> +   u32 word;
>>> +};
>>> +
>>> +union ctrlcfg0_reg {
>>> +   struct {
>>> +   u32 cfg_mem_type:4;
>>> +   u32 cfg_dimm_type:3;
>>> +   u32 cfg_ac_pos:2;
>>> +   u32 cfg_ctrl_burst_len:5;
>>> +   u32 reserved:18;  /* Other fields unused */
>>> +   };
>>> +   u32 word;
>>> +};
>> [...]

[...]

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Re: [U-Boot] [PATCH v2 16/19] arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10

[Marek Vasut]

On 09/26/2017 06:42 AM, Chee, Tien Fong wrote:
> On Isn, 2017-09-25 at 11:23 +0200, Marek Vasut wrote:
>> On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
>>>
>>> From: Tien Fong Chee 
>>>
>>> Enhance preloader header with both additional program length and
>>> program
>>> entry offset attributes, which offset is relative to the start of
>>> program
>>> header.
>>>
>>> Signed-off-by: Tien Fong Chee 
>>> ---
>>>  arch/arm/mach-socfpga/include/mach/boot0.h | 11 +--
>>>  1 file changed, 9 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h
>>> b/arch/arm/mach-socfpga/include/mach/boot0.h
>>> index 22d9e7f..33c9368 100644
>>> --- a/arch/arm/mach-socfpga/include/mach/boot0.h
>>> +++ b/arch/arm/mach-socfpga/include/mach/boot0.h
>>> @@ -11,8 +11,15 @@
>>>     .balignl 64,0xf33db33f;
>>>  
>>>     .word   0x1337c0d3; /* SoCFPGA preloader
>>> validation word */
>>> -   .word   0xc01df00d; /* Version, flags, length
>>> */
>>> -   .word   0xcafec0d3; /* Checksum, zero-pad */
>>> +   .word   0xc01df00d; /* Header
>>> length(2B),flags(1B),version(1B) */
>>> +#ifndef CONFIG_TARGET_SOCFPGA_GEN5
>>> +   .word   0xfeedface; /* Program length(4B) */
>> Keep this indent intact, then it won't generate these crappy -
>> entries.
>>
> Are you saying to keep the comment indent intact, and allign with 1st
> comment  /* SoCFPGA preloader validation word */ ?

Just look at the diff and make sure that it only changes the relevant
parts, not extras due to indent changes.

>>>
>>> +   .word   0xf00dcafe; /*
>>> +    * Program entry offset(4B),relative
>>> to
>>> +    * the start of program header
>>> +    */
>>> +#endif
>>> +   .word   0xcafec0d3; /* Simple
>>> checksum(2B),spare offset(2B) */
>>>     nop;
>>>  
>>>     b reset;/* SoCFPGA jumps here */
>>>


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Re: [U-Boot] [PATCH v2 15/19] arm: socfpga: Add support to memory allocation in SPL

[Marek Vasut]

On 09/26/2017 07:06 AM, Chee, Tien Fong wrote:
> On Isn, 2017-09-25 at 11:21 +0200, Marek Vasut wrote:
>> On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
>>>
>>> From: Tien Fong Chee 
>>>
>>> Add support to memory allocation in SPL for preparation to enable
>>> FAT
>>> in SPL. Memory allocation is needed by FAT to work properly.
>>>
>>> Signed-off-by: Tien Fong Chee 
>> Gen 5 does have malloc support in SPL, so what's the deal here ?
>>
> For FAT to work properly in Arria 10 SPL, SPL malloc need to be
> enabled,

It is already enabled on Gen 5

> and the min of SPL malloc size is 0x2000.

Where did you find about this minimum ? That can be configured ...

> FAT needed in Arria
> 10 SPL, because u-boot.img is stored in FAT partition.

It can also be stored on ext partition (which is preferred, patent-wise)

>>>
>>> ---
>>>  include/configs/socfpga_common.h | 23 ++-
>>>  1 file changed, 22 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/include/configs/socfpga_common.h
>>> b/include/configs/socfpga_common.h
>>> index 7549ee8..9b6719e 100644
>>> --- a/include/configs/socfpga_common.h
>>> +++ b/include/configs/socfpga_common.h
>>> @@ -280,17 +280,34 @@ unsigned int
>>> cm_get_qspi_controller_clk_hz(void);
>>>  /*
>>>   * SPL
>>>   *
>>> - * SRAM Memory layout:
>>> + * SRAM Memory layout for gen 5:
>>>   *
>>>   * 0x_ .. Start of SRAM
>>>   * 0x_ .. Top of stack (grows down)
>>>   * 0x_ .. Malloc area
>>>   * 0x_ .. Global Data
>>>   * 0x_FF00 .. End of SRAM
>>> + *
>>> + * SRAM Memory layout for Arria 10:
>>> + * 0xFFE0_ .. Start of SRAM (bottom)
>>> + * 0xFFEx_ .. Top of stack (grows down to bottom)
>>> + * 0xFFEy_ .. Malloc area (grows up to top)
>>> + * 0xFFEz_ .. Global Data
>>> + * 0xFFE3_ .. End of SRAM (top)
>>>   */
>>>  #define CONFIG_SPL_FRAMEWORK
>>>  #define CONFIG_SPL_TEXT_BASE   CONFIG_SYS_INIT_RAM_AD
>>> DR
>>>  #define CONFIG_SPL_MAX_SIZECONFIG_SYS_INIT_RAM_SIZ
>>> E
>>> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>>> +/* SPL memory allocation configuration, it is required by FAT
>>> feature */
>>> +#ifndef CONFIG_SYS_SPL_MALLOC_START
>>> +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x2000
>>> +#define CONFIG_SYS_SPL_MALLOC_START(CONFIG_SYS_INIT_RAM_SI
>>> ZE - \
>>> +    GENERATED_GBL_DATA_SIZE -
>>> \
>>> +    CONFIG_SYS_SPL_MALLOC_SIZ
>>> E + \
>>> +    CONFIG_SYS_INIT_RAM_ADDR)
>>> +#endif
>>> +#endif
>>>  
>>>  /* SPL SDMMC boot support */
>>>  #ifdef CONFIG_SPL_MMC_SUPPORT
>>> @@ -320,7 +337,11 @@ unsigned int
>>> cm_get_qspi_controller_clk_hz(void);
>>>  /*
>>>   * Stack setup
>>>   */
>>> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>>  #define CONFIG_SPL_STACK   CONFIG_SYS_INIT_SP_ADDR
>>> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>>> +#define CONFIG_SPL_STACK   (CONFIG_SYS_SPL_MALLOC_STA
>>> RT - 1)
>>> +#endif
>>>  
>>>  /* Extra Environment */
>>>  #ifndef CONFIG_SPL_BUILD
>>>


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Re: [U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for programing FPGA from flash

[Marek Vasut]

On 09/26/2017 10:30 AM, Chee, Tien Fong wrote:
> On Isn, 2017-09-25 at 11:14 +0200, Marek Vasut wrote:
>> On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
>>>
>>> From: Tien Fong Chee 
>>>
>>> These drivers handle FPGA program operation from flash loading
>>> RBF to memory and then to program FPGA.
>>>
>>> Signed-off-by: Tien Fong Chee 
>> Did you run checkpatch on this before submitting ? I presume no ...
>>
> Yeah, i run checkpatch for all patches. What's the issue here?

It should definitely indicate problem with ie. yoda-notation
+if (0 == flashinfo->remaining) {
and indent ...

>>>
>>> ---
>>>  .../include/mach/fpga_manager_arria10.h|  27 ++
>>>  drivers/fpga/socfpga_arria10.c | 391
>>> -
>>>  include/altera.h   |   6 +
>>>  include/configs/socfpga_common.h   |   4 +
>>>  4 files changed, 425 insertions(+), 3 deletions(-)
>> [...]
>>
>>>
>>> @@ -112,13 +122,14 @@ static int
>>> wait_for_nconfig_pin_and_nstatus_pin(void)
>>>     unsigned long mask =
>>> ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
>>>     ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATU
>>> S_PIN_SET_MSK;
>>>  
>>> -   /* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop
>>> until de-asserted,
>>> -    * timeout at 1000ms
>>> +   /*
>>> +    * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop
>>> until
>>> +    * de-asserted, timeout at 1000ms
>>>      */
>>>     return wait_for_bit(__func__,
>>>     _manager_base->imgcfg_stat,
>>>     mask,
>>> -   false, FPGA_TIMEOUT_MSEC, false);
>>> +   true, FPGA_TIMEOUT_MSEC, false);
>>>  }
>> Seems more like a fix, split this out.
>>
> Okay.
>>>
>>>  static int wait_for_f2s_nstatus_pin(unsigned long value)
>>> @@ -469,6 +480,7 @@ int socfpga_load(Altera_desc *desc, const void
>>> *rbf_data, size_t rbf_size)
>>>  
>>>     /* Initialize the FPGA Manager */
>>>     status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
>>> +
>>>     if (status)
>>>     return status;
>>>  
>>> @@ -477,3 +489,376 @@ int socfpga_load(Altera_desc *desc, const
>>> void *rbf_data, size_t rbf_size)
>>>  
>>>     return fpgamgr_program_finish();
>>>  }
>>> +
>>> +#if defined(CONFIG_CMD_FPGA_LOADFS)
>>> +const char *get_cff_filename(const void *fdt, int *len, u32 core)
>>> +{
>>> +   const char *cff_filename = NULL;
>>> +   const char *cell;
>>> +   int nodeoffset;
>>> +   nodeoffset = fdtdec_next_compatible(fdt, 0,
>>> +    COMPAT_ALTERA_SOCFPGA_FPGA0);
>>> +
>>> +   if (nodeoffset >= 0) {
>>> +   if (core)
>>> +   cell = fdt_getprop(fdt,
>>> +   nodeoffset,
>>> +   "bitstream_core",
>>> +   len);
>>> +   else
>>> +   cell = fdt_getprop(fdt, nodeoffset,
>>> "bitstream_periph",
>>> +    len);
>>> +
>>> +   if (cell)
>>> +   cff_filename = cell;
>>> +   }
>>> +
>>> +   return cff_filename;
>>> +}
>>> +
>>> +const char *get_cff_devpart(const void *fdt, int *len)
>>> +{
>>> +   const char *cff_devpart = NULL;
>>> +   const char *cell;
>>> +   int nodeoffset;
>>> +   nodeoffset = fdtdec_next_compatible(fdt, 0,
>>> +    COMPAT_ALTERA_SOCFPGA_FPGA0);
>>> +
>>> +   cell = fdt_getprop(fdt, nodeoffset, "bitstream_devpart",
>>> len);
>>> +
>>> +   if (cell)
>>> +   cff_devpart = cell;
>>> +
>>> +   return cff_devpart;
>>> +}
>> Take a look at splash*.c , I believe that can be reworked into
>> generic
>> firmware loader , which you could then use here.

This is important here, I don't want yet another ad-hoc loader ...

>> [...]
>>
>>>
>>> diff --git a/include/configs/socfpga_common.h
>>> b/include/configs/socfpga_common.h
>>> index 9897e11..eadce2d 100644
>>> --- a/include/configs/socfpga_common.h
>>> +++ b/include/configs/socfpga_common.h
>>> @@ -27,7 +27,11 @@
>>>   */
>>>  #define CONFIG_NR_DRAM_BANKS   1
>>>  #define PHYS_SDRAM_1   0x0
>>> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>>  #define CONFIG_SYS_MALLOC_LEN  (64 * 1024 * 1024)
>>> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>>> +#define CONFIG_SYS_MALLOC_LEN  (128 * 1024 * 1024)
>>> +#endif
>> You definitely don't need 128 MiB of malloc area.
>>
> Okay, i will try out with smaller size.

Why do you need such massive area ? It's not a matter of "try out", you
should know why this change was needed for your use-case.

>>>
>>>  #define CONFIG_SYS_MEMTEST_START   PHYS_SDRAM_1
>>>  #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
>>>  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>>


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