Hi Bin,
On 6/5/2019 1:05 PM, Bin Meng wrote:
> Hi Alex,
>
> On Tue, Jun 4, 2019 at 8:46 PM Alex Marginean wrote:
>>
>> This test is built on top of the existing swap_case driver. It adds EA
>> capability structure support to swap_case and uses that to map BARs.
>> BAR1 works as it used to,
Hi Bin,
On 6/10/2019 6:42 AM, Bin Meng wrote:
> Hi Alex,
>
> On Sat, Jun 8, 2019 at 12:12 AM Alex Marginean
> wrote:
>>
>> Adds a driver for NXP ENETC ethernet controller currently integrated in
>> LS1028a. ENETC is a fairly straight-forward BD ring device and interfaces
>> are presented as
Hi Ken,
On 6/11/2019 12:44 PM, Ken Ma wrote:
> Hi Alex
>
> Thanks a lot for your information!
>
> I think our patches have no essential difference.
> The 2 patches have only small implementation difference:
> In my patch, mii bus ops functions(read/write/reset...) need to be
> implemented while
Hi Bin,
On 6/11/2019 11:18 AM, Alexandru Marginean wrote:
> Hi Bin,
>
> On 6/10/2019 6:42 AM, Bin Meng wrote:
>> Hi Alex,
>>
>> On Sat, Jun 8, 2019 at 12:12 AM Alex Marginean
>> wrote:
>>>
>>> Adds a driver for NXP ENETC ethernet con
More email trouble at my end, please ignore this.
I'll resend as v3 from the nxp account..
Alex
On 6/18/2019 5:47 PM, Alex Marginean wrote:
> Adds a short bindings document describing the expected structure of a MDIO
> MUX dts node. This is based on Linux binding and the example is in fact
>
This 2nd register is used by the follow-up MDIO MUX test.
Signed-off-by: Alex Marginean
---
Changes in v2:
- no change
Changes in v3:
- no change, just fighting with the email server
drivers/net/mdio_sandbox.c | 16 +---
test/dm/mdio.c | 3 +++
2 files
Adds a test using a makeshift MDIO MUX. The test is based on the existing
MDIO test. It uses the last emulated PHY register to verify MUX selection.
Signed-off-by: Alex Marginean
---
Changes in v2:
- no change
Changes in v3:
- no change, just fighting with the email server
Adds a class for MDIO MUXes, which control access to a series of
downstream child MDIOs.
MDIO MUX drivers are required to implement a select function used to switch
between child buses.
MUX children are registered as MDIO buses and they can be used just like
regular MDIOs.
Signed-off-by: Alex
Adds a short bindings document describing the expected structure of a MDIO
MUX dts node. This is based on Linux binding and the example is in fact
copied from there.
Signed-off-by: Alex Marginean
---
Changes in v2:
- no change
Changes in v3:
- no change, just fighting with the
adds AQR112 and AQR412 to the list of supported PHYs using existing AQR
code.
Signed-off-by: Alex Marginean
Reviewed-By: Ramon Fried
---
Changes in v2:
- Numerical ordering of structure definition and function calls
Changes in v3:
- Resent, v2 was mangled up pretty bad by
adds AQR112 and AQR412 to the list of supported PHYs using existing AQR
code.
Signed-off-by: Alex Marginean
---
Changes in v2:
- Numerical ordering of structure definition and function calls
drivers/net/phy/aquantia.c | 28
1 file changed, 28 insertions(+)
Current code fails to probe some C45 PHYs that also respond to C22 reads.
This is the case for PHYs like Aquantia AQR112, Marvell 88X2242 (as
previously posted on the u-boot list).
If the PHY ID reads all 0s just ignore it and try the next devad.
Signed-off-by: Alex Marginean
---
adds AQR112 and AQR412 to the list of supported PHYs using existing AQR
code.
Signed-off-by: Alex Marginean
---
drivers/net/phy/aquantia.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
index
It looks like the first patch didn't make it through, blocked by google.
Sorry about that I'll try to resend the series.
Does anyone else have issues with gmail blocking patches and emails?
Any suggestions on how to get them through safely?
Sorry for the spam.
Alex
On 6/18/2019 12:22 PM, Alex
On 7/13/2019 7:02 AM, Bin Meng wrote:
> Hi Alex,
>
> On Fri, Jul 12, 2019 at 10:21 PM Alex Marginean
> wrote:
>>
>> This driver is used for MDIO muxes driven over I2C. This is currently
>> used on Freescale LS1028A QDS board, on which the physical MDIO MUX is
>> controlled by an on-board FPGA
Hi Michael,
On 11/14/2019 6:41 PM, Michael Walle wrote:
Hi,
sorry for being so late..
We're going to try to get this binding accepted in Linux too.
shouldn't we try to get it accepted to linux first? To avoid any
incompatibilities?
I can propagate any changes kernel crows asks us to do
On 11/14/2019 7:19 PM, Alexandru Marginean wrote:
Hi Michael,
On 11/14/2019 6:41 PM, Michael Walle wrote:
Hi,
sorry for being so late..
We're going to try to get this binding accepted in Linux too.
shouldn't we try to get it accepted to linux first? To avoid any
incompatibilities?
I can
Hi Bin,
On 11/15/2019 3:32 PM, Bin Meng wrote:
Hi Alex,
On Fri, Nov 15, 2019 at 8:57 PM Alex Marginean
wrote:
The driver sets up the switch during probe making external and internal ports
available to use. It does not support direct I/O through these switch ports
in this version, instead
Hi JJ,
On 11/5/2019 12:50 PM, Jean-Jacques Hiblot wrote:
This adds a driver for mmio-based syscon multiplexers controlled by
bitfields in a syscon register range.
This is heavily based on the linux mmio-mux driver.
Signed-off-by: Jean-Jacques Hiblot
---
Changes in v2: None
On 11/20/2019 10:51 AM, Grygorii Strashko wrote:
On 19/11/2019 20:58, Grygorii Strashko wrote:
On 19/11/2019 01:31, Alexandru Marginean wrote:
On 11/18/2019 8:11 PM, Grygorii Strashko wrote:
On 14/11/2019 17:04, Alex Marginean wrote:
Adds an optional mdio-handle property which
On 12/3/2019 11:46 AM, Alex Marginean wrote:
> The arch_misc_init function is emtpy on LS2 SoCs/boards, remove it.
s/emtpy/empty/
>
> Signed-off-by: Alex Marginean
> ---
> arch/arm/Kconfig| 5 -
> board/freescale/ls2080a/ls2080a.c | 7 ---
>
Hi,
does anyone have any strong feelings either way about the idea of
driving Eth PHYs as udevices?
I'm looking for a solution for a few problems:
- There are a few Eth switches that are accessed over MDIO and
could/should be driven as DSA switches instead of PHYs. This requires
that MDIO
On 12/10/2019 3:54 PM, Vladimir Oltean wrote:
Hi Alex,
On Tue, 10 Dec 2019 at 16:21, Alex Marginean
wrote:
Passes on the primary address used by u-boot to Linux. The code does a DT
fix-up for ENETC PFs and sets the primary MAC address in IERB. The address
in IERB is restored on ENETC PCI
On 12/17/2019 10:41 AM, Vladimir Oltean wrote:
On Tue, 17 Dec 2019 at 09:18, Alexandru Marginean
wrote:
On 12/15/2019 2:08 PM, Vladimir Oltean wrote:
On Tue, 3 Dec 2019 at 17:32, Alex Marginean wrote:
+/**
+ * This function deals with additional devices around the switch as these
should
On 12/15/2019 1:53 PM, Vladimir Oltean wrote:
Hi Alex,
On Tue, 3 Dec 2019 at 18:18, Alex Marginean wrote:
+static int felix_port_enable(struct udevice *dev, int port,
+struct phy_device *phy)
+{
+ struct felix_priv *priv = dev_get_priv(dev);
+ void
On 12/15/2019 3:16 PM, Vladimir Oltean wrote:
On Sun, 15 Dec 2019 at 14:53, Vladimir Oltean wrote:
Hi Alex,
On Tue, 3 Dec 2019 at 18:18, Alex Marginean wrote:
+static int felix_port_enable(struct udevice *dev, int port,
+struct phy_device *phy)
+{
+ struct
On 12/15/2019 2:08 PM, Vladimir Oltean wrote:
On Tue, 3 Dec 2019 at 17:32, Alex Marginean wrote:
+/**
+ * This function deals with additional devices around the switch as these
should
+ * have been bound to drivers by now.
+ * TODO: pick up references to other switch devices here, if we're
Hi Vladimir,
On 12/15/2019 1:44 PM, Vladimir Oltean wrote:
Hi Alex,
On Tue, 3 Dec 2019 at 17:32, Alex Marginean wrote:
DSA stands for Distributed Switch Architecture and it covers switches that
are connected to the CPU through an Ethernet link and generally use frame
tags to pass
On 12/10/2019 11:47 PM, Michael Walle wrote:
Am 2019-12-10 15:55, schrieb Alex Marginean:
Passes on the primary address used by u-boot to Linux. The code does
a DT
fix-up for ENETC PFs and sets the primary MAC address in IERB. The
address
in IERB is restored on ENETC PCI functions at FLR.
On 12/11/2019 2:16 PM, Michael Walle wrote:
Hi Vladimir,
Am 2019-12-11 13:46, schrieb Vladimir Oltean:
Hi Michael,
On Wed, 11 Dec 2019 at 00:48, Michael Walle wrote:
Am 2019-12-10 15:55, schrieb Alex Marginean:
> Passes on the primary address used by u-boot to Linux. The code
does a
>
On 12/12/2019 1:12 PM, Michael Walle wrote:
Hi Alex,
Am 2019-12-11 22:01, schrieb Alexandru Marginean:
Hi Michael,
On 12/11/2019 6:03 PM, Michael Walle wrote:
Hi Alex,
Am 2019-12-11 16:37, schrieb Alexandru Marginean:
On 12/11/2019 2:16 PM, Michael Walle wrote:
Hi Vladimir,
Am 2019-12-11
Hi Michael,
On 12/11/2019 6:03 PM, Michael Walle wrote:
Hi Alex,
Am 2019-12-11 16:37, schrieb Alexandru Marginean:
On 12/11/2019 2:16 PM, Michael Walle wrote:
Hi Vladimir,
Am 2019-12-11 13:46, schrieb Vladimir Oltean:
Hi Michael,
On Wed, 11 Dec 2019 at 00:48, Michael Walle wrote:
Am
Hi Claudius,
On 12/3/2019 1:28 PM, Claudius Heine wrote:
On 03/12/2019 11.25, Claudius Heine wrote:
On 03/12/2019 10.05, Claudius Heine wrote:
On 03/12/2019 08.44, Claudius Heine wrote:
Hi everyone,
because we are moving the mailing list to a different server, we have to
take it down for
On 10/26/2019 2:39 AM, Michael Walle wrote:
The saved ofnode is used by some PHY drivers to access the device tree
node of the PHY.
Signed-off-by: Michael Walle
---
drivers/net/fsl_enetc.c | 1 +
1 file changed, 1 insertion(+)
Reviewed-by: Alex Marginean
On 10/26/2019 2:39 AM, Michael Walle wrote:
Add the missing RGMII PHY modes in which case the MAC has configure its
RGMII settings. The only difference between these modes is the RX and
TX delay configuration. A user might choose any RGMII mode in the device
tree.
Signed-off-by: Michael Walle
On 11/18/2019 8:11 PM, Grygorii Strashko wrote:
On 14/11/2019 17:04, Alex Marginean wrote:
Adds an optional mdio-handle property which identifies a MDIO bus
which can
be scanned to find the relevant PHY. The property is ignored if
phy-handle
is also present.
Signed-off-by: Alex Marginean
Hi Michael,
On 11/27/2019 3:33 PM, Michael Walle wrote:
Hi Alex,
Am 2019-11-27 14:57, schrieb Alex Marginean:
Hardware comes out of reset with implicit values, but these are outside
the accepted range for Layerscape gen 3 chassis spec used on LS1028A.
Allocate different IDs and fix up Linux
Hi Pramod,
On 11/25/2019 11:42 AM, Pramod Kumar wrote:
LS1044A, LS1048A are LS1088A personalities, which support only one
1x 10GE port.
There's probably a mix-up, and unfortunately we have an issue in the
LS1088A reference manual available on the website too.
- LS1088A is documented as 2x
Hi Joe,
On 11/30/2019 1:56 AM, Joe Hershberger wrote:
Hi Alex,
On Mon, Nov 25, 2019 at 9:54 AM Alex Marginean
wrote:
DSA stands for Distributed Switch Architecture and it covers switches that
are connected to the CPU through an Ethernet link and generally use frame
tags to pass information
Hi Michael,
On 10/22/2019 1:03 AM, Michael Walle wrote:
device_probe() may fail in which case the seq_id will be -1. Don't
display these devices during startup. While this is only a cosmetic
change, the return value of eth_initialize() will also change to the
actual number of available
On 12/1/2019 5:45 PM, Michael Walle wrote:
PCI devices may be disabled in the device tree. Devices which are probed
by the device tree handle the "status" property and are skipped if
disabled. Devices which are probed by the PCI enumeration don't check
that property. Fix it.
Signed-off-by:
On 12/1/2019 5:17 AM, Florian Fainelli wrote:
On 11/30/2019 6:21 PM, Alexandru Marginean wrote:
Hi Joe,
On 11/30/2019 1:56 AM, Joe Hershberger wrote:
Hi Alex,
On Mon, Nov 25, 2019 at 9:54 AM Alex Marginean
wrote:
DSA stands for Distributed Switch Architecture and it covers switches
On 12/1/2019 5:43 PM, Michael Walle wrote:
Am 2019-12-01 01:55, schrieb Alexandru Marginean:
Hi Michael,
On 10/22/2019 1:03 AM, Michael Walle wrote:
device_probe() may fail in which case the seq_id will be -1. Don't
display these devices during startup. While this is only a cosmetic
change
Hi Michael,
On 11/24/2019 1:11 AM, Michael Walle wrote:
> Am 2019-11-22 02:36, schrieb Alex Marginean:
>> The definition follows the DSA binding in kernel and describes the
>> switch,
>> its ports and PHYs.
>> ENETC PF6 is the 2nd Eth controller linked to the switch on LS1028, it is
>
>
On 11/21/2019 1:30 PM, Grygorii Strashko wrote:
Some thought, which i think might help.
- u-boot allows phy node not to have "reg" property.
- phy_connect() will return first PHY discovered on the MDIO bus if
addr<=0
So, if MDIO assignment per ethernet interface/slot is fixed DT can
look
On 12/18/2019 10:45 PM, Michael Walle wrote:
Am 2019-12-18 21:00, schrieb Alexandru Marginean:
Hi Michael,
On 12/18/2019 5:42 PM, Michael Walle wrote:
If there are aliases for an uclass, set the base for the "dynamically"
allocated numbers next to the highest alias.
P
Hi Michael,
On 12/18/2019 5:42 PM, Michael Walle wrote:
If there are aliases for an uclass, set the base for the "dynamically"
allocated numbers next to the highest alias.
Please note, that this might lead to holes in the sequences, depending
on the device tree. For example if there is only an
Hi Michael,
On 12/18/2019 5:47 PM, Michael Walle wrote:
Intead of setting the MAC address in enetc_start() use the proper
write_hwaddr(). U-Boot takes care of the random MAC address, too. Also,
this will correctly handle ethNmacskip etc.
Signed-off-by: Michael Walle
---
On 12/19/2019 7:30 AM, Priyanka Jain wrote:
-Original Message-
From: U-Boot On Behalf Of Marek Vasut
Sent: Wednesday, December 18, 2019 9:47 PM
To: joe.hershber...@ni.com
Cc: u-boot@lists.denx.de; Tom Rini ; Joseph
Hershberger
Subject: Re: [U-Boot] [PATCH] net/phy: Fix phy_connect()
On 3/13/2020 12:04 PM, Vladimir Oltean wrote:
From: Vladimir Oltean
The pci-host-ecam-generic code assumes that the ECAM is the first PCI
bus in the system to be probed. Therefore, the system-wide bus number
allocated by U-Boot in sequence for it is going to be zero, which
corresponds to the
On 3/13/2020 3:33 PM, Vladimir Oltean wrote:
On Tue, 3 Dec 2019 at 17:23, Alex Marginean wrote:
The switch driver for LS1028A Ethernet switch is now compiled in for
both LS1028A boards.
Signed-off-by: Alex Marginean
---
configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 3 ++-
On 2/8/2020 2:19 PM, Vladimir Oltean wrote:
On Tue, 3 Dec 2019 at 18:18, Alex Marginean wrote:
DSA stands for Distributed Switch Architecture and it is a subsystem
introduced in the Linux kernel to support switches that:
- have an Ethernet link up to the CPU
- use some form of tagging to
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