/riscv/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Rick Chen
nly a few
> places need an additional header instead.
>
> Signed-off-by: Tom Rini
> ---
> Cc: Rick Chen
> Cc: Leo
> ---
Reviewed-by: Rick Chen
> configs/sifive_unmatched_defconfig | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Rick Chen
> Hi Rick,
>
> On Wed, 19 Apr 2023 at 00:56, Rick Chen wrote:
> >
> > Hi Simon,
> >
> > > Hi Rick,
> > >
> > > On Mon, 10 Apr 2023 at 01:26, Rick Chen wrote:
> > > >
> > > > Allow U-Boot to load 32 or 64 bits R
; Add include skeleton.
> ---
> arch/riscv/include/asm/acpi_table.h | 11 +++
> 1 file changed, 11 insertions(+)
Reviewed-by: Rick Chen
> ---
> configs/sifive_unmatched_defconfig | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Rick Chen
e/configs/qemu-riscv.h| 2 +-
> 4 files changed, 16 insertions(+), 1 deletion(-)
Reviewed-by: Rick Chen
tion/qemu-riscv/qemu-riscv.c | 24
> include/configs/qemu-riscv.h| 10 --
> 2 files changed, 34 deletions(-)
Reviewed-by: Rick Chen
config | 5 +
> 1 file changed, 5 insertions(+)
Reviewed-by: Rick Chen
3d3 ("riscv: Update alignment for some sections in linker
> scripts")
> Signed-off-by: Bin Meng
>
> ---
> This fix should go into the v2023.07 release.
>
> arch/riscv/cpu/u-boot.lds | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
Reviewed-by: Rick Chen
Hi Leo,
Please help to push this patch ASAP.
Thanks,
Rick
iscv.h | 2 +-
> include/configs/sifive-unleashed.h | 2 +-
> include/configs/starfive-visionfive2.h | 1 +
> 4 files changed, 14 insertions(+), 7 deletions(-)
Reviewed-by: Rick Chen
> From: Yanhong Wang
> Sent: Thursday, June 15, 2023 5:37 PM
> To: u-boot@lists.denx.de; Rick Jian-Zhi Chen(陳建志) ; Leo
> Yu-Chi Liang(梁育齊) ; Joe Hershberger
> ; Ramon Fried
> Cc: Yanhong Wang ; Torsten Duwe ;
> Leyfoon Tan ; samin . guo
> ; Walker Chen ; Hal
> Feng
> Subject: [PATCH v5
spl.c | 157 +++
> 1 file changed, 157 insertions(+)
Reviewed-by: Rick Chen
> arch/riscv/dts/mpfs-icicle-kit.dts| 190 +---
> arch/riscv/dts/mpfs.dtsi | 442 --
> .../dt-bindings/clock/microchip-mpfs-clock.h | 29 +-
> .../microchip-mpfs-plic.h | 196
> .../interrupt-controller/riscv-hart.h | 17 -
Reviewed-by: Rick Chen
fig | 2 +-
> board/sipeed/maix/Kconfig | 2 +-
> drivers/timer/Makefile| 2 +-
> ...ive_clint_timer.c => riscv_aclint_timer.c} | 20 +--
> 14 files changed, 35 insertions(+), 35 deletions(-) rename
> arch/riscv/lib/{sifive_c
mine whether a syscon based approach needs to be taken to get the
> > base address of the ACLINT mswi device.
> >
> > [1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
> >
> > Signed-off-by: Bin Meng
>
> LGTM.
Sorry, forgot the signed up.
Reviewed-by: Rick Chen
>
> Thanks,
> Rick
> From: Bin Meng
> Sent: Monday, June 12, 2023 3:36 PM
> To: u-boot@lists.denx.de
> Cc: Leo Yu-Chi Liang(梁育齊) ; Rick Jian-Zhi Chen(陳建志)
>
> Subject: [PATCH 2/3] riscv: clint: Update the sifive clint ipi driver to
> support aclint
>
> This RISC-V ACLINT specification [1] defines a set of memory
Hi Bin,
> From: Bin Meng
> Sent: Monday, June 12, 2023 3:36 PM
> To: u-boot@lists.denx.de
> Cc: Anup Patel ; Atish Patra ;
> Bin Meng ; Palmer Dabbelt ; Paul
> Walmsley ; Rick Jian-Zhi Chen(陳建志)
>
> Subject: [PATCH 1/3] riscv: timer: Update the sifive clint timer driver to
> support aclint
| 2 +-
> doc/board/microchip/mpfs_icicle.rst | 6 +++---
Reviewed-by: Rick Chen
<--- cleared by lottery winner hart
> +----+ 0x804spl_clear_bss (start.S)
> | hole |
> ++
> | Image+DTB | <--- Assuming cleared/loaded by ROM
> ++ 0x800
>
> Signed-off
-+
> ++ ==> | hart N-1 stack|
> | hart 1 stack |++
> ++| ..|
> | ..|| malloc_base |
> ++++
> | hart N-1 stack|| GD|
> +++----+
&
Hi Minda
> From: Minda Chen
> Sent: Thursday, June 01, 2023 9:07 AM
> To: Leo Yu-Chi Liang(梁育齊) ; Rick Jian-Zhi Chen(陳建志)
> ; Simon Glass ; Stefan Roese
> ; Andrew Scull ; Pali Rohár
> ; Mark Kettenis
> Cc: u-boot@lists.denx.de; Mason Huo ; Leyfoon Tan
> ; Kevin Xie
> Subject: Re: [PATCH
---+
> ++ ==> | hart N-1 stack|
> | hart 1 stack |++
> ++| ..|
> | ..|| malloc_base |
> ++++
> | hart N-1 stack|| GD|
> +++----+
> |||
Hi Simon,
> Hi Rick,
>
> On Mon, 10 Apr 2023 at 01:26, Rick Chen wrote:
> >
> > Allow U-Boot to load 32 or 64 bits RISC-V Kernel Image
> > distinguishly. It helps to avoid someone maybe make a mistake
> > to run 32-bit U-Boot to load 64-bit kernel.
> From: Bin Meng
> Sent: Thursday, March 30, 2023 12:20 PM
> To: u-boot@lists.denx.de
> Cc: Andrew Scull ; Leo Yu-Chi Liang(梁育齊)
> ; Rick Jian-Zhi Chen(陳建志) ; Simon
> Glass
> Subject: [PATCH 7/8] riscv: spl: Remove relocation sections
>
> U-Boot SPL is not relocable. Drop these relocation
Allow U-Boot to load 32 or 64 bits RISC-V Kernel Image
distinguishly. It helps to avoid someone maybe make a mistake
to run 32-bit U-Boot to load 64-bit kernel.
Signed-off-by: Rick Chen
---
The patchset is based on Simon's patch:
riscv: Add a 64-bit image type
---
---
arch/riscv/include/asm/u
d to debug.
>
> Add a new property to make this explicit.
>
> The existing 'RISC-V' is now taken to mean 32-bit.
>
> Signed-off-by: Simon Glass
> ---
>
> boot/image.c| 3 ++-
> include/image.h | 3 ++-
> 2 files changed, 4 insertions(+), 2 deletions(-)
Reviewed-by: Rick Chen
rgument of prelink-riscv
>
> The argv[2] is never used in prelink-riscv. Drop it.
>
> Signed-off-by: Bin Meng
> ---
>
> Makefile | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Rick Chen
LF image that was mapped by
> previous mmap().
>
> Signed-off-by: Bin Meng
> ---
>
> tools/prelink-riscv.c | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Rick Chen
v.inc | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
Reviewed-by: Rick Chen
o don't bother reloading it.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/riscv/cpu/start.S | 1 -
> 1 file changed, 1 deletion(-)
Reviewed-by: Rick Chen
e end address hence load its address directly
> into register 't2' for optimization.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/riscv/cpu/start.S | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
Reviewed-by: Rick Chen
ial IO access instructions just like
> + ARM;
> * all IO is memory mapped.
> * Note that these are defined to perform little endian accesses
> * only. Their primary purpose is to access PCI and ISA peripherals.
Reviewed-by: Rick Chen
Hi Philip,
> From: U-Boot On Behalf Of Bernard, Philip
> Sent: Thursday, February 23, 2023 9:21 AM
> To: u-boot@lists.denx.de
> Subject: Boot from 64-bit memory address?
>
> Hi,
>
> Is it possible to boot from a DRAM memory address beyond the 32-bit boundary?
> I'm trying to configure a new
Add the 'missing-msg' for more detailed output
on missing system firmware.
Signed-off-by: Rick Chen
Reviewed-by: Leo Yu-Chi Liang
---
Changes in v2
- Add more descriptions about fw_dynamic.bin
---
arch/riscv/dts/binman.dtsi | 1 +
tools/binman/missing-blob-help | 6 ++
2 files changed
Hi Leo
> On Thu, Feb 16, 2023 at 09:19:45AM +0800, Rick Chen wrote:
> > Add the 'missing-msg' for more detailed output
> > on missing system firmware.
> >
> > Signed-off-by: Rick Chen
> > ---
> > arch/riscv/dts/binman.dtsi | 1 +
> > tools/b
o OpenSBI document
>
> [1]
> https://patchwork.ozlabs.org/project/uboot/patch/20230212070053.14800-1-peter...@andestech.com/
> ---
> MAINTAINERS| 1 +
> doc/arch/index.rst | 1 +
> doc/arch/riscv.rst | 74 ++
> 3 files changed, 76 insertions(+)
> create mode 100644 doc/arch/riscv.rst
Reviewed-by: Rick Chen
Add the 'missing-msg' for more detailed output
on missing system firmware.
Signed-off-by: Rick Chen
---
arch/riscv/dts/binman.dtsi | 1 +
tools/binman/missing-blob-help | 4
2 files changed, 5 insertions(+)
diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi
index
off-by: Leo Yu-Chi Liang
> ---
> configs/ae350_rv32_spl_defconfig | 6 +++---
> configs/ae350_rv32_spl_xip_defconfig | 6 +++---
> configs/ae350_rv64_spl_defconfig | 6 +++---
> configs/ae350_rv64_spl_xip_defconfig | 6 +++---
> 4 files changed, 12 insertions(+), 12 deletions(-)
Reviewed-by: Rick Chen
related defconfigs could also support newer Andes CPU IP,
> so modify the names of CPU from ax25 to andesv5, and board name from
> ax25-ae350 to ae350.
>
> Signed-off-by: Leo Yu-Chi Liang
Reviewed-by: Rick Chen
s with read and write callbacks to allow the 'mii'
> command to work. Use a timeout of 10 ms to wait for the R/W operations to
> complete.
>
> Signed-off-by: Sergei Antonov
> ---
Reviewed-by: Rick Chen
Tested-by: Rick Chen
I have verified this patch on AE350 platform and it work
lace 'phys_addr_t iobase' with 'struct ftmac100 *ftmac100' in struct
> ftmac100_data. It allows to remove casting in a number of places.
>
> Since priv->iobase is phys_addr_t, use phys_to_virt() to make a pointer from
> it.
>
> Signed-off-by: Sergei Antonov
Reviewed-by: Rick Chen
> So it will be named similarly to the related ftgmac100 driver.
> The old name 'nds32_mac' is not referred to anywhere in U-Boot.
>
> Signed-off-by: Sergei Antonov
> Reviewed-by: Ramon Fried
Reviewed-by: Rick Chen
Hi Zong,
> From: Leo Yu-Chi Liang(梁育齊)
> Sent: Monday, February 06, 2023 3:58 PM
> To: Simon Glass
> Cc: U-Boot Mailing List ; Rick Jian-Zhi Chen(陳建志)
> ; zong...@sifive.com; vincent.c...@sifive.com
> Subject: Re: Docs for RISC-V
>
> Hi Simon,
>
> On Thu, Feb 02, 2023 at 10:25:36AM -0700,
2 ++
> configs/ae350_rv32_spl_xip_defconfig | 2 ++
> configs/ae350_rv32_xip_defconfig | 2 ++
> configs/ae350_rv64_defconfig | 2 ++
> configs/ae350_rv64_spl_defconfig | 2 ++
> configs/ae350_rv64_spl_xip_defconfig | 2 ++
> configs/ae350_rv64_xip_defconfig | 2 ++
> 8 files changed, 16 insertions(+)
Reviewed-by: Rick Chen
/ae350_rv64_spl_xip_defconfig | 2 ++
> 5 files changed, 9 insertions(+)
Reviewed-by: Rick Chen
1 file changed, 68 insertions(+), 30 deletions(-)
Reviewed-by: Rick Chen
changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Rick Chen
arch/riscv/include/asm/arch-andes/csr.h | 29 +++
> 2 files changed, 41 insertions(+), 37 deletions(-) create mode 100644
> arch/riscv/include/asm/arch-andes/csr.h
Reviewed-by: Rick Chen
Peter Lin
> Reviewed-by: Leo Yu-Chi Liang
> ---
> drivers/cache/cache-v5l2.c | 32
> 1 file changed, 24 insertions(+), 8 deletions(-)
Reviewed-by: Rick Chen
Hi Peter,
> From: Peter Yu-Chien Lin(林宇謙)
> Sent: Thursday, January 19, 2023 3:06 PM
> To: u-boot@lists.denx.de
> Cc: Leo Yu-Chi Liang(梁育齊) ; Rick Jian-Zhi Chen(陳建志)
> ; Peter Yu-Chien Lin(林宇謙)
> Subject: [PATCH 08/11] configs: ae350: Enable v5l2 cache for AE350 platforms
>
> Enable cache-v5l2
ard_init()
>
> The L2-cache is not enabled currently, the enbale_caches() will call the
> v5l2_enable() callback to enable it in SPL.
>
> Signed-off-by: Yu Chien Peter Lin
> ---
> board/AndesTech/ax25-ae350/ax25-ae350.c | 17 +
> 1 file changed, 9 insertions(+), 8 deletions(-)
Reviewed-by: Rick Chen
--
> drivers/cache/Kconfig | 1 -
> 3 files changed, 2 insertions(+), 93 deletions(-)
Reviewed-by: Rick Chen
LIC is used for external interrupt, while PLICSW is an Andes-specific design
> for software interrupt.
>
> Signed-off-by: Yu Chien Peter Lin
> ---
> arch/riscv/include/asm/global_data.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
It seems not relative to cache
> On Wed, Jan 4, 2023 at 10:08 AM Rick Chen wrote:
> >
> > Original openSBI (without FW_PIC) will relocate itself
>
> nits: OpenSBI
>
> > from 0x100 to 0x0. After openSBI added FW_PIC codes,
>
> ditto
OK, will fix it.
>
> > it will not
details can refer to commit cb052d771200
("riscv: qemu: spl: Fix booting Linux kernel with OpenSBI 1.0+")
Signed-off-by: Rick Chen
Reviewed-by: Samuel Holland
Reviewed-by: Bin Meng
---
Changes in v4
- fix openSBI typo
---
board/AndesTech/ax25-ae350/Kconfig | 2 +-
1 file changed, 1 inser
details can refer to commit cb052d771200
("riscv: qemu: spl: Fix booting Linux kernel with OpenSBI 1.0+")
Signed-off-by: Rick Chen
Reviewed-by: Samuel Holland
---
Changes in v3
- fix typos
---
board/AndesTech/ax25-ae350/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Add src and dst address checking, if they
are the same address, just return and don't
copy data anymore.
Signed-off-by: Rick Chen
---
Changes in v3
- new patch: separate from [1/2]
---
arch/riscv/lib/memcpy.S | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/riscv/lib/memcpy.S b/arch
by declare the
board_spl_fit_buffer_addr() to replace the original one.
The larger image size (eq: Kernel Image 10~20MB), it
can save more booting time.
Signed-off-by: Rick Chen
---
Changes in v3
- fix aligment
- refine board_spl_fit_buffer_addr
---
arch/riscv/cpu/ax25/Makefile | 1 +
arch/riscv/cpu
> Hi Rick,
>
> On 1/3/23 02:20, Rick Chen wrote:
> > When fit image boots from ram, the payload will
> > be prepared in the address of SPL_LOAD_FIT_ADDRESS.
> > In spl fit generic flow, it will malloc another
> > memory address and copy whole fit image to this
Hi Samuel
> On 1/3/23 02:18, Rick Chen wrote:
> > Original openSBI (without FW_PIC) will relocate itselt
>
> typo: itself
OK, I will fix it.
>
> > from 0x100 to 0x0. After openSBI added FW_PIC codes,
> > it will not relocate any more and alaways run at 0x10
-by: Rick Chen
---
Changes in v2
- Move spl.c to board level instead of arch level
---
arch/riscv/cpu/ax25/Makefile | 1 +
arch/riscv/cpu/ax25/spl.c| 31 +++
arch/riscv/lib/memcpy.S | 2 ++
3 files changed, 34 insertions(+)
create mode 100644 arch/riscv/cpu
details can refer to commit cb052d771200
("riscv: qemu: spl: Fix booting Linux kernel with OpenSBI 1.0+")
Signed-off-by: Rick Chen
---
Changes in v2
- fix typo
- describe why is this change a must have
---
board/AndesTech/ax25-ae350/Kconfig | 2 +-
1 file changed, 1 insertion(+),
CCTL operations are available to Supervisor/User-mode
software under the control of the mcache_ctl.CCTL_SUEN
control bit. Enable it to support Supervisor(and User)
CCTL operations.
Signed-off-by: Rick Chen
---
Changes in v2
- fix typo
- correct aligment
---
arch/riscv/cpu/ax25/cpu.c | 18
> On 12/27/22 21:22, Rick Chen wrote:
> > Hi Samuel,
> >
> > Samuel Holland 於 2022年12月28日 週三 上午10:47寫道：
> >>
> >> On 12/22/22 01:21, Rick Chen wrote:
> >>> When fit image boots from ram, the payload will
> >>> be prepared in the
Hi Samuel,
Samuel Holland 於 2022年12月28日 週三 上午10:47寫道：
>
> On 12/22/22 01:21, Rick Chen wrote:
> > When fit image boots from ram, the payload will
> > be prepared in the address of SPL_LOAD_FIT_ADDRESS.
> > In spl fit generic flow, it will malloc another
> > mem
> On Thu, Dec 22, 2022 at 4:07 PM Rick Chen wrote:
> >
> > > On Thu, Dec 22, 2022 at 1:23 PM Rick Chen wrote:
> > > >
> > > > Hi Bin,
> > > >
> > > > > On Wed, Dec 21, 2022 at 10:29 AM Rick Chen wrote:
>
> On Thu, Dec 22, 2022 at 1:23 PM Rick Chen wrote:
> >
> > Hi Bin,
> >
> > > On Wed, Dec 21, 2022 at 10:29 AM Rick Chen wrote:
> > > >
> > > > Change openSBI load address from 0x100 to 0x0 and it
> > >
> > > nits: Ope
-by: Rick Chen
---
arch/riscv/lib/memcpy.S | 2 ++
arch/riscv/lib/spl.c| 16
2 files changed, 18 insertions(+)
diff --git a/arch/riscv/lib/memcpy.S b/arch/riscv/lib/memcpy.S
index 00672c19ad..9884077c93 100644
--- a/arch/riscv/lib/memcpy.S
+++ b/arch/riscv/lib/memcpy.S
| 23
> arch/riscv/cpu/jh7110/dram.c | 38 +
> arch/riscv/cpu/jh7110/spl.c | 56 +++
> .../include/asm/arch-jh7110/jh7110-regs.h | 20 +++
> arch/riscv/include/asm/arch-jh7110/spl.h | 13 +++++
> 6 files changed, 160 insertions(+)
Reviewed-by: Rick Chen
Hi Bin,
> On Wed, Dec 21, 2022 at 10:29 AM Rick Chen wrote:
> >
> > Change openSBI load address from 0x100 to 0x0 and it
>
> nits: OpenSBI
OK, will fix it.
>
> > will start to run at 0x0 directly without relocation.
> >
> > Signed-off-by: Rick Che
Hi Bin
> On Wed, Dec 21, 2022 at 11:00 AM Rick Chen wrote:
> >
> > CCTL operations are available to Supervisor/User-mode
> > software under the control of the mcache_ctl.CCTL_SUEN
> > control bit. Enable it to support Superviosr(and User)
>
> typo: Supervi
CCTL operations are available to Supervisor/User-mode
software under the control of the mcache_ctl.CCTL_SUEN
control bit. Enable it to support Superviosr(and User)
CCTL operations.
Signed-off-by: Rick Chen
---
arch/riscv/cpu/ax25/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git
Change openSBI load address from 0x100 to 0x0 and it
will start to run at 0x0 directly without relocation.
Signed-off-by: Rick Chen
---
board/AndesTech/ax25-ae350/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/AndesTech/ax25-ae350/Kconfig
b/board
> On 12/13/22 11:24, Tom Rini wrote:
> > On Tue, Dec 13, 2022 at 08:42:47AM +0800, Rick Chen wrote:
> >> Hi Sean,
> >>
> >>> On 12/12/22 10:03, Tom Rini wrote:
> >>>> On Mon, Dec 12, 2022 at 02:45:10PM +0800, Rick Chen wrote:
> >>>&
Hi Tom,
> On Wed, Dec 14, 2022 at 08:49:03AM +0800, Rick Chen wrote:
> > Hi Tom,
> >
> > > On Tue, Dec 13, 2022 at 10:06:50AM +0800, Rick Chen wrote:
> > > > > On Mon, Dec 12, 2022 at 03:49:10PM +0800, Rick Chen wrote:
> > > > > > >
Hi Tom,
> On Tue, Dec 13, 2022 at 10:06:50AM +0800, Rick Chen wrote:
> > > On Mon, Dec 12, 2022 at 03:49:10PM +0800, Rick Chen wrote:
> > > > > On 12/7/22 01:23, Rick Chen wrote:
> > > > > > In RISC-V, it only provide normal mode booting currently
> On Mon, Dec 12, 2022 at 03:49:10PM +0800, Rick Chen wrote:
> > > On 12/7/22 01:23, Rick Chen wrote:
> > > > In RISC-V, it only provide normal mode booting currently.
> > > > To speed up the booting process, here provide SPL_OPENSBI_OS_BOOT
> > > >
Hi Tom
> On Mon, Dec 12, 2022 at 02:45:10PM +0800, Rick Chen wrote:
> > Hi Tom
> >
> > > On Fri, Dec 09, 2022 at 08:48:37AM -0500, Sean Anderson wrote:
> > > > On 12/7/22 01:23, Rick Chen wrote:
> > > > > In RISC-V, it only provide normal mode b
Hi Sean,
> On 12/12/22 10:03, Tom Rini wrote:
> > On Mon, Dec 12, 2022 at 02:45:10PM +0800, Rick Chen wrote:
> >> Hi Tom
> >>
> >>> On Fri, Dec 09, 2022 at 08:48:37AM -0500, Sean Anderson wrote:
> >>>> On 12/7/22 01:23, Rick Chen wrote:
> On 12/7/22 01:23, Rick Chen wrote:
> > In RISC-V, it only provide normal mode booting currently.
> > To speed up the booting process, here provide SPL_OPENSBI_OS_BOOT
> > to achieve this feature which will be call Fast-Boot mode. By
>
> Can you name this something
Hi Tom
> On Fri, Dec 09, 2022 at 08:48:37AM -0500, Sean Anderson wrote:
> > On 12/7/22 01:23, Rick Chen wrote:
> > > In RISC-V, it only provide normal mode booting currently.
> > > To speed up the booting process, here provide SPL_OPENSBI_OS_BOOT
> > > to ach
Descript how to boot Kernel with Fast Boot and record
booting messages here.
Signed-off-by: Rick Chen
---
doc/board/AndesTech/ax25-ae350.rst | 140 +
1 file changed, 140 insertions(+)
diff --git a/doc/board/AndesTech/ax25-ae350.rst
b/doc/board/AndesTech/ax25-ae350
Add defconfig for Fast Boot
Signed-off-by: Rick Chen
---
board/AndesTech/ax25-ae350/ax25-ae350.c | 7 ++-
configs/ae350_rv32_spl_fastboot_defconfig | 53 +++
configs/ae350_rv64_spl_fastboot_defconfig | 53 +++
3 files changed, 111 insertions(+), 2
By enabling SPL_OPENSBI_OS_BOOT, it will generate linux.itb instead
of default u-boot.itb after compiling. And Lnux Kernel Image will be
appended in linux.itb. Then it can jump to Linux Kernel from openSBI
directly.
Signed-off-by: Rick Chen
---
arch/riscv/dts/binman.dtsi | 24
.
Signed-off-by: Rick Chen
---
common/spl/Kconfig | 14 ++
common/spl/spl_fit.c | 3 ++-
common/spl/spl_opensbi.c | 25 -
3 files changed, 28 insertions(+), 14 deletions(-)
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 05181bdba3
> From: Zong Li
> Sent: Tuesday, November 29, 2022 10:02 AM
> To: Sean Anderson
> Cc: s...@chromium.org; michal.si...@amd.com; sean.ander...@seco.com; Leo
> Yu-Chi Liang(梁育齊) ; Rick Jian-Zhi Chen(陳建志)
> ; u-boot@lists.denx.de
> Subject: Re: [PATCH] riscv: use imply instead of select for
ply instead of select for SPL_SEPARATE_BSS
>
> Use imply instead of select, then it can still be disabled by board-specific
> defconfig, or be set to n manually.
>
> Signed-off-by: Zong Li
> ---
> arch/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Rick Chen
ff-by: Heinrich Schuchardt
> >>
> >> ---
> >> arch/riscv/Kconfig | 14 +++---
> >> 1 file changed, 7 insertions(+), 7 deletions(-)
Reviewed-by: Rick Chen
Hi Heinrich
> From: Heinrich Schuchardt
> Sent: Tuesday, November 08, 2022 11:14 PM
> To: Bin Meng
> Cc: Rick Jian-Zhi Chen(陳建志) ; Leo Yu-Chi Liang(梁育齊)
> ; Conor Dooley ;
> u-boot@lists.denx.de
> Subject: Re: [PATCH 1/1] riscv: clarify meaning of CONFIG_SBI_V02
>
> On 11/8/22 16:05, Bin Meng
.
>
> Signed-off-by: Yu Chien Peter Lin
> ---
> arch/riscv/cpu/cpu.c | 14 +++---
> 1 file changed, 11 insertions(+), 3 deletions(-)
Reviewed-by: Rick Chen
deletions(-) rename
> arch/riscv/lib/{andes_plic.c => andes_plicsw.c} (76%)
Reviewed-by: Rick Chen
ion is made at the end of 32-bit DDR to
> provide some memory for the HSS to use.
>
> Signed-off-by: Padmarao Begari
> Reviewed-by: Conor Dooley
> ---
> board/microchip/mpfs_icicle/Kconfig | 7 +++
> configs/microchip_mpfs_icicle_defconfig | 1 +
> 2 files changed, 8 insertions(+)
Reviewed-by: Rick Chen
d to the Icicle Kit by using the
> Mikroe Flash 5 click board and the Pi 3 Click shield.
>
> Signed-off-by: Padmarao Begari
> Reviewed-by: Conor Dooley
> ---
> arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 16 ++++
> 1 file changed, 16 insertions(+)
Reviewed-by: Rick Chen
Reviewed-by: Conor Dooley
> ---
> arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 75 +---
> 1 file changed, 17 insertions(+), 58 deletions(-)
Reviewed-by: Rick Chen
Check firmware_fdt_addr header to see if it
is a valid fdt blob.
Signed-off-by: Rick Chen
Reviewed-by: Leo Yu-Chi Liang
---
board/AndesTech/ax25-ae350/ax25-ae350.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c
b/board/AndesTech
OpenSBI has been updated to support 8-core AE350 platform,
> the plicsw configuration needs to be modified accordingly.
>
> Signed-off-by: Yu Chien Peter Lin
> ---
> arch/riscv/lib/andes_plic.c | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
Reviewed-by: Rick Chen
Reported-by: Yangjie Zhang
> Signed-off-by: Bin Meng
> Tested-by: Yangjie Zhang
>
> ---
>
> board/emulation/qemu-riscv/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Rick Chen
Check firmware_fdt_addr header to see if it is a valid
fdt blob.
Signed-off-by: Rick Chen
---
board/AndesTech/ax25-ae350/ax25-ae350.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c
b/board/AndesTech/ax25-ae350/ax25-ae350.c
index
quot;Standard extension for Single-Precision Floating Point"
> >> + default y
> >
> >
> > Shall this default y need to depend on RV32 ?
>
> All RV64 boards that we currently support have the F and D extension and
> these extensions are in RV64GC. There is no
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