of Capabilities Pointer Register.
3. Find the address of requested capability from the first capability.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
arch/powerpc/include/asm/fsl_pci.h | 13 +---
drivers/pci/fsl_pci_init.c | 40 +++---
drivers/pci/pci.c
SGMII5/6 and SGMII7/8 are not on the same slot on P5040
according to the serdes protocol.
So it is not proper to organize SGMII5/6 and SGMII7/8
on one bus and SGMII5/6 can't work.
So a new bus SUPER_HYDRA_FM3_SGMII_MDIO is added for
SGMII5/6
Signed-off-by: Zhao Qiang b45...@freescale.com
to confirm the protocol before
setting PHY addresses.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
board/freescale/b4860qds/b4860qds_qixis.h | 5 +++
board/freescale/b4860qds/eth_b4860qds.c | 18 +++
board/freescale/corenet_ds/eth_hydra.c | 6
board/freescale/corenet_ds
of Capabilities Pointer Register.
3. Find the address of requested capability from the first capability.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
arch/powerpc/include/asm/fsl_pci.h | 13 +---
drivers/pci/fsl_pci_init.c | 44 +++---
drivers/pci/pci.c
capability from the first capability.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
arch/powerpc/include/asm/fsl_pci.h | 13 +---
drivers/pci/fsl_pci_init.c | 44 +++---
drivers/pci/pci.c | 65 ++
include/pci.h
capability from the first capability.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
Changes for v2:
-Put an variable into #ifdef and #endif
Changes for v3:
-Modify the patch description
arch/powerpc/include/asm/fsl_pci.h | 13 +---
drivers/pci/fsl_pci_init.c | 44
The default partition table matches the .dts files for these boards in
Linux. This allows these partitions to be used by name with U-Boot's
nand command.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
include/configs/P1010RDB.h | 7 +++
1 file changed, 7 insertions(+)
diff --git
T1040 has QE-related addresses different from other boards,
modify those addresses value with macro CONFIG_PPC_T1040
and CONFIG_T1040QDS.
Add function qe_board_setup to mux the bus to tdm or uart
according to hwconfig.
Signed-off-by: Jiucheng Xu jiucheng...@freescale.com
Signed-off-by: Zhao Qiang
T1040 has QE-related addresses different from other boards,
modify those addresses value with macro CONFIG_PPC_T1040
and CONFIG_T1040QDS.
Add function qe_board_setup to mux the bus to tdm or uart
according to hwconfig.
Signed-off-by: Jiucheng Xu jiucheng...@freescale.com
Signed-off-by: Zhao Qiang
CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address.
Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address,
and CONFIG_SYS_QE_FW_ADDR for QE microcode address.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
README | 9
CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address.
Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address,
and CONFIG_SYS_QE_FW_ADDR for QE microcode address.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
Changes for v2:
- no
Changes for v3
The u-qe of T1040 has addresses different from qe,
modify those addresses value for both u-qe and qe.
Add function qe_board_setup to mux the bus to tdm or uart
according to hwconfig.
Signed-off-by: Jiucheng Xu jiucheng...@freescale.com
Signed-off-by: Zhao Qiang b45...@freescale.com
---
Changes
CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address.
Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address,
and CONFIG_SYS_QE_FW_ADDR for QE microcode address.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
Changes for v2:
- no
Changes for v3
The u-qe of T1040 has addresses different from qe,
modify those addresses value for both u-qe and qe.
Add function qe_board_setup to mux the bus to tdm or uart
according to hwconfig.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
Changes for v2:
- modify CONFIG_SYS_QE_FMAN_FW_ADDR
ls1021 is arm-core and supports qe too.
Move immap_qe.h into common directory for both arm and powerpc.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
arch/powerpc/cpu/mpc83xx/cpu.c | 2 +-
arch/powerpc/cpu/mpc83xx/fdt.c | 2 +-
drivers
In new board P1010RDB-PB, the interrupt vector table is at
the start of memory. So if the start_address needs to be set
a proper value.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
include/configs/P1010RDB.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include
Function genphy_parse_link() used if (mii_reg BMSR_ANEGCAPABLE) before
while if (phydev-supported SUPPORTED_Autoneg) now.
So assign phydev-supported to phydev-drv-features for ar8031/8033
to enable autonegotiation.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
drivers/net/phy/atheros.c
ls1021 is arm-core and support qe which is u-qe.
add u-qe init for arm board.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
arch/arm/include/asm/arch-ls102xa/config.h | 4
arch/arm/include/asm/global_data.h | 8
drivers/Makefile | 1
T2080 v1.0 has this errata while v1.1 has fixed
this errata by hardware, add a new function to
check the SVR_SOC_VER, SVR_MAJ and SVR_MIN first,
if the cpu is T2080 and version is not v1.0, doesn't
run the a007212 errata_workaround.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
arch/powerpc
T2080 v1.0 has this errata while v1.1 has fixed
this errata by hardware, add a new function to
check the SVR_SOC_VER, SVR_MAJ and SVR_MIN first,
if the cpu is T2080 and version is not v1.0, doesn't
run the a007186 errata_workaround.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
arch/powerpc
Signed-off-by: Zhao Qiang b45...@freescale.com
---
board/freescale/ls1021atwr/ls1021atwr.c | 7 +++
include/configs/ls1021atwr.h| 6 ++
2 files changed, 13 insertions(+)
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c
b/board/freescale/ls1021atwr/ls1021atwr.c
index
add qe support to ls1021aqds
Signed-off-by: Zhao Qiang b45...@freescale.com
---
board/freescale/ls1021aqds/ls1021aqds.c | 8
include/configs/ls1021aqds.h| 5 +
2 files changed, 13 insertions(+)
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c
b/board/freescale
T2080 v1.0 has this errata while v1.1 has fixed
this errata by hardware, add a new function has_errata_a007186
to check the SVR_SOC_VER, SVR_MAJ and SVR_MIN first,
if the sil has errata a007186, then run the errata code,
if not, doesn't run the code.
Signed-off-by: Zhao Qiang b45...@freescale.com
T2080 v1.0 has this errata while v1.1 has fixed
this errata by hardware, add a new function has_errata_a007186
to check the SVR_SOC_VER, SVR_MAJ and SVR_MIN first,
if the sil has errata a007186, then run the errata code,
if not, doesn't run the code.
Signed-off-by: Zhao Qiang b45...@freescale.com
T2080 v1.0 has this errata while v1.1 has fixed
this errata by hardware, add a new function has_errata_a007186
to check the SVR_SOC_VER, SVR_MAJ and SVR_MIN first,
if the sil has errata a007186, then run the errata code,
if not, doesn't run the code.
Signed-off-by: Zhao Qiang b45...@freescale.com
capability from the first capability.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
Changes for v2:
-Put an variable into #ifdef and #endif
Changes for v3:
-Modify the patch description
Changes for v4:
-rebase on u-boot master branch
arch/powerpc/include/asm/fsl_pci.h | 18
capability from the first capability.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
Changes for v2:
-Put an variable into #ifdef and #endif
Changes for v3:
-Modify the patch description
Changes for v4:
-Rebase on u-boot master branch
Changes for v5:
-Remove a blank
CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address.
Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address,
and CONFIG_SYS_QE_FW_ADDR for QE microcode address.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
Changes for v2:
- no
Changes for v3
The u-qe of T1040 has addresses different from qe,
modify those addresses value for both u-qe and qe.
Add function qe_board_setup to mux the bus to tdm or uart
according to hwconfig.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
Changes for v2:
- modify CONFIG_SYS_QE_FMAN_FW_ADDR
The u-qe of T1040 has addresses different from qe,
modify those addresses value for both u-qe and qe.
Add function qe_board_setup to mux the bus to tdm or uart
according to hwconfig.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
Changes for v2:
- modify CONFIG_SYS_QE_FMAN_FW_ADDR
CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address.
Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address,
and CONFIG_SYS_QE_FW_ADDR for QE microcode address.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
Changes for v2:
- no
Changes for v3
add CONFIG_QE, CONFIG_U_QE and CONFIG_SYS_QE_FW_ADDR into
include/configs/T1040RDB.h
Signed-off-by: Zhao Qiang b45...@freescale.com
---
include/configs/T1040RDB.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/configs/T1040RDB.h b/include/configs/T1040RDB.h
index 7420db9
usb hub for p1010rdb-pb is not needed to re-power on
when init it.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
common/usb_hub.c | 4
1 file changed, 4 insertions(+)
diff --git a/common/usb_hub.c b/common/usb_hub.c
index ffac0e7..edb1fc0 100644
--- a/common/usb_hub.c
+++ b/common
Modify code to adapt to both u-qe and qe.
U_QE is a kind of cutted QE.
the differences between U_QE and QE
1. UCC: U_QE supports 2 UCCs while QE supports up to 8 UCCs.
2. IMMR: have different immr base addr.
3. iopin: U_QE doesn't need to config iopin.
Signed-off-by: Zhao
Add u-qe support for t1040qds
Signed-off-by: Zhao Qiang b45...@freescale.com
---
Changes for v2:
- modify CONFIG_SYS_QE_FMAN_FW_ADDR to CONFIG_SYS_FMAN_FW_ADDR and
CONFIG_SYS_QE_FW_ADDR
Changes for v3:
- use CONFIG_U_QE instead of CONFIG_PPC_T1040
Changes for v4:
- ifdef
CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address.
Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address,
and CONFIG_SYS_QE_FW_ADDR for QE microcode address.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
Changes for v2:
- no
Changes for v3
The patch with commit id 020bbcb76b5be0d5406d2ae7c26dbdb013ead812
adds some init codes for XHCI but not for EHCI.
It will causes a bug for EHCI.
so use macro #ifndef CONFIG_USB_EHCI to mask
it for EHCI.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
common/usb_hub.c | 5 +
1 file changed
The patch with commit id 020bbcb76b5be0d5406d2ae7c26dbdb013ead812
adds some init codes for XHCI but not for other usb controllers.
And it will causes a bug for EHCI.
so use macro #ifdef CONFIG_USB_XHCI to run it just for XHCI.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
common/usb_hub.c
ar8031 has the same config steps with ar8021, so change its
config func to ar8021_config instead of genphy_config.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
drivers/net/phy/atheros.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/phy/atheros.c b/drivers
when qe-ucode fails to be uploaded, disable qe.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
drivers/qe/qe.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index b1da75e..c77cc16 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -14,6 +14,8
when qe-ucode fails to be uploaded, disable qe.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
Changes for v2:
- add #ifdef CONFIG_MPC85xx
drivers/qe/qe.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index b5ddc4b
when qe-ucode fails to be uploaded, deep sleep will hang,
so disable qe when there is no qe-ucode.
Only mpc85xx support deep sleep and mpc83xx doesn't,
it doesn't need to disable qe for mpc83xx.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
Changes for v2:
- add #ifdef CONFIG_MPC85xx
when qe-ucode fails to be uploaded, deep sleep will hang.
if there is no qe-ucode, disable qe module for platforms
which support deep sleep
Signed-off-by: Zhao Qiang b45...@freescale.com
---
Changes for v2:
- add #ifdef CONFIG_MPC85xx
Changes for v3:
- modify commit msg
Changes
Signed-off-by: Zhao Qiang b45...@freescale.com
---
drivers/qe/qe.c | 125 +++-
drivers/qe/qe.h | 1 +
2 files changed, 125 insertions(+), 1 deletion(-)
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 4de1881..5485672 100644
--- a/drivers
T2080 v1.0 has this errata while v1.1 has fixed
this errata by hardware, add a new function has_errata_a007186
to check the SVR_SOC_VER, SVR_MAJ and SVR_MIN first,
if the sil has errata a007186, then run the errata code,
if not, doesn't run the code.
Signed-off-by: Zhao Qiang b45...@freescale.com
Signed-off-by: Zhao Qiang b45...@freescale.com
---
Changes for v2:
- put u_qe functions under #ifdef CONFIG_U_QE
drivers/qe/qe.c | 129 +++-
drivers/qe/qe.h | 6 ++-
2 files changed, 133 insertions(+), 2 deletions(-)
diff --git
IRAM will power off and microcode will lost when system go into
deepsleep, so upload it when resume deepsleep.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
board/freescale/ls1021aqds/ls1021aqds.c | 4 +-
drivers/qe/qe.c | 76
Deep sleep for generic board is supported now,
and it use CONFIG_FSL_DEEP_SLEEP instead of CONFIG_DEEP_SLEEP,
so modify it for qe.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
drivers/qe/qe.c | 23 +--
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git
Deep sleep for generic board is supported now,
and it use CONFIG_FSL_DEEP_SLEEP instead of CONFIG_DEEP_SLEEP,
so modify it for qe.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
drivers/qe/qe.c | 31 +--
1 file changed, 21 insertions(+), 10 deletions(-)
diff
Deep sleep for generic board is supported now,
modify qe deep-sleep code to adapt it.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
Changes for v2:
- rebase
drivers/qe/qe.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index
T2080QDS PEX1/Slot#1 will down-train from x4 to x2,
with SRDS_PRTCL_S1 = 0x66 and SRDS_PRTCL_S2 = 0x15.
Soft reset PCIe can fix this issue, this is a workaround.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
drivers/pci/fsl_pci_init.c | 17 +
include/configs/T208xQDS.h | 1
T2080QDS PEX1/Slot#1 will down-train from x4 to x2,
Soft reset PCIe can fix this issue, this is a workaround.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
changes for v2
- modify the commit message
drivers/pci/fsl_pci_init.c | 17 +
include/configs/T208xQDS.h | 1
Muram will power off during deepsleep, and the microcode of qe
in muram will be lost, it should be reload when resume.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
arch/arm/include/asm/arch-ls102xa/config.h | 4 --
board/freescale/common/mpc85xx_sleep.c | 8 +++
drivers/qe/qe.c
T2080QDS PEX1/Slot#1 will down-train from x4 to x2,
with SRDS_PRTCL_S1 = 0x66 and SRDS_PRTCL_S2 = 0x15.
Soft reset PCIe can fix this issue.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
changes for v2
- modify the commit message
changes for v3
- use CONFIG_FSL_PCIE_RESET
when using printf, the parameter type need to be compatible
type, so transform them to compatible type
Signed-off-by: Zhao Qiang b45...@freescale.com
---
drivers/qe/qe.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 84e1433
strncpy is safer than strcpy, use it to instead of strcpy.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
drivers/qe/qe.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index f1df0a4..08620b2 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe
Muram will power off during deepsleep, and the microcode of qe
in muram will be lost, it should be reload when resume.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
board/freescale/common/arm_sleep.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/board/freescale/common
qe-tdm is muxed with diu, if hwconfig setted as qe-tdm,
assign muxed pins to qe-tdm, then delete diu node from
device tree.
Signed-off-by: Zhao Qiang qiang.z...@freescale.com
---
changes for v2
- move fdt_del_diu to arch/powerpc/cpu/mpc85xx/fdt.c
- add new .h file arch/powerpc
qe-tdm is muxed with diu, if hwconfig setted as qe-tdm,
assign muxed pins to qe-tdm, then delete diu node from
device tree.
Signed-off-by: Zhao Qiang qiang.z...@freescale.com
---
board/freescale/t104xrdb/cpld.h | 1 +
board/freescale/t104xrdb/t104xrdb.c | 19 +++
2 files
On Thu 8/27/2015 2:36 pm, Kushwaha Prabhakar-B32579 wrote:
-Original Message-
From: Kushwaha Prabhakar-B32579
Sent: Thursday, August 27, 2015 2:36 PM
To: Zhao Qiang-B45475
Cc: u-boot@lists.denx.de; Sun York-R58495; Jain Priyanka-B32167; Zhao
Qiang-B45475
Subject: RE: [PATCH
-Original Message-
From: Kushwaha Prabhakar-B32579
Sent: Thursday, August 27, 2015 4:23 PM
To: Zhao Qiang-B45475
Cc: u-boot@lists.denx.de; Sun York-R58495; Jain Priyanka-B32167
Subject: RE: [PATCH] t1040d4rdb: assign muxed pins to qe-tdm when set
hwconfig qe-tdm
From: Zhao Qiang <b45...@freescale.com>
ls1021 is arm-core and support qe which is u-qe.
add u-qe init for arm board.
Signed-off-by: Zhao Qiang <b45...@freescale.com>
---
arch/arm/include/asm/arch-ls102xa/config.h | 4
arch/arm/include/asm/global_data.h | 8 +
From: Zhao Qiang <b45...@freescale.com>
the address of uboot changed, so change qe ucode
Signed-off-by: Zhao Qiang <b45...@freescale.com>
---
include/configs/ls1021aqds.h | 2 +-
include/configs/ls1021atwr.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/inc
qe: add qe support MACRO to ls1021a-twr head file
Signed-off-by: Zhao Qiang <qiang.z...@freescale.com>
---
board/freescale/ls1021atwr/ls1021atwr.c | 7 +++
include/configs/ls1021atwr.h| 6 ++
2 files changed, 13 insertions(+)
diff --git a/board/freescale/ls10
add qe support MACRO to ls1021aqds head file
Signed-off-by: Zhao Qiang <qiang.z...@freescale.com>
---
board/freescale/ls1021aqds/ls1021aqds.c | 8
include/configs/ls1021aqds.h| 6 ++
2 files changed, 14 insertions(+)
diff --git a/board/freescale/ls1021aqds/ls1021
There are uQE on ls1043ardb board, add uQE support for the board.
Call u_qe_init in ls1043ardb's board_init.
Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
---
Changes for v2:
- get qe_immr directly instead of qe_base
Changes for v3:
- NA
Changes for v4:
- NA
C
Pin-muxing code should be in config_board_mux, move USB muxing
config to config_board_mux.
Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
---
Changes for v2:
- NA
Changes for v3:
- split from "[PATCH v2 3/3] QE: assgin pins to QE-HDLC"
Changes for v4:
- N
QE-HDLC and USB multi-use the pins, modify the pin-muxing code
for them, when set "hwconfig=qe-hdlc" in uboot, assign the pins
to QE-HDLC, if not, assgin it to USB
Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
---
Changes for v2:
- NA
Changes for v3:
- split fro
there are some code in qe.c not used for micro QE,
use "#ifdef CONFIG_QE" to mask them.
Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
---
Changes for v2:
- new added
Changes for v3:
- NA
Changes for v4:
- NA
Changes for v5:
- modify commit mess
*Changes in v4:
-[PATCH v4 4/4] qe: assgin pins to qe-hdlc
- modify the format of multi-line comments
*Changes in v3:
-split [PATCH v2 3/3] QE: assgin pins to QE-HDLC to two patches:
[PATCH v3 3/4] ls1043rdb: move USB mux config to config_board_mux
and [PATCH v3 4/4] qe: assgin pins
Upload qe microcode on ls1043ardb
Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
---
board/freescale/ls1043ardb/ls1043ardb.c | 8
drivers/qe/qe.c | 6 ++
include/configs/ls1043ardb.h| 7 +++
3 files changed, 17 insertions(+), 4 del
USB pins are muxed with other feature, move USB mux config
to config_board_mux.
Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
---
board/freescale/ls1043ardb/ls1043ardb.c | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/board/fre
use "#ifdef CONFIG_QE" to mask the codes
not used for micro QE
Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
---
drivers/qe/qe.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 08620b2..2a9e61b 100644
--- a/drivers/qe/qe.c
+++ b
qe-hdlc and usb multi-use the pins, when set hwconfig=qe-hdlc,
assign the pins to qe-hdlc, if not, assgin it to usb
Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
---
board/freescale/ls1043ardb/ls1043ardb.c | 53 ++---
1 file changed, 43 insertions(+), 10 del
Upload qe microcode on ls1043ardb
Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
---
board/freescale/ls1043ardb/ls1043ardb.c | 8
drivers/qe/qe.c | 6 ++
include/configs/ls1043ardb.h| 7 +++
3 files changed, 17 insertions(+), 4 del
use "#ifdef CONFIG_QE" to mask the codes
not used for micro QE
Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
---
drivers/qe/qe.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 08620b2..2a9e61b 100644
--- a/drivers/qe/qe.c
+++ b
*Changes in v3:
- split [PATCH v2 3/3] QE: assgin pins to QE-HDLC to two patches:
[PATCH v3 3/4] ls1043rdb: move USB mux config to config_board_mux
and [PATCH v3 4/4] qe: assgin pins to qe-hdlc.
*Changes in v2:
- Add new patch in patchset.QE: mask the codes not used for micro QE
- [PATCH v2
USB pins are muxed with other feature, move USB mux config
to config_board_mux.
Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
---
board/freescale/ls1043ardb/ls1043ardb.c | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/board/fre
qe-hdlc and usb multi-use the pins, when set hwconfig=qe-hdlc,
assign the pins to qe-hdlc, if not, assgin it to usb
Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
---
board/freescale/ls1043ardb/ls1043ardb.c | 51 ++---
1 file changed, 41 insertions(+), 10 del
Upload QE microcode on ls1043ardb
Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
---
board/freescale/ls1043ardb/ls1043ardb.c | 8
include/configs/ls1043ardb.h| 7 +++
2 files changed, 15 insertions(+)
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c
b
QE-HDLC and USB multi-use the pins, when set "hwconfig=qe-hdlc",
assign the pins to QE-HDLC, if not, assgin to USB
Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
---
board/freescale/ls1043ardb/ls1043ardb.c | 54 -
1 file changed, 39 insertions(
qe-hdlc and usb multi-use the pins, when set hwconfig=qe-hdlc,
assign the pins to qe-hdlc, if not, assgin it to usb
Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
---
Changes for v2:
- NA
board/freescale/ls1043ardb/ls1043ardb.c | 54 -
1 file chang
Upload qe microcode on ls1043ardb
Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
---
Changes for v2:
- get qe_immr and qe_immr directly instead of from qe_base
board/freescale/ls1043ardb/ls1043ardb.c | 8
drivers/qe/qe.c | 6 ++
include/c
use "#ifdef CONFIG_QE" to mask the codes
not used for micro QE
Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
---
Changes for v2:
- this patch is new added to this patchset
drivers/qe/qe.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/qe/qe.c b/drive
This reverts commit 5066e62847bddf6030262ade2aa3e7bcdc930037.
The reverted patch will block t2080RDB iNiC, it was a workaround for
T2080QDS
down-training issue, we need to revert it and find the root cause for
T2080QDS
down-training issue.
Signed-off-by: Zhao Qiang <qiang.z...@nxp.
PBI_SRC=14 for IFC NAND boot
Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
---
Changes for v2:
- split to two patches
Changes for v3:
- modify commit msg, explain why modify the PBI_SRC.
.../t102xqds/{t1024_rcw.cfg => t1024_nand_rcw.cfg} | 0
...
FLUSH command is restricted to CCSR board. So use WAIT
command in case of non-CCSR board.
Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
---
Changes for v2:
- split to two patches
Changes for v3:
- modify commit msg
board/freescale/t208xqds/t208x_pbi.cfg | 3 +--
board/fre
PBL flush command is restricted to CCSR memory space.
So use WAIT PBI command to provide enough time for data to get flush in
target memory
Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
---
Changes for v2:
- split to two patches
Changes for v3:
- modify commit msg
Changes
PBI_SRC=14 for IFC NAND boot
Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
---
Changes for v2:
- split to two patches
Changes for v3:
- modify commit msg, explain why modify the PBI_SRC.
Changes for v4:
- modify commit msg
Changes for v5:
-
T series boards use unified RCW for sd, api and nand boot.
Now split txxx_rcw.cfg to txxx_sd_rcw.cfg, txxx_spi_rcw.cfg
and txxx_nand_rcw.cfg for SPI/NAND/SD boot.
Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
---
.../t102xqds/{t1024_rcw.cfg => t1024_nand_rcw.cfg} | 0
...
FLUSH command is restricted to CCSR space. So use WAIT
command in case of non-CCSR board.
Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
---
board/freescale/t208xqds/t208x_pbi.cfg | 3 +--
board/freescale/t208xrdb/t2080_pbi.cfg | 3 +--
board/freescale/t4qds/t4_pbi.cfg | 3 +--
FLUSH command is restricted to CCSR space. So use WAIT
command in case of non-CCSR board.
And split txxx_rcw.cfg to txxx_sd_rcw.cfg, txxx_spi_rcw.cfg
and txxx_nand_rcw.cfg for SPI/NAND/SD boot.
Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
---
.../t102xqds/{t1024_rcw.cfg => t1024_nan
PBL flush command is restricted to CCSR memory space.
So use WAIT PBI command to provide enough time for data to get flush in
target memory
Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
---
Changes for v2:
- split to two patches
Changes for v3:
- modify commit msg
Changes
PBI_SRC=14 for IFC NAND boot
Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
---
Changes for v2:
- split to two patches
Changes for v3:
- modify commit msg, explain why modify the PBI_SRC.
Changes for v4:
- modify commit msg
.../t102xqds/{t1024_r
modify u_qe_init to upload QE firmware from SD card when it is SD
boot
Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
---
Changes for v2:
- fix issue of memory leak
drivers/qe/qe.c | 37 -
include/configs/ls1043a_common.
modify u_qe_init to upload QE firmware from SD card when it is SD
boot
Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
---
drivers/qe/qe.c | 34 +-
include/configs/ls1043a_common.h | 4
include/configs/ls1043ardb.h | 7 ---
3
add if condition to check the return value, if 0, firmware is uploaded
successfully, then mark QE_IRAM as ready.
Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
---
drivers/qe/qe.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
QE_IRAM_READY should be set only after successfully uploading the
firmware.
Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
---
Changes for v2:
- modify commit msg to make it more understandable
drivers/qe/qe.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
modify u_qe_init to upload QE firmware from SD card when it is SD
boot
Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
---
Changes for v2:
- fix issue of memory leak
Changes for v3:
- add CONFIG_SYS_QE_FMAN_FW_IN_NOR to ls1021a
drivers/qe/qe.c
modify u_qe_init to upload QE firmware from SD card when it is SD
boot
Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
---
Changes for v2:
- fix issue of memory leak
Changes for v3:
- add CONFIG_SYS_QE_FMAN_FW_IN_NOR to ls1021a
Changes for v4:
- rebase due to memory-m
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