78cab an out of bound access occurs. See
> > below.
> >
> > On 11/4/15 10:48 PM, Andy Fleming wrote:
> > > This board runs a P5020 or P5040 chip, and utilizes
> > > an EEPROM with similar formatting to the Freescale P5020DS.
> > >
> > > Large am
On Thu, Jan 7, 2016 at 2:50 AM, Yangbo Lu wrote:
> Fill the right command type when using CMD12 to stop data transfer.
>
> Signed-off-by: Yangbo Lu
> ---
> Changes for v2:
> - Removed fix for T4160 because other patch had done that
> ---
> drivers/mmc/fsl_esdhc.c | 2 +-
> 1 file changed
If CONFIG_SYS_STDIO_DEREGISTER is not enabled, usb reset
will fail every time. Enabling it allows usb reset to
work.
Signed-off-by: Andy Fleming
---
include/configs/cyrus.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h
index bc7cac4
a/board/varisys/cyrus/cyrus.c
> +++ b/board/varisys/cyrus/cyrus.c
> @@ -20,7 +20,7 @@
> #include
>
> #include "cyrus.h"
> -#include "../common/eeprom.h"
> +#include
Acked-by: Andy Fleming
___
U-Boot mailin
Looks like one spot got missed. Probably due to the backslash.
Signed-off-by: Andy Fleming
---
Noticed this while reading up on the MAINTAINERS files
scripts/get_maintainer.pl | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/get_maintainer.pl b/scripts
This board runs a P5020 or P5040 chip, and utilizes
an EEPROM with similar formatting to the Freescale P5020DS.
Large amounts of this code were developed by
Adrian Cox
Signed-off-by: Andy Fleming
---
v3:
* Clarified sys_eeprom.c comments
* Removed errant whitespace
On Wed, Nov 4, 2015 at 12:39 PM, York Sun wrote:
>
>
> On 11/03/2015 03:30 PM, Andy Fleming wrote:
>> This board runs a P5020 or P5040 chip, and utilizes
>> an EEPROM with similar formatting to the Freescale P5020DS.
>>
>> Large amounts of this code were develop
This board runs a P5020 or P5040 chip, and utilizes
an EEPROM with similar formatting to the Freescale P5020DS.
Large amounts of this code were developed by
Adrian Cox
Signed-off-by: Andy Fleming
---
v2:
* Cleaned up sys_eeprom.c
* Removed CONFIG_CMD_ELF
On Fri, Oct 30, 2015 at 12:10 PM, York Sun wrote:
>
>
> On 10/21/2015 04:59 PM, Andy Fleming wrote:
>> This board runs a P5020 or P5040 chip, and utilizes
>> an EEPROM with similar formatting to the Freescale P5020DS.
>>
>> Large amounts of this code were develop
This board runs a P5020 or P5040 chip, and utilizes
an EEPROM with similar formatting to the Freescale P5020DS.
Large amounts of this code were developed by
Adrian Cox
Signed-off-by: Andy Fleming
---
arch/powerpc/cpu/mpc85xx/Kconfig | 4 +
board/varisys/common/Makefile| 23
The code is from Adrian Cox, and is patterned after similar
support in Linux (drivers/rtc/rtc-ds1307.c:1121-1135). This
chip is used on the Cyrus board from Varisys.
Signed-off-by: Andy Fleming
---
drivers/rtc/Makefile | 2 +-
drivers/rtc/ds1307.c | 34 ++
2
Much of this code is patterned off the P5020DS support.
The Cyrus board uses an MCP79411 rtc chip, so we add
support for that before adding the board.
Andy Fleming (2):
rtc: Add MCP79411 support to DS1307 rtc driver
mpc85xx: Add support for the Varisys Cyrus board
arch/powerpc/cpu/mpc85xx
15 at 03:56:09PM +, Joakim Tjernlund wrote:
>> > > > On Tue, 2015-10-06 at 11:17 +, Joakim Tjernlund wrote:
>> > > > > On Thu, 2015-10-01 at 08:57 +, Joakim Tjernlund wrote:
>> > > > > > On Wed, 2015-09-30 at 21:35 +0200, Marek Vasut
On Thu, Oct 1, 2015 at 9:18 AM, Wolfgang Denk wrote:
> Dear Andy,
>
> In message
> you
> wrote:
>>
>> > Given that GCC 4.9.1 apparently solves this issue I wonder which
>> > approach we should take?
> ...
>> Was there a resolution to this thread?
>
> No, there was no real resolution.
>
> My und
On Thu, Oct 23, 2014 at 8:10 AM, Wolfgang Denk wrote:
> Dear Joakim, dear Dirk,
>
> In message
> you
> wrote:
>>
>> Ouch, that was a nasty surprise.
>
> Indeed.
>
>> > In my original mail I referenced this potential solution, at least it
>> > worked for me:
>> > https://gcc.gnu.org/ml/gcc-help/
Messages to aflem...@freescale.com now bounce, and should be
directed to my personal address at aflem...@gmail.com
Signed-off-by: Andy Fleming
---
doc/feature-removal-schedule.txt | 2 +-
doc/git-mailrc | 2 +-
drivers/net/fm/memac_phy.c | 2 +-
drivers/net/fm/tgec_phy.c
On Fri, Jun 27, 2014 at 4:37 AM, Pantelis Antoniou <
pantelis.anton...@gmail.com> wrote:
> Hi Eli,
>
> On Jun 12, 2014, at 12:41 PM, Eli Billauer wrote:
>
> > The current wait loop just reads the status 1 times, which makes the
> > actual timeout period platform-dependent. The udelay() call wi
On Thu, Jun 12, 2014 at 4:41 AM, Eli Billauer wrote:
> The current wait loop just reads the status 1 times, which makes the
> actual timeout period platform-dependent. The udelay() call within the loop
> makes the new timeout ~100 ms.
>
> Signed-off-by: Eli Billauer
> ---
> drivers/mmc/sdhci
On Sun, Jun 15, 2014 at 7:46 PM, Otavio Salvador
wrote:
> This adds support to switch to 1.8V in case CMD11 succeeds.
>
> Signed-off-by: Otavio Salvador
> ---
>
> drivers/mmc/fsl_esdhc.c | 30 +++---
> include/fsl_esdhc.h | 2 ++
> include/mmc.h | 1 +
> 3
On Mon, Sep 2, 2013 at 7:30 AM, Christian Gmeiner <
christian.gmei...@gmail.com> wrote:
> This patch is needed if the MAC is directly connected to a ethernet switch.
> In my case the FEC MAC is connected to a Micrel KSZ8895. All I need to to
> is configure my fixed phy/link like:
>
> #define IMX_F
On Thu, Aug 8, 2013 at 10:39 AM, Tom Rini wrote:
> Hey all,
>
> I want to announce a few custodian changes. Andy Fleming is stepping
> down from both his PowerPC and MMC custodianships to go off and do
> something non-technical and fun for a while. I want to thank him for
>
On Mon, Jul 01, 2013 at 02:26:01PM +0800, Haijun.Zhang wrote:
> Fill the right command type when using CMD12 to stop data transfer.
>
> Signed-off-by: Haijun Zhang
> CC: Fleming Andrew-AFLEMING
> CC: Scott Wood
Applied to get the fix, though I don't like this sort of #ifdef.
_
On Mon, Jul 15, 2013 at 03:44:29PM +0200, Dirk Behme wrote:
> Dealing with the sys ctrl register should touch only the
> relevant bits and not accidently the whole register. On i.MX6,
> the sys control register contains bits which shouldn't be reset to
> 0, e.g. SYS_CTRL[3-0] and IPP_RST_N (SYS_CTR
be built for arches
> other than ARM. For ARM driver still builds without it.
>
> Signed-off-by: Alexey Brodkin
>
> Cc: Mischa Jonker
> Cc: Andy Fleming
> Cc: Rajeshwari Shinde
> Cc: Amar
> Cc: Minkyu Kang
> Cc: Jaehoon Chung
Applied, thanks!
Andy
___
The following changes since commit baa8841d6cc8a8cb79e0aee2fe1b360dacc05aaf:
arm:samsung:trats:fix: Restore proper orientation of TRATS's LCD panel
(2013-07-16 09:20:16 -0400)
are available in the git repository at:
git://www.denx.de/git/u-boot-mmc.git master
for you to fetch changes up to
arm:samsung:trats:fix: Restore proper orientation of TRATS's LCD panel
(2013-07-16 09:20:16 -0400)
are available in the git repository at:
git://www.denx.de/git/u-boot-mpc85xx.git master
for you to fetch changes up to 2a6936059a1f393d828274bf5d33dd54c0a3c882:
powerpc/mpc85xx:Disable Debu
On Fri, Jul 05, 2013 at 11:59:26AM +0530, Prabhakar Kushwaha wrote:
> CONFIG_SPL_BUILD creates debug TLB entry, so disable it before init_tlbs.
>
> CONFIG_SPL_INIT_MINIMAL never creates any debug TLB entry, so no need
> of disable_tlb().
>
> Signed-off-by: Prabhakar Kushwaha
Applied, thanks!
A
On Wed, Jun 26, 2013 at 03:55:17PM +0200, Dirk Eibach wrote:
> From: Dirk Eibach
>
> The gdsys ControlCenter Digital board is based on a Freescale P1022 QorIQ SOC.
> It boots from SPI-Flash but can be configured to boot from SD-card for
> factory programming and testing.
> On board peripherals in
On Wed, Jun 26, 2013 at 03:55:16PM +0200, Dirk Eibach wrote:
> From: Dirk Eibach
>
> MAKEALL is fine for ppc4xx and mpc85xx.
> Run checks were done on our controlcenterd hardware.
>
> Signed-off-by: Dirk Eibach
Applied, thanks!
Andy
___
U-Boot mail
On Wed, Jun 26, 2013 at 03:55:15PM +0200, Dirk Eibach wrote:
> From: Dirk Eibach
>
> Add support for Atmel TPM devices with two wire interface.
>
> Signed-off-by: Dirk Eibach
> Signed-off-by: Reinhard Pfau
> Reviewed-by: Simon Glass
Applied, thanks!
Andy
___
On Wed, Jun 26, 2013 at 03:55:13PM +0200, Dirk Eibach wrote:
> From: Reinhard Pfau
>
> Extend the tpm library with support for single authorized (AUTH1) commands
> as specified in the TCG Main Specification 1.2. (The internally used helper
> functions are implemented in a way that they could also
On Wed, Jun 26, 2013 at 03:55:14PM +0200, Dirk Eibach wrote:
> From: Reinhard Pfau
>
> if alen is 0: no longer start a write cycle before reading data.
>
> Signed-off-by: Dirk Eibach
> Signed-off-by: Reinhard Pfau
> Acked-by: Heiko Schocher
Applied, thanks!
Andy
___
On Sun, Jun 16, 2013 at 9:32 PM, Shengzhou Liu
wrote:
> SDHC pins are multiplexed with IFC and ULPI interfaces.
> This patch intends to enable SDHC function in case of
> NOR/NAND/SPI boot aside from SD boot.
>
> If "esdhc" is configured in hwconfig, u-boot will configure
> multiplexing pins from d
On Fri, Jun 14, 2013 at 4:14 AM, Wolfgang Denk wrote:
> Dear Kim,
>
> In message <1371198068-3581-1-git-send-email...@denx.de> you wrote:
> >
> > mpc8323erdb.c: In function 'mac_read_from_eeprom':
> > mpc8323erdb.c:198:3: warning: dereferencing type-punned pointer will
> > break strict-aliasing r
On Thu, Jun 27, 2013 at 9:33 PM, Zhang Haijun-B42677
wrote:
> Hi, Fleming
>
> ** **
>
> I found the root cause.
>
> Our driver didn’t make a distinction between different board for this
> register. (Just distinguish by esdhc version)
>
> On p1025 board watermark level was used both fo
This patch was
On Thu, Jun 27, 2013 at 5:03 PM, Tom Rini wrote:
> On Thu, Jun 20, 2013 at 04:04:21PM +0800, ying.zh...@freescale.com wrote:
>
> > From: Ying Zhang
> >
> > There will need the environment in SPL for reasons other than network
> > support (in particular, hwconfig contains info fo
On Thu, Jun 27, 2013 at 5:01 PM, Tom Rini wrote:
> On Fri, Jun 21, 2013 at 07:36:09AM +0200, Wolfgang Denk wrote:
> > Dear ying.zh...@freescale.com,
> >
> > In message <1371715468-21120-1-git-send-email-ying.zh...@freescale.com>
> you wrote:
> > >
> > > --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.l
On Thu, Jun 27, 2013 at 4:50 AM, Zhang Haijun-B42677
wrote:
> Hi, Fleming and Fabio
>
> Sorry to reply to you so late.
>
> As our manual described.
>
> In the eSDHC, the data buffer can hold up to 128 words (32-bit).
>
> The watermark levels for both write and read can be configured for CPU
> poll
On Fri, Jun 07, 2013 at 05:25:16PM +0800, ying.zh...@freescale.com wrote:
> From: Ying Zhang
>
> There will clear the BSS in the function clear_bss(), the reset address of
> the BSS started from the __bss_start, and increased by four-byte increments,
> finally stoped depending on the address is e
5707233880090f785c33df32c04549ea1aeef61e:
powerpc/85xx: Add P1023RDB board support (2013-06-20 17:08:53 -0500)
Andy Fleming (2):
85xx: Change clock-frequency compatible to 2.0
85xx: Change case of MPC85XX_PORBMSR_ROMLOC_SHIFT
On Fri, Jun 14, 2013 at 04:21:48PM +0800, Chunhe Lan wrote:
> P1023RDB Specification:
> ---
> Memory subsystem:
>512MB DDR3 (Fixed DDR on board)
>64MB NOR flash
>128MB NAND flash
>
> Ethernet:
>eTSEC1: Connected to Atheros AR8035 GETH PHY
>eTSEC2: Connected
On Sun, May 26, 2013 at 03:00:30PM +0800, Axel Lin wrote:
> If a variable is used as array subscript, it's valid value range is
> 0 ... ARRAY_SIZE -1.
>
> Signed-off-by: Axel Lin
Applied, thanks!
Andy
___
U-Boot mailing list
U-Boot@lists.denx.de
http
On Fri, May 31, 2013 at 08:48:04AM -0700, York Sun wrote:
> "pixis_reset help" command prints the message without a new line "\n",
> which makes the prompt on the same line.
>
> Signed-off-by: York Sun
Applied, thanks!
Andy
___
U-Boot mailing list
U-
On Mon, May 20, 2013 at 02:07:26PM +0800, ying.zh...@freescale.com wrote:
> From: Ying Zhang
>
> Move the common makefile line shared by the SPL and non-SPL to the public
> area,
> so that we can avoid excessive SPL symbols. Some of them will be used by the
> SPL later.
>
> This patch is on top
On Mon, May 20, 2013 at 02:07:25PM +0800, ying.zh...@freescale.com wrote:
> From: Ying Zhang
>
> There will need the environment in SPL for reasons other than network
> support (in particular, hwconfig contains info for how to set up DDR).
>
> Add a new symbol CONFIG_SPL_ENV_SUPPORT to replace C
On Mon, May 20, 2013 at 02:07:23PM +0800, ying.zh...@freescale.com wrote:
> From: Ying Zhang
>
> For SD/SPI 2-stage bootloader, the On-Chip Rom code loads the SPL into L2
> SRAM,
> then jump to it to begin execution. After that, the SPL loads the final uboot
> image into DDR, then jump to it to
On Fri, May 17, 2013 at 02:22:34PM +0530, Prabhakar Kushwaha wrote:
> PCIe TLB should be created with CONFIG_PCI defined
>
> Signed-off-by: Prabhakar Kushwaha
Applied, thanks!
Andy
___
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U-Boot@lists.denx.de
http://lists.denx.de/mai
On Tue, May 07, 2013 at 04:30:46PM +0800, Liu Gang wrote:
> Currently, the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" can enable
> the master module of Boot from SRIO and PCIE on a platform. But this
> is not a silicon feature, it's just a specific booting mode based on
> the SRIO and PCIE interf
On Tue, May 07, 2013 at 04:30:49PM +0800, Liu Gang wrote:
> T4 can support the feature of Boot from SRIO/PCIE, and the macro
> "CONFIG_SRIO_PCIE_BOOT_MASTER" will enable the master module of this feature
> when building the u-boot image.
>
> You can get some description about this macro in README
On Thu, May 16, 2013 at 10:18:13AM +0800, Mingkai Hu wrote:
> From: Mingkai Hu
>
> Calculate reserved fields according to IFC bank count
>
> 1. Move csor_ext register behind csor register and fix res offset
> 2. Move ifc bank count to config_mpc85xx.h to support 8 bank count
> 3. Guard fsl_ifc.h
On Fri, May 17, 2013 at 01:40:52PM +0530, Prabhakar Kushwaha wrote:
> Relax parameters to give address latching more time to setup.
>
> Signed-off-by: Prabhakar Kushwaha
Applied, thanks!
Andy
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.
On Wed, May 15, 2013 at 05:50:13PM -0500, Scott Wood wrote:
> Erratum A-006593 is "Atomic store may report failure but still allow
> the store data to be visible".
>
> The workaround is: "Set CoreNet Platform Cache register CPCHDBCR0 bit
> 21 to 1'b1. This may have a small impact on synthetic wri
On Tue, May 07, 2013 at 04:30:45PM +0800, Liu Gang wrote:
> 1. Misalignment will be found in the doc/README.srio-pcie-boot-corenet
>file when the tabs are set to 8 characters. And the standard for
>u-boot should be 8 character tabs! So this issue should be amended.
>
> 2. Add a NOTE for th
On Tue, May 07, 2013 at 04:30:47PM +0800, Liu Gang wrote:
> B4860QDS can support the feature of Boot from SRIO/PCIE, and the macro
> "CONFIG_SRIO_PCIE_BOOT_MASTER" will enable the master module of this feature
> when building the u-boot image.
>
> You can get some description about this macro in R
On Tue, May 07, 2013 at 11:19:55AM +0530, Prabhakar Kushwaha wrote:
> e500v2 processor does not support 8K page size TLB entries.
>
> So create new TLB entry only during NAND SPL boot.
>
> Signed-off-by: Prabhakar Kushwaha
Applied, thanks!
Andy
___
On Tue, May 07, 2013 at 04:30:48PM +0800, Liu Gang wrote:
> When a b4860qds board boots from SRIO or PCIE, it needs to finish these
> processes:
> 1. Set all the cores in holdoff status.
> 2. Set the boot location to one PCIE or SRIO interface by RCW.
> 3. Set a specific TLB entry
On Sun, Apr 21, 2013 at 01:11:02PM -0300, Fabio Estevam wrote:
> From: Fabio Estevam
>
> Freescale documentation presents the PowerPC core names in lower case, such as
> "e300", "e500", "e600", etc.
>
> Change the upper case occurrences into lower case so that the core names
> reported in U-boo
On Thu, Apr 18, 2013 at 07:31:01PM -0700, York Sun wrote:
> BSC9132 has 3 IFC banks.
>
> Signed-off-by: York Sun
Applied, thanks!
Andy
___
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http://lists.denx.de/mailman/listinfo/u-boot
On Tue, Apr 16, 2013 at 01:28:12PM +0530, Prabhakar Kushwaha wrote:
> - defines contants
> - Add spl_minimal.c to initialise DDR
> - update TLB entries as per NAND boot
> - remove nand_spl support for P1010RDB
>
> Signed-off-by: Prabhakar Kushwaha
Applied, thanks! Fixed typos in commit mes
On Tue, Apr 16, 2013 at 01:28:25PM +0530, Prabhakar Kushwaha wrote:
> - Add NAND boot target
>- defines contants
>- Add spl_minimal.c to initialise DDR
>- update TLB entries as per NAND boot
>
> Signed-off-by: Prabhakar Kushwaha
Applied, thanks! Fixed typo
Andy
On Tue, Apr 16, 2013 at 01:28:40PM +0530, Prabhakar Kushwaha wrote:
> - Add NAND boot target
>- defines contants
>- Add spl_minimal.c to initialise DDR
>- update TLB, LAW entries as per NAND boot
>
> Signed-off-by: Prabhakar Kushwaha
Applied, thanks! Fixed typo.
Andy
__
On Tue, Apr 16, 2013 at 01:27:59PM +0530, Prabhakar Kushwaha wrote:
> Linker script is not able find start.o binary. So add its absolute path in
> u-boot-spl.lds. This change is similar to u-boot-nand.lds
>
> common/Makefile: Avoid compiling unnecssary files
>
> fsl_ifc_spl.c : It is is responsib
On Tue, Apr 16, 2013 at 01:27:44PM +0530, Prabhakar Kushwaha wrote:
> IFC errata A003399 is valid for IFC NOR boot i.e.if no on-board NOR flash or
> no NOR boot, do not compile its workaround.
>
> Signed-off-by: Prabhakar Kushwaha
Applied, thanks!
Andy
_
On Thu, Apr 04, 2013 at 09:31:54AM +0530, Priyanka Jain wrote:
> BSC9131RDB is a Freescale Reference Design Board for
> BSC9131 SoC which is a integrated device that contains
> one powerpc e500v2 core and one DSP starcore.
>
> To support DSP starcore
> -Creating LAW and TLB for DSP-CCSR space.
> -
On Thu, Apr 04, 2013 at 02:40:32PM +0530, Priyanka Jain wrote:
> BSC9131RDB has 1GB DDR.
> Out of this, only 880MB is passed on to Linux via bootm_size.
> Remaining
> -16MB is reserved for PowerPC-DSP shared control area
> -128MB is reserved for DSP private area.
>
> Also 256MB, out of this 880MB
On Fri, Apr 12, 2013 at 03:56:28PM +0800, Mingkai Hu wrote:
> To avoid sign extension problem, use explicit casting to cast
> the SDRAM size to type phys_size_t, or else, if the SDRAM size
> is 2G(0x8000), it will be extended to 0x8000
> when phys_size_t is type 'unsigned long long'
On Mon, Apr 01, 2013 at 12:12:45PM +0530, Priyanka Jain wrote:
> BSC9131RDB supports Sysclk
> -66MHz if jumper J16 is close (default state)
> -100MHz if jumper J16 is open
>
> Add targets
> -BSC9131RDB_NAND_SYSCLK100 : for NAND boot at Sysclk 100MHz
> -BSC9131RDB_SPIFLASH_SYSCLK100: for SPI boot a
On Thu, Jun 13, 2013 at 10:14:00AM +0530, Prabhakar Kushwaha wrote:
> init_tlbs() initialize all the TLB entries required for the system.
>
> So disable DEBUG TLB entry before TLB entries initialization.
>
> Signed-off-by: Prabhakar Kushwaha
Applied, with fixes.
> diff --git a/arch/powerpc/cpu
On Tue, May 07, 2013 at 04:30:50PM +0800, Liu Gang wrote:
> When a T4 board boots from SRIO or PCIE, it needs to finish these processes:
> 1. Set all the cores in holdoff status.
> 2. Set the boot location to one PCIE or SRIO interface by RCW.
> 3. Set a specific TLB entry for the
On Mon, May 27, 2013 at 10:51:46AM +1200, Chris Packham wrote:
> From: Chris Packham
>
> Instead of assuming that SYS_TEXT_BASE is 0xFFF8 calculate the initial
> pbl command offset by subtracting the image size from the top of the
> 24-bit address range. Also increase the size of the memory b
On Thu, Apr 25, 2013 at 03:51:11PM +0800, Xie Xiaobo wrote:
> TWR-P1025 Specification:
> ---
> Memory subsystem:
>512MB DDR3 (on board DDR)
>64Mbyte 16bit NOR flash
>One microSD Card slot
>
> Ethernet:
>eTSEC1: Connected to Atheros AR8035 GETH PHY
>eTSEC3: C
On Wed, Jun 12, 2013 at 3:08 AM, wrote:
> From: Dirk Eibach
>
> MAKEALL is fine for ppc4xx and mpc85xx.
> Run checks were done on our controlcenterd hardware.
>
> Signed-off-by: Dirk Eibach
>
>
> Signed-off-by: Dirk Eibach
>
You don't need two sign-offs.
Does anyone have comments on these pa
On Fri, Jun 7, 2013 at 4:25 AM, wrote:
> From: Ying Zhang
>
> Support to boot from spi flash.
>
> This patch is on top of the patch:
> powerpc/p1022ds: boot from SD Card with SPL
>
> Signed-off-by: Ying Zhang
> ---
> board/freescale/p1022ds/spl.c | 12 +-
> drivers/mtd/spi/Makefile
On Tue, Jun 18, 2013 at 12:54 PM, Scott Wood wrote:
> On 06/18/2013 10:37:02 AM, Timur Tabi wrote:
>
>> On Tue, Jun 18, 2013 at 5:39 AM, wrote:
>> > From: Ying Zhang
>> >
>> > Support TPL on the P1022DS.
>>
>> Please define "TPL". I have no idea what it is.
>>
>
> Third Program Loader. An add
On Thu, Apr 25, 2013 at 4:07 AM, wrote:
> Hi, experts:
> MIPI(Mobile Industry Processor Interface) has defined many mobile device
> interface.
> Such as:
> CSI --- for Camera
> DSI --- for Display
>
> It seems DSI has samples on Exynos board.(in drivers\video directory)
> I want to know the statu
On Wed, Apr 24, 2013 at 2:14 AM, Po Liu wrote:
> From: Mingkai Hu
>
> The Freescale C29x family is a high performance crypto co-processor.
> It combines a single e500v2 core with necessary SEC engine. There're
> three SoC types(C291, C292, C293) with the following features:
>
> - 512K L2 Cache/
On Wed, Apr 24, 2013 at 2:14 AM, Po Liu wrote:
> From: Mingkai Hu
>
> C29XPCIE board is a series of Freescale PCIe add-in cards to perform
> as public key crypto accelerator or secure key management module. It
> includes C293PCIE board, C293PCIE board and C291PCIE board.
>
> - 512KB platform SR
> --- a/arch/powerpc/cpu/mpc85xx/fdt.c
> +++ b/arch/powerpc/cpu/mpc85xx/fdt.c
> @@ -492,7 +492,7 @@
> if (!p)
> return;
>
> - fmanfw = (struct qe_firmware *) simple_strtoul(p, NULL, 0);
> + fmanfw = (struct qe_firmware *) simple_strtoul(p, NULL, 16);
> if (!fmanfw)
> return;
>
Could you s
On Mon, Jun 17, 2013 at 7:07 AM, Kuo-Jung Su wrote:
> From: Kuo-Jung Su
>
> This updates ftsdc010_mci.c for latest Faraday clock APIs.
>
> Signed-off-by: Kuo-Jung Su
> CC: Albert Aribaud
> CC: Andy Fleming
>
Acked-by: Andy Fleming
Since this is part of a series,
The following changes since commit 077becc345717c3cf32e88316298b74d0cff6581:
Merge branch 'master' of git://git.denx.de/u-boot-74xx-7xx (2013-06-11
18:11:47 -0400)
are available in the git repository at:
git://www.denx.de/git/u-boot-mmc.git master
for you to fetch changes up to 91171091c6
On Tue, Jun 11, 2013 at 03:14:02PM -0600, Stephen Warren wrote:
> From: Stephen Warren
>
> A negative value of CONFIG_ENV_OFFSET is treated as a backwards offset
> from the end of the eMMC device/partition, rather than a forwards offset
> from the start.
>
> This is useful when a single board ma
On Tue, Jun 11, 2013 at 03:14:01PM -0600, Stephen Warren wrote:
> From: Stephen Warren
>
> Enhance the MMC core to calculate the size of each MMC partition, and
> update mmc->capacity whenever a partition is selected. This causes:
>
> mmc dev 0 1 ; mmcinfo
>
> ... to report the size of the curr
On Tue, Jun 11, 2013 at 03:14:03PM -0600, Stephen Warren wrote:
> From: Stephen Warren
>
> Use a negative value of CONFIG_ENV_OFFSET for all NVIDIA reference boards
> that store the U-Boot environment in the 2nd eMMC boot partition. This
> makes U-Boot agnostic to the size of the eMMC boot partit
On Tue, Jun 11, 2013 at 03:14:00PM -0600, Stephen Warren wrote:
> From: Stephen Warren
>
> Describe the meaning of CONFIG_ENV_IS_IN_MMC, and all related defines that
> must or can be set when using that option.
>
> Signed-off-by: Stephen Warren
> Reviewed-by: Peter Korsgaard
> Acked-by: Tom Ri
On Tue, Jun 11, 2013 at 10:34:22AM -0500, Andrew Gabbasov wrote:
> After waiting for the command completion event, the interrupt status
> bits, that occured to be set by that time, are cleared by writing them
> back. It is supposed, that it should be command related bits (command
> complete and may
> The same problem occurs if the "mmc write" command is given with a block
> count being 0.
>
> By adding a check for the block count being zero in mmc_write_blocks
> (drivers/mmc.c), this problem is solved.
>
> Signed-off-by: Ruud Commandeur
> Cc: Tom Rini
> C
On Tue, May 21, 2013 at 03:01:36PM +0530, Jagannadha Sutradharudu Teki wrote:
> CAP register don't have any information for 8-bit buswidth support
> on 2.0 sdhci spec, only from 3.0 onwards bit[18] got this information.
>
> Due to this misassignment in sdhci, mmc is setting 8-bit buswidth using
>
gt; http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/160247
>
> Signed-off-by: Hatim Ali
> Signed-off-by: Rajeshwari Shinde
> Acked-by: Simon Glass
> Tested-by: Simon Glass
> Acked-by: Jaehoon Chung
Acked-by: Andy Fleming
Looks like the patch this is based on is alre
On Wed, May 15, 2013 at 09:38:16AM +0800, Bo Shen wrote:
> The commit d196bd8 (env_mmc: add support for redundant environment)
> introduce the following compile error when enable redundant
> environment support with MMC
> ---8<---
> env_mmc.c:149: error: 'env_t' has no member named 'flags'
> env_mm
On Tue, May 28, 2013 at 03:09:42PM -0300, Fabio Estevam wrote:
> Since commit 48e0b2bd (powerpc/esdhc: Correct judgement for DATA PIO mode)
> we see mx6 systems to hang after doing a 'save' command.
>
> Revert this commit since the original 'ifdef' logic from 7b43db92
> (drivers/mmc/fsl_esdhc.c:
On Mon, Jun 10, 2013 at 8:45 AM, Wolfgang Denk wrote:
> Some systems use a SoM (system on module) in such a way that the PHY
> addresses depend on the carrier board used, or even on the geographic
> position of the SoM on the carrier board. This patch adds support for
> runtime assignment of the
The following changes since commit 53237afe5b64abe7b17fbfed958f3dc83f503ffa:
cmd_mem: fix cp command (2013-05-24 10:38:08 -0400)
are available in the git repository at:
git://www.denx.de/git/u-boot-mpc85xx.git master
for you to fetch changes up to a71d45d706a5b51c348160163b6c159632273fed:
On Thu, May 23, 2013 at 5:27 PM, Andy Fleming wrote:
>
>
>
> On Tue, Apr 16, 2013 at 2:58 AM, Prabhakar Kushwaha <
> prabha...@freescale.com> wrote:
>
>>- Add NAND boot target
>>- defines contants
>>- Add spl_minimal.c to initialise DDR
&
On Tue, Apr 16, 2013 at 2:58 AM, Prabhakar Kushwaha wrote:
>- Add NAND boot target
>- defines contants
>- Add spl_minimal.c to initialise DDR
>- update TLB entries as per NAND boot
>
> Signed-off-by: Prabhakar Kushwaha
>
I'm currently applying your SYSCLK change which depends o
On Thu, Mar 28, 2013 at 5:46 AM, Ruchika Gupta
wrote:
> PAMU driver basic support for usage in Secure Boot.
> In secure boot PAMU is not in bypass mode. Hence to use
> any peripheral (SEC Job ring in our case), PAMU has to be
> configured.
>
> The Header file fsl_pamu.h and few functions in driver
On Thu, May 16, 2013 at 4:26 AM, Ruud Commandeur wrote:
> > Assuming this is necessary, I think it then might be time to
> > reorder this:
> >
> > if (!blkcnt) <-- possibly at the very start of the function.
> > return 0;
> >
> > if (blkcnt == 1)
> > cmd.cmdidx = MMC_CMD_WRITE_SINGLE_BLOCK;
The following changes since commit fb651b10d43be36e7d7e16704c4b5ea1e295587a:
Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx (2013-05-15
08:41:04 -0400)
are available in the git repository at:
git://www.denx.de/git/u-boot-mmc.git master
for you to fetch changes up to 48e0b2b
On Wed, May 15, 2013 at 2:02 AM, wrote:
> From: Ying Zhang
>
> Add the symbol CONFIG_SPL_BUILD_MINIMAL for the minimal SPL. It used to
> eliminate code unused in the minimal SPL but used in the SPL.
>
> This patch is on top of the following patch:
> 1. common/Makefile: Add new symbol CONFIG_SPL_
On Tue, May 14, 2013 at 8:38 PM, Bo Shen wrote:
> The commit d196bd8 (env_mmc: add support for redundant environment)
> introduce the following compile error when enable redundant
> environment support with MMC
> ---8<---
> env_mmc.c:149: error: 'env_t' has no member named 'flags'
> env_mmc.c:248
On Wed, May 15, 2013 at 9:23 AM, Ruud Commandeur wrote:
> This patch fixes a number of mmc and fat-related bugs:
>
> > Added a check for blkcnt > 0 in mmc_write_blocks (drivers/mmc.c) to
> prevent a hangup for further mmc commands.
>
You need more information than that. Why is some code request
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