building and testing, I get ACK timeouts on the controlport bus.
Jeff
From: Hodges, Jeff via USRP-users
Sent: Monday, September 20, 2021 3:09 PM
To: Wade Fife ; Rob Kossler
Cc: usrp-users@lists.ettus.com
Subject: [USRP-users] Re: rfnoc 4.0 gain block tutorial --> register problem
Rob/Wade,
Th
this would cause.
Rob
On Mon, Sep 13, 2021 at 1:07 PM Hodges, Jeff via USRP-users
mailto:usrp-users@lists.ettus.com>> wrote:
I'm now convinced there is something majorly wrong with UHD4.0 controlport.
Not only am I experiencing the issue I have described here but if I create an
image wit
From: Hodges, Jeff via USRP-users
Sent: Monday, September 13, 2021 11:48:06 AM
To: usrp-users@lists.ettus.com
Subject: [USRP-users] Re: rfnoc 4.0 gain block tutorial --> register problem
I can read and write from register addr 0x0 but the default value read from
peek32(0x0) i
I can read and write from register addr 0x0 but the default value read from
peek32(0x0) is 0 regardless of what I set the REG_USER_DEFAULT value to.
This only occurs on register addr 0x0.
Jeff
From: Hodges, Jeff via USRP-users
Sent: Saturday, September 11
Following the gain block tutorial from GRCON20, when I read from the registers
using gain_block->regs().peek32(0x0), the default value that is return is not
the same as set during reset. The default value I read is always 0 even when my
verilog sets it to some other value after rebuilding the
Has this issue been resolved?
If I export the UHD_MODULE_PATH = the .so file it will find the gain block, but
it prints a bunch of error strings trying to open every file in the directory.
If I do not set the UHD_MODULE_PATH, I cannot find the block. How can I get
around this? I’m trying to
How many rfnoc Computation Engines (CEs) are available on the N3xx radios
FPGAs? For example, i read online that the x3xx has 16 CEs.
How does the tuning speed compare between the N2xx and N3xx radios? I saw a
whitepaper a few years back that listed the max sustained hop rate of the
N210+WBX
On the AXI Bus, what is the the behavior of data_tready? Does it go low at the
conclusion of each packet? If not, how long after de-asserting data_tvalid is
it allowable to re-assert data_tvalid and begin another packet?
Thanks,
Jeff
___
USRP-users
I am using the standard X310 HG image running a simple flow graph with one
dma_FIFO as follows, and the flowgraph freezes after approximately 800,000
samples:
signal_source --> throttle --> dma_fifo --> timesink
However, if I put an RFNOC block in, it works:
signal_source --> throttle -->
ry packet consumed. The different input/output
packet lengths do not matter as AXI wrapper internally calculates the output
packet length and updates the header automatically.
Jonathon
On Fri, Dec 11, 2020 at 3:48 PM Hodges, Jeff via USRP-users
mailto:usrp-users@lists.ettus.com>> wrote:
I meant
, Dec 11, 2020 at 3:48 PM Hodges, Jeff via USRP-users
mailto:usrp-users@lists.ettus.com>> wrote:
I meant rfnoc_create_verilog.py
https://github.com/EttusResearch/uhd/blob/master/host/utils/rfnoc_blocktool/rfnoc_create_verilog.py
jeff
From: Hodges, Jef
I meant rfnoc_create_verilog.py
https://github.com/EttusResearch/uhd/blob/master/host/utils/rfnoc_blocktool/rfnoc_create_verilog.py
jeff
From: Hodges, Jeff
Sent: Friday, December 11, 2020 3:44:41 PM
To: usrp-users@lists.ettus.com
Subject: RFNoC passing
I'd like to pass metadata over the dataplane using the available space in the
CHDR header. However, I cannot find an easy way to do this using UHD3.15.
I've identified two possible approaches but I'm not sure either will work:
(1) Set AXI_Wrapper (Simple_Mode =0) to require user provided CHDR
I have a lab set-up where I remotely run uhd_image_loader on my X310, but then
I need to power-cycle the device in order for the new image to be used.
Does the uhd driver have a command that will do this? or can this be done by
the aux IO or JTAG? or do I need to buy a remote power switch?
in the
gr-UHD API, and if you were just using the straight Python programming model
you could use them directly.
Sent from my iPhone
On Oct 27, 2020, at 12:25 PM, Hodges, Jeff via USRP-users
wrote:
How do I get the device sptr (::uhd::usrp::multi_usrp::sptr) from the
usrp_sink_block sptr
How do I get the device sptr (::uhd::usrp::multi_usrp::sptr) from the
usrp_sink_block sptr?
For example, the following works:
basic_block_sptr blk =
global_block_registry.block_lookup(pmt::intern(usrp_alias));
d_usrp =
boost::dynamic_pointer_cast(blk);
But
, Hodges, Jeff via USRP-users wrote:
I'm thinking that timed tune commands will not work on tagged streams in burst
mode. Is that correct? I've been looking at the USRP sink block code and it
supports the timed commands on the stream, but from reading a recent thread, it
seems like this will not work
I'm thinking that timed tune commands will not work on tagged streams in burst
mode. Is that correct? I've been looking at the USRP sink block code and it
supports the timed commands on the stream, but from reading a recent thread, it
seems like this will not work because of how the DUC derives
Hi, I've built my own RFNoC block and everything works fine, except the
tx_dc_offset is -40 dBc at all times, which seems pretty high. I tried to
follow the example from another user, since I have the same setup with my UBX
in the second slot (B) but I get the error:
>> uhd_cal_tx_dc_offset
Hodges, Jeff via USRP-users
mailto:usrp-users@lists.ettus.com>> wrote:
Has anyone been able to transmit with RFNoC Radio using the standard FPGA image
from UHD.3.15.LTS?
I have a clean installation and ran SigGen --> RFNoC: DmaFIFO --> RFNoC: DUC
--> RFNoC: Radio
Most basic
_0.set_tx_gain(0, 0)
File "/usr/local/lib/python2.7/dist-packages/ettus/ettus_swig.py", line 3235,
in set_tx_gain
return _ettus_swig.rfnoc_radio_sptr_set_tx_gain(self, gain, chan)
RuntimeError: _Map_base::at
Jeff
____________
From: USRP-users on behalf of Ho
I get a set_tx_gain error running a basic signal generator through RFNoC Radio:
Signal Source -> DMA FIFO -> DUC -> Radio (See image below)
This is equivalent to:
Signal Source --> USRP Sink(Works fine)
https://kb.ettus.com/File:dma_fifo_v02.png
Cherif,
Did you install gr-ettus? Unless you are using UHD on master branch (4.0), you
need gr-ettus. I installed UHD3.15LTS on Ubuntu 18.04 without PYBOMBS and it
works fine.
Jeff
From: USRP-users on behalf of Marcus
Müller via USRP-users
Sent: Tuesday,
@lists.ettus.com
Subject: Re: [USRP-users] uhd_image_loader bricked my x310
On 06/03/2020 08:16 PM, Hodges, Jeff via USRP-users wrote:
The uhd_image_loader seems to have bricked my x310!
Prior to running it, the device was connected fine but after running the
script, it loaded to 100% and said
The uhd_image_loader seems to have bricked my x310!
Prior to running it, the device was connected fine but after running the
script, it loaded to 100% and said to recycle power. After recycling power, the
USRP will no longer connect to my computer. The LINK light does not come on and
the
_HG] Error 2
Thanks,
Jeff
From: USRP-users
mailto:usrp-users-boun...@lists.ettus.com>>
On Behalf Of Hodges, Jeff via USRP-users
Sent: Thursday, May 21, 2020 11:50 AM
To: Michael Dickens
mailto:michael.dick...@ettus.com>>
Cc: usrp-users@lists.ettus.com<mailto:usrp-users@lis
locktool/rfnoc_create_verilog.py". - MLD
---
Michael Dickens
Ettus Research Technical Support
Email: supp...@ettus.com<mailto:supp...@ettus.com>
Web: https://ettus.com/
On Thu, May 28, 2020 at 11:54 PM Hodges, Jeff via USRP-users
mailto:usrp-users@lists.ettus.com>> wrote:
I also w
l: supp...@ettus.com<mailto:supp...@ettus.com>
Web: https://ettus.com/
On Thu, May 28, 2020 at 11:54 PM Hodges, Jeff via USRP-users
mailto:usrp-users@lists.ettus.com>> wrote:
I also would like to know the answer to Rob’s question:
Rfnocmodtool is in gr-ettus but if I try to install gr-ettu
I also would like to know the answer to Rob’s question:
Rfnocmodtool is in gr-ettus but if I try to install gr-ettus with the uhd
master branch, I get the following error:
[ 5%] Building CXX object lib/CMakeFiles/gnuradio-ettus.dir/device3.cc.o
In file included from
gpio_fix
}}}
---
Michael Dickens
Ettus Research Technical Support
Email: supp...@ettus.com<mailto:supp...@ettus.com>
Web: https://ettus.com/
On Thu, May 21, 2020 at 11:35 AM Hodges, Jeff via USRP-users
mailto:usrp-users@lists.ettus.com>> wrote:
I apologize for my ignorance, which of these
On Behalf Of Hodges, Jeff
via USRP-users
Sent: Wednesday, May 27, 2020 1:02 PM
To: usrp-users@lists.ettus.com
Subject: [USRP-users] rfnoc gain tutorial block freezing on testbench TEST CASE
5
I am getting the same error as Pratik:
http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2018
I am getting the same error as Pratik:
http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2018-September/057930.html
When I run the testbench, it is gets stuck on TEST CASE 5.
I have used rfnocmodtool to create the tutorial and added a gain block. I have
downloaded the files directly
When I run ./uhd_image_builder_gui.py, the GUI cannot select the makefile.src
from my OOT block. The file is grayed-out when I try to select it from the OOT
directory: {USER_PREFIX}/src/{USER-OOT-moddir}/rfnoc/fpga-srcs/
In addition, it gives the following warning message, which may or may not
rch Technical Support
Email: supp...@ettus.com<mailto:supp...@ettus.com>
Web: https://ettus.com/
On Thu, May 21, 2020 at 11:35 AM Hodges, Jeff via USRP-users
mailto:usrp-users@lists.ettus.com>> wrote:
I apologize for my ignorance, which of these is the LTS tag?
git tag -l
003_00
To: usrp-users@lists.ettus.com
Cc: Hodges, Jeff
Subject: Re: [USRP-users] rfnoc build standard image x310 failing
I think you want to be using the UHD-3.15.LTS tag.
- Ryan
From: USRP-users
mailto:usrp-users-boun...@lists.ettus.com>>
On Behalf Of Hodges, Jeff via USRP-user
:35 PM Hodges, Jeff via USRP-users
mailto:usrp-users@lists.ettus.com>> wrote:
Can someone please tell me what version of uhd and rfnoc are compatible for
building an image on Ubuntu 18.04?
I cannot get any of the UHD releases to properly build a standard rfnoc image.
sudo ./uhd_image_buil
Can someone please tell me what version of uhd and rfnoc are compatible for
building an image on Ubuntu 18.04?
I cannot get any of the UHD releases to properly build a standard rfnoc image.
sudo ./uhd_image_builder.py fft ddc duc -g -t X310_RFNOC_HG -c -d X310
--fill-with-fifos
I installed
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