On 04/09/2018 02:48 PM, Matis Alun via USRP-users wrote:
>
> Le 09/04/2018 à 23:20, Martin Braun via USRP-users a écrit :
>> On 04/09/2018 07:35 AM, Matis Alun via USRP-users wrote:
>>> Hi everybody,
>>>
>>> I saw that a /tmp/uhd.log is created when running a sampling program and it
>>> is
On 04/10/2018 04:27 PM, Martin Braun wrote:
> On 04/10/2018 09:14 AM, Rob Kossler via USRP-users wrote:
>> Hi,
>> Within the last couple of weeks, the N310 tree went from having 1 front
>> end to 2 front ends per daughterboard (A,B,C, or D). What is the reason
>> for this? Why would the user
On 04/10/2018 09:14 AM, Rob Kossler via USRP-users wrote:
> Hi,
> Within the last couple of weeks, the N310 tree went from having 1 front
> end to 2 front ends per daughterboard (A,B,C, or D). What is the reason
> for this? Why would the user want to choose subdev spec "A0" as opposed
> to "A1"
*
*** NEWSDR at WPI on Thr/Fri May 3/4 ***
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On 04/10/2018 06:49 AM, ALEJANDRO BLANCO PIZARRO wrote:
Hi all, Marcus,
I continue trying to generate the square signal as a clock but now by
means of a FPGA.
The square signal, that I generated, has *a period of 100 ns and a Vpp
of 0.65 V (in attached). *These values are correct in order
Hi,
Within the last couple of weeks, the N310 tree went from having 1 front end
to 2 front ends per daughterboard (A,B,C, or D). What is the reason for
this? Why would the user want to choose subdev spec "A0" as opposed to
"A1" and same for other paths?
I attached the uhd_usrp_probe results
Hello. I use B200 to scan the spectrum in a certain band. I have two
problems.
1) the last part of the collection of the spectrum becomes the beginning. Fig.
1
2) the switching time from frequency to frequency is alternated
0.00305509567261
0.0539989471436
0.00493001937866
0.054967880249
Hi,
is there any updates on supporting Ubuntu 17? Currently installation of
NI-USRP 15.0 driver fails on Ubuntu due to changes in the kernel. The
driver is necessary to use X310 PCIe interface.
thanks,
Dmitry
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Hi all, Marcus,
I continue trying to generate the square signal as a clock but now by means
of a FPGA.
The square signal, that I generated, has *a period of 100 ns and a Vpp of
0.65 V (in attached). *These values are correct in order to feed a USRP?
Thanks in advance. Best regards,
Alejandro
Hi everyone,
I want to control the AD9361 in USRP B210 using external host, how can I do it?
What are the steps and procedures I have to do?
I am using Xilinx ISE 14.7 and Ubuntu.
Thanks in advance!
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Dear community,
I implemented C++ codes of the transmitter and receiver using UHD API,
starting from example provided by Ettus.
Until now, I'm testing my codes using a coax cable for connecting the
USRPs (a USRP used as transmitter and a USRP used as receiver).
In this setup, just before
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