On 07/31/2018 11:14 PM, Young C. Park wrote:
Hi Marcus,
Thanks for the reply.
But the situation is, I see a lot of underflow when the sample rate is
100MHz (yes, the MCR is 200MHz), whereas it works ok with 50MHz.
The buffer size does not change the underflow when it's set lower than
:
Hi Marcus,
Thanks for the reply.
But the situation is, I see a lot of underflow when the sample rate is
100MHz (yes, the MCR is 200MHz), whereas it works ok with 50MHz.
The buffer size does not change the underflow when it's set lower than :
samps_per_buff = tx_stream->get_max_num_samps();
Any
On 07/31/2018 10:21 PM, Young C. Park via USRP-users wrote:
Hi, I would like to make sure about the bandwidth and sampling rate on
X310.
Say, I have 2channel, 1000 complex f32 samples to be sent by X310,
over 10GbE.
The wire format is sc16.
As far as I understand, f32 (64bit IQ) is converted
Hi, I would like to make sure about the bandwidth and sampling rate on X310.
Say, I have 2channel, 1000 complex f32 samples to be sent by X310, over
10GbE.
The wire format is sc16.
As far as I understand, f32 (64bit IQ) is converted to sc16 (32bit IQ)
Then the time for the transmission will be :
On 07/31/2018 02:40 PM, Sirkin, Joshua F. via USRP-users wrote:
Has sc8 capability been added to the X310? I know it the past it hasn't but
this page seems to indicate sc8 is generally implemented
https://files.ettus.com/manual/structuhd_1_1stream__args__t.html. We have an
X310 with a
Hassna,
you can't build RFNoC images with Vivado_Lab. You need the full Vivado.
-- M
On 07/31/2018 12:14 PM, Ouassal, Hassna via USRP-users wrote:
> Hello,
>
>
>
> I ma wokring through "Build custom image with pre-built RFNoC blocks"
>
>
> I am running the following script:
>
>
On 07/31/2018 11:40 AM, Sirkin, Joshua F. via USRP-users wrote:
> Has sc8 capability been added to the X310? I know it the past it hasn't but
> this page seems to indicate sc8 is generally implemented
> https://files.ettus.com/manual/structuhd_1_1stream__args__t.html. We have an
> X310 with a
Found the problem. Was using the wrong adapter.
On Sun, Jul 29, 2018 at 9:07 PM, Sayyed Dormiani Tabatabaei <
sdorm...@eng.ucsd.edu> wrote:
> I just followed the online KB guide exactly (I think). I have a successful
> serial connection and RJ45 connection.
>
> Here is the output from
Hello,
I ma wokring through "Build custom image with pre-built RFNoC blocks"
I am running the following script:
hassna@hassna-desktop:~/rfnoc/src/uhd-fpga/usrp3/tools/scripts$
./uhd_image_builder_gui.py
--Using the following blocks to generate image:
* window
* fft
Adding CE
Has sc8 capability been added to the X310? I know it the past it hasn't but
this page seems to indicate sc8 is generally implemented
https://files.ettus.com/manual/structuhd_1_1stream__args__t.html. We have an
X310 with a UBX-160 daughter card and are having trouble getting the full
What I don't understand is, why is the null sink able to have one input and no
outputs? I would think that it would suffer the same issues that a 2-in 1-out
block would have.
I tried to understand the noc_block_null_source_sink.v, but I didn't really see
how to use it as a sink only. I was
Hi Farnaz,
Regarding #1, the USRP can be either Tx, Rx, or both, but it does not
affect maximum streaming rates. The 10Gbe link is bi-directional and can
handle a maximum of 300 MS/s on a single link in both directions. You can
use both links such that you can receive both channels of the X310
Dear Rob,
1. Can you explain if the USRP may be configured only in receive/transmit
mode or is it also possible to configure in a single mode (a pure
transmitter or a pure receiver) using both optical interfaces for the task?
2. In the first remark in your email, you mentioned that the
Hi Andreas,
The timekeeper lives inside of the Radio block. However, after looking more
into the code, the DUC and DDC do already read the timestamp data from the
CHDR packets. You could modify the DUC and DDC to use the timestamp data to
jump the phase accumulator's value to compensate for the
Thank you Derek for the explanations,
As workaround I will have to send continuously.
Just a curiosity, as I am very new in rfnoc development: Where is the
timing of the bursts done in the FPGA? In the DmaFIFO block? And would
it be possible to modify this block such that it sends zeros while
Hello,
a question that keeps popping up on the list: is there a way to tag samples
within RFNoC such that it can be processed in GNU Radio?
In earlier discussions, the EOB bit was suggested for such purposes:
http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2016-June/020733.html
But
Hey Jon,
Is it possible to connect this block to an RFNoC port and not use it? Use
others.
2018-07-31 4:49 GMT+02:00 Jon Pendlum via USRP-users <
usrp-users@lists.ettus.com>:
> Hey Jason,
>
> The block is functionally complete, in fact I think it was the first
> block ever made. There is a UHD
Fabian and Derek,
Thanks for your comments,
Yesterday I realized that 10GbE could not support my 100MSymps, complex
dual channel output.
That's why I've seen underflow messages. I actually have got around this
underflow by putting (ms) delay between bursts.
However, it seems like that there's
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