Le 11/04/2018 à 02:16, Martin Braun via USRP-users a écrit :
> On 04/09/2018 02:48 PM, Matis Alun via USRP-users wrote:
>> Le 09/04/2018 à 23:20, Martin Braun via USRP-users a écrit :
>>> On 04/09/2018 07:35 AM, Matis Alun via USRP-users wrote:
Hi everybody,
I saw that a /tmp/uhd.log
Hey everybody,
I was able to make an example block by installing uhd+gr-ettus with PyBombs
rfnoc-devel recipes, then using rfnocmodtool, generating .xml and .v files, and
then "compiling and installing" the block from the previously generated
makefiles.
I also included the block in the FPGA code,
Hi all,
In this Ettus UHD Manual page:
http://files.ettus.com/manual/page_calibration.html#calibration_self_utils
It is written to "*Disconnect* any external hardware from the RF antenna
ports" before executing the calibration tool.
Q: What is the exact reason for disconnecting external h/w from
Hi all,
How do we set up the Ad9361_driver and ad9361 controls in the
uhd/host/lib/usrp/common file for Ubuntu? What are the steps and prerequisites
for this?
Thank you in advance!
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What exactly do you want to do?
On Wed, Apr 11, 2018 at 6:33 PM Yeo Jin Kuang Alvin (IA) via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Hi all,
>
>
>
> How do we set up the Ad9361_driver and ad9361 controls in the
> uhd/host/lib/usrp/common file for Ubuntu? What are the steps and
> prerequ
Hi,
I have the FPGA source code using Xilinx ISE 14.7, I want to output a signal
out that is generated from the FPGA, however I suppose I have to control the
AD9361 to get an output out to transmit unless I am wrong.
Thanks in advance!
From: Nick Foster [mailto:bistrom...@gmail.com]
Sent: Thur
On 04/11/2018 09:08 PM, Serge Malo via USRP-users wrote:
Hi all,
In this Ettus UHD Manual page:
http://files.ettus.com/manual/page_calibration.html#calibration_self_utils
It is written to "*Disconnect*any external hardware from the RF
antenna ports" before executing the calibration tool.
Q:
The best option is probably to use existing UHD commands to set the gain,
frequency, master clock rate, etc., while modifying the image to generate
the transmit signal in the FPGA rather than in the host.
Nick
On Wed, Apr 11, 2018 at 6:41 PM Yeo Jin Kuang Alvin (IA) <
yjink...@dso.org.sg> wrote:
I have been fighting for a day with issues on my N200s and N210s to no
avail. These were working units, but are giving me the following:
$ uhd_usrp_probe
[INFO] [UHD] linux; GNU C++ version 4.8.5 20150623 (Red Hat 4.8.5-16);
Boost_105300; UHD_3.11.0.0-34-g4844f66d
[ERROR] [UHD] Exception caught in
Hi,
Sorry I am very new to all these, do you mean that I have to download visual
studio to compile all the UHD .cpp and run them for the UHD commands? And for
the FPGA image you talking about, is it the .bit file that is generated in the
IMPACT?
Thank you in advance!
From: Nick Foster [mailto
On Wed, Apr 11, 2018 at 10:15 PM Yeo Jin Kuang Alvin (IA) <
yjink...@dso.org.sg> wrote:
> Hi,
>
>
>
> Sorry I am very new to all these, do you mean that I have to download
> visual studio to compile all the UHD .cpp and run them for the UHD
> commands?
>
No, I mean that you can probably just get
Hi,
Thank you! Btw will the FPGA image be ‘overlap’ after running the UHD software
or they can both run concurrently?
Thank you in advance!
From: Nick Foster [mailto:bistrom...@gmail.com]
Sent: Thursday, 12 April 2018 1:28 PM
To: Yeo Jin Kuang Alvin (IA)
Cc: usrp-users@lists.ettus.com
Subject:
They are both necessary and serve completely separate and complementary
functions. At this point you are best served by reading the documentation.
Nick
On Wed, Apr 11, 2018, 10:33 PM Yeo Jin Kuang Alvin (IA)
wrote:
> Hi,
>
>
>
> Thank you! Btw will the FPGA image be ‘overlap’ after running the
Thank you! :D
From: Nick Foster [mailto:bistrom...@gmail.com]
Sent: Thursday, 12 April 2018 1:38 PM
To: Yeo Jin Kuang Alvin (IA)
Cc: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] AD9361 in USRP B210
They are both necessary and serve completely separate and complementary
functions. At this
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