On 09/18/2011 04:43 PM, Bertold Van den Bergh wrote:
> Hello,
>
> Thanks for the reply. The timer register has the following layout: bit
> 0-15: reload, bit 16-31: counter. Thats why I put 0x. Looking
> at the code this cannot work so I added an extra field to indicate the
> shift after ap
On 09/18/2011 04:43 PM, Bertold Van den Bergh wrote:
> Hello,
>
> Thanks for the reply. The timer register has the following layout: bit
> 0-15: reload, bit 16-31: counter. Thats why I put 0x. Looking
> at the code this cannot work so I added an extra field to indicate the
> shift after ap
Hello,
Thanks for the reply. The timer register has the following layout: bit
0-15: reload, bit 16-31: counter. Thats why I put 0x. Looking
at the code this cannot work so I added an extra field to indicate the
shift after applying the mask.
Now the userspace latency test prorgam gives va
On 09/17/2011 05:15 PM, Bertold Van den Bergh wrote:
> Hello,
>
> I am trying to port Xenomai to the freescale stmp3xxx cpu (I.MX233).
>
> I added TSC code from plat-s3c24xx as this processor also uses a 16
> bit downcounter based timer. I run the system tick counter and the TSC
> freerunning cou
