Hi, and welcome :)
On Tue, May 22, 2012 at 11:09:18PM +0200, Iztok Jeras wrote: > Dumps: > > I have access to a logic analyzer at work, and I have a USB/UART based > 1-Wire master, and the FPGA based master mentioned above. I also have > several 1-Wire devices (thermometers, ADC, GPIO, memory). I can create Yes, various dumps for all those devices would be great, each in an extra subdir in onewire/ in the sigrok-dumps repo, and each with a detailed README of which device it is, what traffic is going over the wire, which LA/samplerate/probes were used etc. etc. I've not merged your current sigrok-dumps stuff though, that also contains VHDL stuff and shell scripts etc. which are not relevant for the sigrok-dumps repo (should only contain .sr files and README). Feel free to make another branch/clone with just those *.sr/README files, we'll pull that in then. And/or I can manually commit your current .sr file, but then your name won't be in the git log. > some dumps, but I need some help with the conversion to *.sr files, > since I do not have access to a sigrok compatible device. Currently I > have created some binary files (using Verilog simulation), I can > probably also export from the logic analyzer into binary (I have not > tried yet). Currently I use the next command line: > $ sigrok-cli -i onewire.bin -I binary -p 1=OWR -o onewire.sr > The problem with the output file is that it is missing a sample rate. > How could I specify it? That's not possible at the moment, sorry. The 'binary' input module hardcodes 8 probes (and various other stuff) and has no samplerate. We'll need to add options for the input format so you can specify samplerate and other values, but that's not implemented, yet. > https://github.com/jeras/sigrok-dump/tree/master/onewire/verilog > > Protocol decoder: > > I started writing the protocol decoder. > https://github.com/jeras/sigrok/tree/master/libsigrokdecode/decoders/onewire Great, thanks! I've pulled in the decoder (after a "git rebase origin/master"). Please always try to keep your changed on top of the current master, if possible (not a big deal, though). If you continue working in your branch you probably need to "force-push" once now due to my rebase. And/or it's probably easier if you don't work in the "master" branch, but rather keep that at the current "upstream" state always. Instead, make another "onewire" (or whatever name) branch with your changed, probably makes things a bit easier. > But I have issues debugging it. Currently I run configure, "make" and > "sudo make install". I was able to run the decoder, but the given > error did not help much. How do you debug this decoders (while I've fixed a few smaller issues, but the main problem was that you used in some places %d instead of %s. The error is more useful now: srd: Calling decode() on all instances with starting sample number 0, 3480 bytes at 0x0x16d7f80 srd: Calling decode() on instance onewire with 3480 bytes starting at sample 0. srd: Protocol decoder instance onewire: Exception: Invalid lnk_state: WAIT FOR NEGEDGE You can use "-l 5" as option for sigrok-cli for maximum debug output. > developing them)? I would like to see the Python error trace, if > possible, and avoid installing. I usually just do 'make install' in libsigrokdecode, that doesn't take much time at all if you only change .py files. I have libsigrok installed in $HOME/sr (or some other temp. dir) and libsigrokdecode and sigrok-cli, too, and run it from there: ~/sr/bin/sigrok-cli -i onewire.sr -a onewire:owr=0 -l 5 (do "./configure --prefix=$HOME/sr ..." when installing the first time) Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org ------------------------------------------------------------------------------ Live Security Virtual Conference Exclusive live event will cover all the ways today's security and threat landscape has changed and how IT managers can respond. Discussions will include endpoint security, mobile security and the latest in malware threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/ _______________________________________________ sigrok-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/sigrok-devel
