Hi, On Tue, Jul 03, 2012 at 12:33:17AM +0200, Iztok Jeras wrote: > The 1-Wire protocol decoder should be almost ready now, this week I > will add some more dumps and test the decoder with them. The code is > ready for a first review, next issues remain:
Thanks, merged for now with a few minor changes and quite a bunch of rebasing and git fixups, though. > 1. Annotations: > Currently there are 3 annotation options, for three protocol layers > (link, network, transport), but this separation does not work well > with sigrok, since the display of annotations should overlap. I will > probably update this after running through some more example dumps. This should change anyway, as there is a clear layer system in this protocol(stack), we certainly want one protocol decoder per layer (at least) and then stack them. In this case, something like this would probably make sense (example): onewire_link -> onewire_network -> ds18s20 As you mention below the transport layer (and possibly others) can be device-specific. In those cases a generic decoder should only do generic decoding, all device-specific knowledge and decoding should happen in a respective decoder for that device. Example: We certainly want a 'ds18s20' decoder, which takes (I guess) onewire_network as input, which in turn takes onewire_link as input, which in turn has raw signal values as input. Whether or not a 'onewire_transport' PD makes sense, depends on how much non-device-specific stuff would be in there, need to look into the spec and some datasheets to check. > 2. Overdrive support: > Overdrive support was not tested yet, although all the needed code > should be present. Sounds good, haven't tested anything though. I think I might have some 1-Wire devices here, will try to make a few additional dumps for the repo, so you have some more files to test against. > 3. Transport layer: > The transport layer is very device specific although there are some > common aspects. For now I decided not to decode this protocol layer > and to only display transported data bytes. I think this is good > enough for the first release. Yup. But see above for plans for later versions. > 4. White space: > I have my own preferences regarding white space, I prefer long lines > with vertically aligned keywords. Could you please apply the preferred > formatting to the source while merging it? I'll have a run over the code and fix various issues, both functional and coding-style/whitespace, just let me know when I should do it -- before or after we split the PD into multiple ones? Also, do you want to do the splitting, or should I give it a go? > sigrok-dump GIT is here (master branch): > https://github.com/jeras/sigrok-dump > The Verilog dump generators, and Tektronix text dumps with the > converter were deleted from GIT, but remain in the history. Thanks, I picked and merged the files themselves for now (without history). If you really want the scripts etc. to be in sigrok-dumps (not sure if that is really relevant there, though), feel free to post another patch which adds them to a onewire/owfs/scripts subdir or so. Otherwise, I suggest you put them in an extra 'my_vhdl_stuff' or such repo on your github account, as it's technically not really sigrok-related. Thanks for your continued work on this PD! Cheers, Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org ------------------------------------------------------------------------------ Live Security Virtual Conference Exclusive live event will cover all the ways today's security and threat landscape has changed and how IT managers can respond. Discussions will include endpoint security, mobile security and the latest in malware threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/ _______________________________________________ sigrok-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/sigrok-devel
