The current implementation of the ASIX Sigma firmware download contains
comments which express uncertainty. Rephrase them, no magic is involved.
Discuss the polarity of the CCLK hardware signal. Which shall eliminate
potential concerns in future reviews or maintenance.
Put an explicit "EMPTY" marker in an empty loop body. To reflect that
nothing is missing, and that the empty body is intended.
This commit only updates comments, and does not change behaviour.
Signed-off-by: Gerhard Sittig <gerhard.sit...@gmx.net>
---
Remark: Ondrej @ASIX confirmed that CCLK is inverted in hardware, and
that DIN vs CCLK setup times are not violated on Sigma models.
---
src/hardware/asix-sigma/protocol.c | 25 ++++++++++++++++---------
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/src/hardware/asix-sigma/protocol.c
b/src/hardware/asix-sigma/protocol.c
index 5fa7b2d015a1..9965f24cbc21 100644
--- a/src/hardware/asix-sigma/protocol.c
+++ b/src/hardware/asix-sigma/protocol.c
@@ -383,44 +383,51 @@ static int sigma_fw_2_bitbang(struct sr_context *ctx,
const char *name,
{
size_t i, file_size, bb_size;
char *firmware;
uint8_t *bb_stream, *bbs;
uint32_t imm;
int bit, v;
int ret = SR_OK;
+ /* Retrieve the on-disk firmware file content. */
firmware = sr_resource_load(ctx, SR_RESOURCE_FIRMWARE,
name, &file_size, 256 * 1024);
if (!firmware)
return SR_ERR;
- /* Weird magic transformation below, I have no idea what it does. */
+ /* Unscramble the file content (XOR with "random" sequence). */
imm = 0x3f6df2ab;
for (i = 0; i < file_size; i++) {
imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
firmware[i] ^= imm & 0xff;
}
/*
- * Now that the firmware is "transformed", we will transcribe the
- * firmware blob into a sequence of toggles of the Dx wires. This
- * sequence will be fed directly into the Sigma, which must be in
- * the FPGA bitbang programming mode.
+ * Generate a sequence of bitbang samples. With two samples per
+ * FPGA configuration bit, providing the level for the DIN signal
+ * as well as two edges for CCLK. See Xilinx UG332 for details
+ * ("slave serial" mode).
+ *
+ * Note that CCLK is inverted in hardware. That's why the
+ * respective bit is first set and then cleared in the bitbang
+ * sample sets. So that the DIN level will be stable when the
+ * data gets sampled at the rising CCLK edge, and the signals'
+ * setup time constraint will be met.
+ *
+ * The caller will put the FPGA into download mode, will send
+ * the bitbang samples, and release the allocated memory.
*/
-
- /* Each bit of firmware is transcribed as two toggles of Dx wires. */
bb_size = file_size * 8 * 2;
bb_stream = (uint8_t *)g_try_malloc(bb_size);
if (!bb_stream) {
sr_err("%s: Failed to allocate bitbang stream", __func__);
ret = SR_ERR_MALLOC;
goto exit;
}
-
bbs = bb_stream;
for (i = 0; i < file_size; i++) {
for (bit = 7; bit >= 0; bit--) {
v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00;
*bbs++ = v | 0x01;
*bbs++ = v;
}
}
@@ -498,7 +505,7 @@ static int upload_firmware(struct sr_context *ctx,
/* Discard garbage. */
while (sigma_read(&pins, 1, devc) == 1)
- ;
+ /* EMPTY */;
/* Initialize the FPGA for logic-analyzer mode. */
ret = sigma_fpga_init_la(devc);
--
1.9.1
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