On Fri, 2022-12-02 at 19:51 +0100, Markus Heidelberg wrote:
>
> I found a problem with importing wrong values from CSV files when
> 0.0 voltage was given.
>
> clear_analog_samples() didn't clear, so old buffer content existed.
> I noticed it by sporadic peaks in low bus signal (around 0 voltage).
>
> https://github.com/sigrokproject/libsigrok/pull/201
Got example data to reproduce? Helps others review that change,
improves the odds of having it go mainline. Could even be part of
the commit message when "the file" only got a few lines of text.
There is prior art in some of the src/input/ modules.
virtually yours
Gerhard Sittig
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