Am Freitag, 2. Dezember 2022, 20:56:45 CET schrieb Gerhard Sittig: > On Fri, 2022-12-02 at 19:51 +0100, Markus Heidelberg wrote: > > I found a problem with importing wrong values from CSV files when > > 0.0 voltage was given. > > > > clear_analog_samples() didn't clear, so old buffer content existed. > > I noticed it by sporadic peaks in low bus signal (around 0 voltage). > > > > https://github.com/sigrokproject/libsigrok/pull/201 > > Got example data to reproduce? Helps others review that change, > improves the odds of having it go mainline. Could even be part of > the commit message when "the file" only got a few lines of text.
I attached an example file. However, more than 2^19 samples are needed for the bug to become effective, so it couldn't be smaller. > There is prior art in some of the src/input/ modules. Didn't understand that part. Markus _______________________________________________ sigrok-devel mailing list sigrok-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/sigrok-devel
