On 9/6/13 7:32 AM, Timothe Litt wrote:
This is all a matter of how you account for the cycles. The instruction must be fetched. The source must be read. And the destination must be written. These all cause some sort of cycle - whether or not it appears on the external bus.
Non-processor requests will also effect how often you can get out the Unibus. I remember the VT11 being a particularly bad bus hog. Massbus disks and I would think comms processors would be a problem too. I would imagine this would be a huge win for even the smallest caches to try keeping the CPU off of the Unibus. _______________________________________________ Simh mailing list [email protected] http://mailman.trailing-edge.com/mailman/listinfo/simh
