On 2013-09-06 17:07, Al Kossow wrote:
On 9/6/13 7:32 AM, Timothe Litt wrote:
This is all a matter of how you account for the cycles. The
instruction must be fetched. The source must be read. And the
destination must be written. These all cause some sort of cycle -
whether
or not it appears on the external bus.
Non-processor requests will also effect how often you can get out the
Unibus.
I remember the VT11 being a particularly bad bus hog. Massbus disks and
I would think comms processors would be a problem too.
I would imagine this would be a huge win for even the smallest caches to
try
keeping the CPU off of the Unibus.
Indeed.
And I just realized/remembered one more thing about the separate memory
bus thingy. One could also argue that the memory on the 11/24 and 11/44
are on a separate memory bus, since these machines also have 22-bit
addressing for memory, which cannot be done over the Unibus. However,
they share parts of the signals with the Unibus, so for those machines,
it does not really offload the bus in any way.
Johnny
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